Related Manuals for Excalibur Excalibur EPXA1
Summary of Contents for Excalibur Excalibur EPXA1
-
Page 1: Epxa1 Development Board
EPXA1 Development Board Hardware Reference Manual September 2002 Version 1.1 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com MNL-EPXA1DEVBD-1.1... - Page 2 Copyright 2002 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S.
-
Page 3: About This Manual
About this Manual ® This manual provides comprehensive information about the Altera EPXA1 development board. Table 1 shows the manual revision history. Table 1. Revision History Date Description August 2002 First publication September 2002 Minor amendments How to Find The Adobe Acrobat Find feature allows you to search the contents of a PDF file. -
Page 4: How To Contact Altera
Altera literature services lit_req@altera.com (1) lit_req@altera.com (1) Non-technical customer (800) 767-3753 (408) 544-7000 service (7:30 a.m. to 5:30 p.m. Pacific Time) FTP site ftp.altera.com ftp.altera.com Note: You can also contact your local Altera sales office or sales representative. Altera Corporation... -
Page 5: Typographic Conventions
The checkmark indicates a procedure that consists of one step only. The hand points to information that requires special attention. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Altera Corporation... - Page 6 Notes:...
-
Page 7: Table Of Contents
Contents About this Manual ..................iii How to Find Information ......................iii How to Contact Altera ........................iv Typographic Conventions ......................v EPXA1 Development Board ................9 Features .............................9 Functional Overview ........................9 EPXA1 Development Board Components .................10 EPXA1 Device .........................10 Prototyping Area ........................11 Interfaces ..........................13... - Page 8 Contents Excalibur EPXA1 Development Board Hardware Refewrence Manual Anti-Static Handling ......................48 Power Consumption ......................48 Test Core Functionality ......................49 Unused I/O Pins ........................50 viii Altera Corporation...
-
Page 9: Epxa1 Development Board
In addition, the board can be used for system prototyping, emulation, hardware and software development or other special requirements. The development board provides a flexible, powerful debug and development environment to support the development of systems using Excalibur ™ devices. Altera Corporation... -
Page 10: Epxa1 Development Board Components
Table 1 on page 10 lists the main features of the device. Table 1. EPXA1 Device Features Feature Capacity Maximum system gates 263,000 Typical gates 100,000 4,160 ESBs Maximum RAM bits 53,248 Maximum macrocells Maximum user I/O pins Altera Corporation... -
Page 11: Prototyping Area
3.3-V and 5-V supply, plus ground connections, 32 I/O pins that facilitate connection to the Excalibur device, and a reset pin in a 6 × 15 matrix. Figure 2 shows the prototyping area on the development board. Altera Corporation... - Page 12 EPXA1 Development Board Hardware Reference Manual Figure 2. Prototyping Area on the EPXA1 Development Board Figure 3 on page 13 shows how the pins are located in the prototyping area. Altera Corporation...
-
Page 13: Interfaces
EBI Expansion headers These headers are used to connect Altera daughter cards or customer- designed daughter cards to develop and test custom circuitry IEEE Std. 488 RS-232 serial interfaces This is a 250-kbps true RS-232 data terminal equipment (DTE) interface... - Page 14 Table 5. UART LEDs Board Signal Description Reference This LED indicates activity on the line This LED indicates activity on the line This LED indicates activity on the line XA-TXD This LED indicates activity on the line XA-RXD Altera Corporation...
- Page 15 Data Lines Control Lines Memory Organization Size 4 M × 16 × 4 banks SDR SDRAM 32 Mbytes; 16-bit 2 × 4 Mbytes Flash 8 Mbytes Figure 4 on page 16 shows the location of the on-board memory. Altera Corporation...
- Page 16 Two flash memory chips, FLASH1 and FLASH2, are connected to the EBI of the EPXA1 development board (see Figure Figure 5. Flash Memory Interface Flash Memory (2 x 4 Mbyte) EBI_CS0 EBI_CS1 EPXA1 A1-A22 A0-A21 PHY/MAC FLASH1 FLASH2 D0-D15 OE, WE, CE Altera Corporation...
- Page 17 On the EPXA1 development board, there are ten user-definable LEDs in a graph-type LED package, DG1. They connect directly to the EPXA1 device I/O pins and can be used for any kind of application. Table 8 on page 18 lists the user LEDs on the development board. Altera Corporation...
- Page 18 5-V power indicator VCC_5V 3.3-V power indicator VCC_3V3 1.8-V power indicator VCC_1V8 indicator FPGA UART signal indicator FPGA UART signal Embedded stripe UART signal indicator XA-TXD Embedded stripe UART signal indicator XA-RXD Ethernet signal indicator Ethernet signal indicator Altera Corporation...
- Page 19 Active-low switch that generates a full power-on reset NPOR when pressed for more than two seconds Active-low switch that generates a warm reset N_CONFIG Table 12. User-Definable Push-Button Switches Push Button EPXA1 I/O Pin Signal Voltage (V) USER_PB0 USER_PB1 USER_PB2 USER_PB3 Altera Corporation...
-
Page 20: Development Board Expansion
Pin 1 The expansion header interfaces can be used to interface to special- function daughter cards; contact your Altera representative for details of the daughter cards available for use with the expansion header interfaces. By using the EPXA1 I/O pins and the power-supply pins on the... - Page 21 The maximum current load on each header is 500 mA at 3.3 V, 50 mA at 5 V and 100 mA at 12 V The remaining pins on the expansion headers connect to user I/O pins on the EPXA1 device. Table 24 on page 34 lists the expansion header signal pin assignments Altera Corporation...
- Page 22 EPXA1 device signals available to the standard expansion header interface. The definitions are used with Altera daughter cards. The general purpose I/O signals can be used as required. Table 13. Standard Expansion Header Signal Definitions...
-
Page 23: Jumper Configuration
Figure 8. Jumper Locations on the EPXA1 Development Board JSELECT (J5) CLKA Select CLKB Select (J13) (J14) Table 15 on page 24 lists the jumper settings and their uses. Altera Corporation... -
Page 24: Clocks
Socket for alternative 5-V DIL14 crystal oscillator, XSKT1 Generator clock input via SMA connector, SMA1 The location of the clocks on the development board is shown in Figure Figure 9. Clocks on the EPXA1 Development Board Altera Corporation... - Page 25 CLKLK_ENA Clock-enable for PLL circuitry; permanently on EPXA1 CLKLK_ENA CLKLK_OUT2p U22 CLKLK_OUT2p Dedicated pin allowing PLL2 output to be driven Standard off-chip, providing the PLL clock to the expansion expansion headers as H5V_CLK header, Long expansion header Altera Corporation...
-
Page 26: Jumper Configuration For The Clock Inputs
EPXA1 device. During development, if you need to run the clock at a rate other than 25 MHz, you can do so using the SMA connector or an alternative 5-V DIL14 oscillator. Altera Corporation... -
Page 27: Sources For The Stripe Clock Reference
To select the SMA connector, follow the steps below: Remove any alternative 5-V DIL14 oscillator from the socket, XSKT1. Apply an external clock source to the SMA connector. The clock signal should be a maximum 5 V Set CLKA Select to position 2-3. Altera Corporation... -
Page 28: Sources For Clk3 & Clk4
16-bit flash memory. Booting from Flash Memory The Altera flash memory programmer (exc_flash_programmer.exe) is a utility that allows you to program flash memory on the EBI using the JTAG interface and the ByteBlasterMV or MasterBlaster download cable, so that you can boot from it. -
Page 29: Using The Quartus Ii Software
Figure 10. JTAG Interfaces on the EPXA1 Development Board JTAG connectors (pin 1s indicated) The JTAG connector, J6, is used to connect an Altera ByteBlaster or MasterBlaster download cable. The Multi-ICE connector, J8, is used to connect a Multi-ICE cable or any other compatible cable. Altera Corporation... -
Page 30: Power Supply
The JSELECT jumper, J5, determines whether a JTAG debugger can be connected to the JTAG connector or to the Multi-ICE connector. When using Altera-RDI via a ByteBlasterMV or MasterBlaster cable, the JSELECT jumper must be set to 2-3; when using Multi-ICE or a compatible device on the Multi-ICE connector, JSELECT must be set to 1-2. - Page 31 The typical power-supply requirement for the development board is 250 mA/500 mA. Table 19. 12-V Supply Requirements Module Max mA Expansion headers 100 per header Table 20. 5-V Supply Requirements Module Max mA Alternative crystal oscillator—75 CLK_REF 50 per header Expansion headers Altera Corporation...
-
Page 32: Test Points & Test Pads
Test points on the EPXA1 development board, annotated as TPx, are provided for voltages and ground connections; see Table 35 on page Test Pads For selected signals, test pads are provided on the board, annotated as Tx; they are listed in Table 36 on page Altera Corporation... -
Page 33: Signals
Signal ground Data set ready Request to send Clear to send Ring indicator Note: The EPXA1 development board has two DB9 male connectors. Table 33 on page 44 lists pin-out information for the UARTs on the development board. Altera Corporation... -
Page 34: Expansion Headers
B_H5V_IO2 B_H5V_IO24 Removed B_H5V_IO3 B_H5V_IO4 B_H5V_IO16 B_H5V_IO25 B_H5V_IO5 B_H5V_IO26 B_H5V_IO6 B_H5V_IO17 B_H5V_IO27 B_H5V_IO7 H5_CS_N B_H5V_IO8 B_H5V_IO18 B_H5V_IO28 B_H5V_IO9 B_H5V_IO10 B_H5V_IO19 B_H5V_IO11 B_H5V_IO20 Table 39 on page 48 lists pin-out information for the standard expansion header on development board. Altera Corporation... - Page 35 VCC_3V3 20 × 2 Header, J9 H5_RST_N B_H5V_IO12 B_H5V_IO21 B_H5V_IO13 B_H5V_IO0 B_H5V_IO14 B_H5V_IO22 B_H5V_IO1 B_H5V_IO15 B_H5V_IO23 B_H5V_IO2 B_H5V_IO24 Removed B_H5V_IO3 B_H5V_IO4 B_H5V_IO16 B_H5V_IO25 B_H5V_IO5 B_H5V_IO26 B_H5V_IO6 B_H5V_IO17 B_H5V_IO27 B_H5V_IO7 H5_CS_N B_H5V_IO8 B_H5V_IO18 B_H5V_IO28 B_H5V_IO9 B_H5V_IO10 B_H5V_IO19 B_H5V_IO11 B_H5V_IO20 Altera Corporation...
- Page 36 B_eup_A7 B_eup_A13 B_eup_D1 B_eup_D7 B_eup_D13 B_eup_A2 B_eup_A8 B_eup_A14 B_eup_D2 B_eup_D8 B_eup_D14 B_eup_A3 B_eup_A9 B_eup_A15 B_eup_D3 B_eup_D9 B_eup_D15 B_eup_A4 B_eup_A10 B_eup_D4 B_eup_D10 Table 38 on page 47 lists pin-out information for the long expansion header on the development board. Altera Corporation...
-
Page 37: Configuration/Debugging Interfaces
6 GND Ground 7 PROC_TMS Processor test mode select Input 8 GND Ground 9 PROC_TCK Processor test clock input Input 10 GND Ground 11 GND Ground 12 GND Ground 13 PROC_TDO Processor test data output 14 GND Ground Altera Corporation... -
Page 38: Development Board Pin-Outs
Pin assignments are grouped into tables for control pins, address pins, and data bus pins where appropriate. The tables also detail signals passing across a connection. The remaining I/O pins on the EPXA1 device are listed at the end of this section. Altera Corporation... -
Page 39: Configuration
J8.7 JTAG mode select PROC_TMS J8.3 JTAG reset (pulled high) PROC_TRST T15, T14 FPGA clear signal taken to test pad T15, placed next to DEV_CLR_n grounded test pad T14 near SW1; allows use of this signal, if required Altera Corporation... -
Page 40: Sdr Sdram Interface
Data byte mask SD_DQM[0] U13.39 Data byte mask SD_DQM[1] Read data strobe input in SDR mode SD_DQS[0](1) Not used SD_DQM_ECC Note: These pins are tied together to provide a data-read strobe. See the Excalibur Devices Hardware Reference Manual. Altera Corporation... - Page 41 U13.48 U13.50 SD_DQ12 SD_DQ13 U13.51 U13.53 SD_DQ14 SD_DQ15 U13.23 U13.24 SD_A0 SD_A1 U13.25 U13.26 SD_A2 SD_A3 U13.29 U13.30 SD_A4 SD_A5 U13.31 U13.32 SD_A6 SD_A7 U13.33 U13.34 SD_A8 SD_A9 U13.22 U13.35 SD_A10 SD_A11 U13.36 U13.20 SD_A12 SD_A13 U13.21 SD_A14 Altera Corporation...
-
Page 42: Ebi
FLASH2.29 EBI_DQ0 U9.108 FLASH1.31 FLASH2.31 EBI_DQ1 U9.107 FLASH1.33 FLASH2.33 EBI_DQ2 U9.106 FLASH1.35 FLASH2.35 EBI_DQ3 U9.104 FLASH1.38 FLASH2.38 EBI_DQ4 U9.103 FLASH1.40 FLASH2.40 EBI_DQ5 U9.102 FLASH1.42 FLASH2.42 EBI_DQ6 U9.101 FLASH1.44 FLASH2.44 EBI_DQ7 U9.78 FLASH1.30 FLASH2.30 EBI_DQ8 U9.77 FLASH1.32 FLASH2.32 EBI_DQ9 Altera Corporation... - Page 43 EBI_A13 U9.93 FLASH1.3 FLASH2.3 EBI_A14 U9.94 FLASH1.2 FLASH2.2 EBI_A15 FLASH1.1 FLASH2.1 EBI_A16 FLASH1.48 FLASH2.48 EBI_A17 FLASH1.17 FLASH2.17 EBI_A18 FLASH1.16 FLASH2.16 EBI_A19 FLASH1.15 FLASH2.15 EBI_A20 FLASH1.10 FLASH2.10 EBI_A21 FLASH1.9 FLASH2.9 EBI_A22 A9 (not used) EBI_A23 G10 (not used) EBI_A24 Altera Corporation...
-
Page 44: Uart1 & Uart2
EPXA1 fast I/O pins, which are used as expansion header clock inputs. Table 34. EPXA1 Fast I/O Pins EPXA1 Pin Name Board Signal Description EPXA1 Pin Expansion Header Card Connector FAST1 Dedicated fast I/O pin J3.13 H5V_CLKOUT FAST4 Dedicated fast I/O pin J10.13 H5V_CLKOUT Altera Corporation... -
Page 45: Test Points
EBI write enable JTAG clock Ethernet loopback active output JTAG data output EBI output enable JTAG mode select EBI chip-select 0 JTAG data input EBI chip-select 2 Feedback clock to PLL2 EBI byte enable 0 25-MHz clock EBI chip-select 1 Altera Corporation... -
Page 46: Prototyping Area
VCC_5V VCC_3V3 protoIO_21 (L17) protoIO_11 (M20) protoIO_1 (R22) VCC_5V VCC_3V3 protoIO_20 (L18) protoIO_10 (M21) NC VCC_5V VCC_3V3 NC VCC_5V VCC_3V3 NC protoIO_32 (AA19) VCC_5V VCC_3V3 NC protoIO_31 (AA20) VCC_5V VCC_3V3 NC protoIO_30 (AB19) VCC_5V VCC_3V3 NC RESET_n (H4) Altera Corporation... -
Page 47: Expansion Header I/O Pins
J4.8 J9.25 J2.18 J4.9 J9.27 J2.19 J4.10 J9.28 J2.20 J4.11 J9.29 J2.21 J4.12 J9.31 J2.22 J4.13 J9.32 J2.23 J4.14 J9.33 J2.24 J9.3 J9.35 J2.25 J9.4 J9.36 J2.26 J9.5 J9.37 J2.29 J9.6 J9.39 J2.30 J9.7 H5_CS_N (J15.38) J2.31 J9.8 Altera Corporation... -
Page 48: General Usage Guidelines
The board’s typical operating current while running diagnostics is approximately 250 mA. A 20-W power supply is supplied as part of the EPXA1 development kit. It is capable of meeting the maximum power requirement imposed by the board if all interfaces are used within specification. Altera Corporation... -
Page 49: Test Core Functionality
When held down, SW5 toggles the 9th LED When held down, SW4 toggles the 10th LED When held down, SW3 inverts the current setting of all the LEDS SW2 shifts all the LEDS right (as viewed) by one place Altera Corporation... -
Page 50: Unused I/O Pins
Choose Compile Mode (Processing menu). Choose Compiler Settings (Processing menu). Click the Chips & Devices tab. Click Device & Pin Options. Click the Unused Pins tab. Select As inputs, tri-stated. Click Apply. Altera Corporation...
Need help?
Do you have a question about the Excalibur EPXA1 and is the answer not in the manual?
Questions and answers