Summary of Contents for Inova PD00941013.001
- Page 1 ICP-CM ® ® Intel Celeron M Low Power CPU Boards USER’S MANUAL Publication Number: PD00941013.001 AB MAN-ICP-CM...
- Page 2 The content of this user’s manual is furnished for informational use only, is subject to change without notice, and should not be constructed as a commitment by Inova Computers GmbH. Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that may appear in this user’s manual.
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Page 3: Table Of Contents
1.32 Windows 2000 (Professional) ... 1-9 1.33 Linux ... 1-9 1.34 VentureCom ... 1-9 1.35 Windows CE ... 1-10 1.36 VxWorks ... 1-10 1.37 OS-9 x86 ... 1-10 1.38 QNX ... 1-10 1.39 Jbed ... 1-10 Doc. PD00941013.001 ©2004 Inova Computers GmbH Preface Page 0-1... - Page 4 Table 2.40 DMA Channel Description ... 2-7 2.5 Inova CM SMB Devices ... 2-8 Table 2.50 SMB Devices ... 2-8 2.6 Inova CM PCI Device List ... 2-9 Table 2.60 Legacy I/O Map (ISA Compatible) ... 2-9 Page 0-2 ©2004 Inova Computers GmbH ICP-CM Doc.
- Page 5 Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration ... 3-6 3.1 CompactPCI Backplane ... 3-7 Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ... 3-8 3.2 Interfaces ... 3-9 3.21 J6 & J7 Ethernet ... 3-9 Figure 3.21 RJ45 Pinout ...
- Page 6 Table C1.11 Rear I/O Module Functionality ... C-2 C1.2 ITM-RIO Rear-Panels (4HP or 8HP) ... C-3 Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x ... C-3 C1.3 ITM-RIO-D-x Transition Module ... C-4 Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x ... C-4 Table C1.3 ITM-RIO-D-x Connector Description ...
- Page 7 Table E1.20 J4 Pinout - Contd..E-6 E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces ... E-7 Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK ... E-7 Table E1.30 J3 & J5 Interface Pinout ... E-8 E1.4 J1 Front-Panel VGA/TMDS Interface ... E-9 Figure E1.40 Standard Front-Panel VGA/TMDS Interface ...
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Page 8: Unpacking And Special Handling Instructions
Company name, contact person, shipping address and invoice address Product name and serial number Failure or fault description Clearly write the RMA number on the outside of the transportation carton. Page 0-6 ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 9: Revision History
ICP-CM Revision History Manual MAN-ICP-CM Publication Number PD00941013.XXX Issue PD00941013.001 Preliminary, First Release; All pages revised Doc. PD00941013.001 Revision History Brief Description of Changes ©2004 Inova Computers GmbH Preface Date of Issue Author 26/07/2004 Page 0-7... -
Page 10: Three Year Limited Warranty
Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are valid unless the consumer has the expressed written consent of Inova. - Page 11 1.33 Linux ... 1-9 1.34 VentureCom ... 1-9 1.35 Windows CE ... 1-10 1.36 VxWorks ... 1-10 1.37 OS-9 x86 ... 1-10 1.38 QNX ... 1-10 1.39 Jbed ... 1-10 Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview Page 1-1...
- Page 12 Table 1.49 ICP-CM Power Reqirements ... 1-19 1.50 Power Consumption ... 1-20 Figure 1.50 ICP-CM Power Consumption ... 1-20 1.51 Thermal Considerations ... 1-21 Table 1.51 ICP-CM Airflow Requirements ... 1-21 Page 1-2 ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001...
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Page 13: Icp-Cm Cpu
CompactPCI backplane (for high-speed DMA for example) or front-panel TCP/IP. The standard Inova ICP-CM configuration is ready to run - straight from the box. Utilizing the low- power consumption and the high-performance of the Celeron processor enables truly embedded, ruggedized industrial applications to be engineered utilizing the latest software available today. -
Page 14: Interfacing
Built in to the ICP-CM chipset is an analog VGA interface with BIOS configurable video RAM allocation extracted from the system memory. Inova have also developed a number of ATI Radeon R7000-based dedicated AGP plug-in modules complete with video controller and RAM etc. for graphic intensive applications or to provide greater display flexibility. -
Page 15: Specifications
PanelLink & TFT support GigaST R support Sound support Dual View support under Microsoft Windows 9x, Windows 2000 & XP CRT / TFT resolutions up to 2048x1536 Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview USB Boot Quick Boot Quiet Boot Page 1-5... - Page 16 Rear I/O D necessitates backplanes being PICMG 2.0 Rev. 3.0 compatible Page 1-6 IDE channel (Master & Slave) ® XP, Windows ® 2000, Windows , OS9 ©2004 Inova Computers GmbH ICP-CM ® NT, Windows ® 9x, Linux, VxWorks Doc. PD00941013.001 ®...
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Page 17: Functional Overview
Be aware that boards using the PXI bus will experience signal conflict if used with any (includes non Inova boards) CPU offering rear I/O - Therefore, in such cases always select a CPU board configuration without rear I/O. Also, for compatibility with older backplane revisions (2.11), rear I/O (C) should be selected if indeed rear I/O is required. -
Page 18: Figure 1.21 Icp-Cm Board Overview
Ethernet Fast Ethernet VGA, GigaST R, TMDS ( DVI ) or TFT etc. Page 1-8 Reset Button & Hot-Swap LED ©2004 Inova Computers GmbH ICP-CM 32-bit and rear I/O 256MB or 1GByte on- board DDR SDRAM Host Bridge AGP 4x Socket for Inova Graphic Module Doc. -
Page 19: Software
Windows NT operating system. Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview Page 1-9... -
Page 20: Windows Ce
(native processor speed) or hard real-time performance. In addition, advanced features are implemented such as modularity, hot updates, deadline-driven scheduling admission testing as well as a fast and pro- ductive cross-development. Page 1-10 ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 21: Hardware
ICP-CM 1.4 Hardware 1.41 Block Diagram Figure 1.41 Block Diagram This block diagram is applicable to all Inova’s CM-based CPUs. Components and/or functionality may change without notice. 32-bit with or without Rear I/O (RIO) configurations are possible. User’s of NI peripheral cards should check to see whether signal conflict is possible with the RIO option selected. -
Page 22: Connector Location
Table 1.43 Connector Description Connector J1, J2 CompactPCI Interface Connector AGP 4x for Optional Inova Graphic Piggyback 10BaseT/100BaseTx Fast Ethernet Interface ETH2 - [SiS 900 - chipset] 10BaseT/100BaseTx Fast Ethernet Interface ETH1 - [i82551] CompactFlash Socket (MicroDrive or Flash) Page 1-12 Description ©2004 Inova Computers GmbH... -
Page 23: Table 1.43 Continued
LPT1 25-Pin D-Sub integrated within the 12HP panel only Floppy Standard (notebook) header for slim-line floppy interface jumper selectable COM configurations Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview Description Description & Location Note The ICP-CM Hard Disk carrier -... -
Page 24: Figure 1.44 Front-Panel Options
IDE FLASH or an adapter that accesses other devices attached to this primary IDE channel, then an 8TE front-panel is selected. Both COM ports (jumper selectable to be RS232 or RS485) are installed on Inova’s ICP-HD-3 carrier board as are the interfaces for the LPT and slim-line FD. -
Page 25: Interface Positions
COM1, COM2, and LPT interfaces. A hard disk, if installed, will generally be fitted to the piggyback containing the combined PS-2 mouse / keyboard, USB2.0, COM1 and COM2 interfaces. Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview Note Page 1-15... -
Page 26: Construction - 4Hp Standard Cpu
2.0 interface for mouse, keyboard, FD, CD-ROM etc. The minimum airflow requirements must be compatible with the selected ‘processor speed, CPU damage could result otherwise ! Figure 1.46 Construction of CPU with Heat-Sink Assembly Page 1-16 ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 27: Construction - 8Hp Standard Cpu
FD and LPT - refer to Appendix A for further information. The minimum airflow requirements must be matched with the selected ‘processor speed, CPU damage could result otherwise ! Figure 1.47 Construction of CPU with Heat-Sink Assembly Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview Page 1-17... -
Page 28: Construction - 8Hp Standard Cpu With Agp
Figure 1.48 Construction of CPU with Heat-Sink Assembly Note: The dedicated carrier board - ICP-HD-3 is mounted to the baseboard in exactly the same fashion as illustrated in figure 1.47. It has been omitted here for clarity. Page 1-18 ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 29: Power Requirements
This CPU board is a high-performance, low-power device and, as such, requires voltage, current and power timing as defined in table 1.49 for correct operation. The Inova >70W PSUs fulfil these requirements and reference should be made to this products’ data sheet and user’s manual. -
Page 30: Power Consumption
CPU power consumption was measured with the ‘processor in idle state, in BIOS mode (i.e. the OS power management features were not being utilised) and software stressed to 100% ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 31: Thermal Considerations
If the ambient temperature is greater than 50 C, systems utilizing the benefit of this Celeron M CPU cannot operate with a standard hard-disk, floppy or CD-ROM Doc. PD00941013.001 ©2004 Inova Computers GmbH Product Overview Ambient Air Temperature 65 C 75 C 0.15... - Page 32 Product Overview ICP-CM This page has been left blank intentionally Page 1-22 ©2004 Inova Computers GmbH Doc. PD00941013.001...
- Page 33 Table 2.40 DMA Channel Description ... 2-7 2.5 Inova CM SMB Devices ... 2-8 Table 2.50 SMB Devices ... 2-8 2.6 Inova CM PCI Device List ... 2-9 Table 2.60 Legacy I/O Map (ISA Compatible) ... 2-9 2.7 Interrupt Configuration ... 2-10 Table 2.70 CompactPCI Bus Interrupts ...
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Page 34: Memory Map
Configuration ICP-CM 2.0 Memory Map Figure 2.00 System Architecture Page 2-2 ©2004 Inova Computers GmbH Doc. PD00941013.001... -
Page 35: Doc. Pd00941013.001 ©2004 Inova Computers Gmbh Page
- PXE Boot (48kByte) In addition, 3rd party devices can also have their ‘space’ here such as addi- tional networking cards, SCSI or FireWire etc. The total available space cannot exceed 96kByte. Doc. PD00941013.001 ©2004 Inova Computers GmbH Page 2-3... -
Page 36: I/O Mapped Peripherals
CompactPCI systems permit the full 16-bit addressing capability of the Intel 80x86 ‘processors, from 0h to 0FFFFh. All Inova CPU boards include peripheral devices requiring I/O address space on board and hence the BIOS automatically assigns the I/O address required by peripheral boards and PCI devices at boot time based on the requirements of each device. -
Page 37: Table 2.10 Legacy I/O Map (Isa Compatible) Contd
$CFC *) Denotes Plug ‘n’ Play devices that are configured during the BIOS POST. Values shown are ISA compatible I/O Doc. PD00941013.001 ©2004 Inova Computers GmbH Configuration Description *) Secondary Hard Disk Controller *) Parallel Port (LPT1) - Bi-Directional *) Floppy Disk Controller... -
Page 38: Memory Mapped Peripherals
Intel 80x86 memory map from 0h to 0FFFFFFh. Inova’s CompactPCI systems allow the full 32-bit addressing capability of the Intel Pentium 4 range of ‘processors so that memory mapped peripheral devices may be mapped locally to the ‘processor board at any location in the memory map not being used by other devices (e.g. -
Page 39: Table 2.30 Pc-At Interrupt Definitions
Entries may be reserved for ISA devices with the BIOS 2.4 DMA Channel Descriptions The ICP-CM CPU can access the devices shown in table 2.4 through the specified DMA channels. Table 2.40 DMA Channel Description DMA Channel Doc. PD00941013.001 ©2004 Inova Computers GmbH Configuration Function/Assignment Timer Keyboard Slave 8259... -
Page 40: Inova Cm Smb Devices
Configuration 2.5 Inova CM SMB Devices Table 2.50 shows the addressing of the SMB (System Management Bus) Devices Table 2.50 SMB Devices Address b[7:1] 0101 100 1010 000 1010 101 1010 110 1010 111 1101 001 Page 2-8 Device LM87 (Temperature Monitor) EEPROM SPD DDR Bank 0 EEPROM TOP EXTENSION (e.g. -
Page 41: Inova Cm Pci Device List
2.6 Inova CM PCI Device List Table 2.60 shows the available PCI devices both on-board and off-board (CompactPCI backplane). It should be noted that the interrupt routing assumes a standard Inova backplane configuration with a right-hand system slot. Table 2.60 Legacy I/O Map (ISA Compatible) -
Page 42: Interrupt Configuration
INTS Refer to BIOS Documentation ENUM# Routed by BIOS Note: Interrupts INTA through INTS and ENUM are System Master CPU inputs. INTA and ENUM are outputs if the CPU is in Peripheral Mode. ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 43: Timer / Counter
The BIOS featured in Inova’s CPUs programs the system timer tick for PC compatibility. The inter- rupt generated by the timer creates an interrupt request on IRQ0 of the programmable interrupt controller (PIC) which is serviced by the CPU as interrupt vector 08h. - Page 44 Configuration ICP-CM This page has been left blank intentionally. Page 2-12 ©2004 Inova Computers GmbH Doc. PD00941013.001...
- Page 45 Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration ... 3-6 3.1 CompactPCI Backplane ... 3-7 Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ... 3-8 3.2 Interfaces ... 3-9 3.21 J6 & J7 Ethernet ... 3-9 Figure 3.21 RJ45 Pinout ...
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Page 46: Compactpci J1/J2 Connectors
Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector 3.03 ICP-PM Connector J1 and J2 Inova’s ICP-CM CPU board has been designed as a 32-bit (or 64-bit) system slot device able to operate in either +5V or +3.3V (I/O) systems. The CompactPCI backplane connector is keyed accordingly (yellow for +3.3V and blue for +5V.) -
Page 47: Table 3.03 32-Bit Compactpci J1 Pin Assignment
J1-07 AD[30] J1-06 REQ0# J1-05 J1-04 J1-03 INTA# J1-02 J1-01 Reserved for use for Inova’s Uninterruptible Power Supply (UPS) Doc. PD00941013.001 ©2004 Inova Computers GmbH Row B Row C Row D REQ64# ENUM# +3.3V V( I / O ) AD[0]... -
Page 48: Table 3.04 32-Bit Compactpci J2 Pin Assignment (Std. With Rear I/O (D))
COM1_DCD FAL# LPT_SLCT FD_WGATE# +5V (1.5A) COM1_RI VGA_HSYNC V(I/O) ATA_IOW# USB4_D+ SMB_DAT ATA_IOR# USB4_D- PM_DAT V(I/O) ATA_IRQ15 ATA_DMARQ ©2004 Inova Computers GmbH ICP-CM Row D Row E (GA1) (GA0) ETH1_TXF- ATA_CS0# ATA_RST# ETH1_RXF+ ETH1_RXF- ATA_CS1# REQ6# GNT6# KB_CLK REQ5# GNT5#... -
Page 49: Table 3.04 32-Bit Compactpci J2 Pin Assignment (Std. - With Rear I/O (D)) - Contd
LPT_D6 J2-06 FD_DRATE0 COM2_RI LPT_D7 J2-05 FD_MSEN1 J2-04 V(I/O) J2-03 CLK4 J2-02 CLK2 J2-01 CLK1 Doc. PD00941013.001 ©2004 Inova Computers GmbH Row B Row C Row D PM_CLK SMB_CLK ATA_D10 KB_DAT ATA_DMACK VGA_B 64EN# V(I/O) ATA_D13 ATA_IORDY SPEAKER GNT3# REQ4#... -
Page 50: Table 3.05 Inova's Icp-Cm Rear I/O J2 (Cpu) Integration
Interfaces Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration Option Fast Ethernet USB 1.1 PS-2 Mouse & Keyboard 2nd IDE Channel Reset & Beeper LPT1 COM1 & COM2 Floppy Disk (A or B) The rear I/O options described here do not detract from the latest PICMG 2.0 R3.0 specification. -
Page 51: Compactpci Backplane
The System Slot is responsible for performing system initialization by managing each local board’s IDSEL signal. Physically, the System Slot may be located at either end of the backplane but Inova have placed theirs on the right to cater for physical expansion due to heat-sink, hard disk, extended function- ality etc. -
Page 52: Interfaces
Interfaces ICP-CM Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot Note: The logical slots are different to the physical slots. The slot marked with the ‘ ‘ is the System Slot and always as- signed logical ‘1’. The neighbouring slot is logical ‘2’! -
Page 53: J6 & J7 Ethernet
Data Rate Cable 10Mbit/2 2-pair Cat-5 100Mbit/s 2-pair Cat-5 Signal Description Ethernet / Fast Ethernet TX0+ TX0- RX0+ RX0- ©2004 Inova Computers GmbH Interfaces Note: Max. Length 100m 100m Page 3-9... -
Page 54: J17 Vga Interface
Supports VESA standard super high resolution graphics modes Supports low-resolution modes (320x240, 512x384, 400x300) Supports VESA Display Power Management Signalling Supports clock throttling for 2D engine and 3D engine Supports RAMDAC snoop for multimedia applications ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 55: Figure 3.23 High-Density D-Sub Vga Interface Pinout
Figure 3.23 High-Density D-Sub VGA Interface Pinout Table 3.23b Video Output Connector Signals Pin No. Analog RED Analog GREEN Analog BLUE 5, 6, 7, 8 CRT Ground +5V (DDC) CRT Ground DDC-SDA HSYNC VSYNC DDC-SCL Doc. PD00941013.001 ©2004 Inova Computers GmbH Signal Interfaces Page 3-11... -
Page 56: J19 Usb Interface
J19 is located as standard on the front panel. All standard USB 2.0 and 1.1 compatible devices can be connected to this interface. Figure 3.24 USB Interface Pinout Table 3.24 USB Connector Signals Pin No. Page 3-12 Signal USB P0- USB P0+ ©2004 Inova Computers GmbH ICP-CM Doc. PD00941013.001... -
Page 57: J10 Hot-Swap Interface
J9 is the standard CompactFlash interface and needs no further explanation. 3.28 Connecting the CM to the Inova ICP-HD3(-ND) Appendix A provides more information on the ICP-HD3(-ND) and its derivatives. For the sake of completeness however, the ICP-HD3(-ND) must only be attached / detached to / from the CM base board without power applied i.e. - Page 58 Interfaces ICP-CM This page has been left blank intentionally. Page 3-14 ©2004 Inova Computers GmbH Doc. PD00941013.001...
- Page 59 Table A2.3 USB Connector Signals ... A-7 A2.3 USB 2.0 Interfaces ... A-7 Figure A2.3 USB Interface Pinout ... A-7 A2.4 EIDE Interface ... A-8 A2.5 Slim-Line Floppy Disk Interface ... A-8 ICP-PM/CM Appendix-A ©2004 Inova Computers GmbH ICP-HD-3 Page A-1...
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Page 60: A1 Icp-Hd-3(-Nd) Cpu Extension
A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP) The Inova ICP-HD-3(-ND) interface is a mass-storage carrier board that is only available as a CPU plug-in device with either an 8HP or 12HP front-panel as illustrated in figure A1.1. -
Page 61: A1.2 Ide Carrier Board Icp-Hd-3(-Nd
Damage to the CPU, hard-disk carrier board or the LPT piggyback may result if the flex cable is positioned incorrectly. Inova will not accept responsibility for negligent actions! Position the blue side of the flex-cable to the blue-flanked connector shown Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module... -
Page 62: Table A1.2 Interface Description Of The Icp-Hd-3(-Nd) Module
Note: Any notebook-style IDE hard disk, Flash device or similar mass-storage unit can be connected here. However, Inova recommend only those devices from known manufacturers. Connecting devices to both J9 and J12 simultaneously is not recommended. A better configuration is to use Master and Slave devices connected to J12 only or use the Rear I/O feature. -
Page 63: A2 Icp-Hd-3(-Nd) Interfaces
Figure A2.1 COM1 & COM2 Interface Pinout Table A2.1 COM1 & COM2 Connector Signals Signal Pin No. RS232 ICP-PM/CM Appendix-A ©2004 Inova Computers GmbH Note: used from the CPU front-panel. rear I/O COM port option. RS485 RxD, TxD + The standard CPU configuration has both RxD, TxD - COM ports set for RS232 communication. -
Page 64: A2.2 Mouse & Keyboard Interfaces
Communicating from both mouse and keyboard sources is physi- cally possible but is not recommended! Signal Pin No. ©2004 Inova Computers GmbH Appendix A Signal Data - Mouse Clock - Mouse ICP-PM/CM Appendix-A... -
Page 65: Table A2.3 Usb Connector Signals
Standard to all ICP-HD-3 carrier board modules are the two USB (2.0) interfaces which are back- ward compatible to USB 1.1 devices. Figure A2.3 USB Interface Pinout Table A2.3 USB Connector Signals Pin No. USB P0- USB P0+ ICP-PM/CM Appendix-A ©2004 Inova Computers GmbH Signal ICP-HD-3 Page A-7... -
Page 66: A2.4 Eide Interface
To conform with the UDMA 66 (or higher) standards, only suitable, commercially available 80-strand ribbon cable should be used. Failure to do so may result in data transmission errors or even cause the CPU to crash! ©2004 Inova Computers GmbH Appendix A ICP-PM/CM Appendix-A... - Page 67 Figure B1.3 LPT1 Piggyback Board IPB-FPE12 ... B-3 Table B1.3 IPB-FPE12 Connector Description ... B-4 B1.4 LPT1 Interface ... B-4 Figure B1.4 LPT1 Interface Pinout ... B-4 Table B1.4 LPT1 Connector Signals ... B-4 ICP-P4/PM/CM Appendix-B ©2004 Inova Computers GmbH IPB-FPE12 Page B-1...
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Page 68: B1 Ipb-Fpe12 Cpu Extension
IPB-FPE12 B1 IPB-FPE12 CPU Extension The Inova IPB-FPE12 adds LPT functionality to any Inova Pentium M, Celeron M or Pentium 4(M) CPU. The piggyback is available as a stand-alone device with its own 4HP front-panel or integrated within a 12HP front-panel. The information documented here is valid regardless of the connection choice. -
Page 69: B1.3 Lpt1 Piggyback
Damage to the CPU, hard-disk carrier board or the piggyback may result if the flex cable is positioned incorrectly. Inova will not accept responsibility for Figure B1.3 LPT1 Piggyback Board IPB-FPE12 The physical connection of the IPB- FPE12 is electrically identical regard- ICP-P4/PM/CM Appendix-B ©2004 Inova Computers GmbH... -
Page 70: Table B1.3 Ipb-Fpe12 Connector Description
(ICP-HD-3) mounted J13 connector. Figure B1.4 LPT1 Interface Pinout Table B1.4 LPT1 Connector Signals Pin No. STROBE BUSY SLCT ERROR SLCTIN Page B-4 Description Signal Pin No. 18-25 ©2004 Inova Computers GmbH Appendix B Signal AUTOFD INIT ICP-P4/PM/CM Appendix-B... - Page 71 Table C1.11 Rear I/O Module Functionality ... C-2 C1.2 ITM-RIO Rear-Panels (4HP or 8HP) ... C-3 Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x ... C-3 C1.3 ITM-RIO-D-x Transition Module ... C-4 Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x ... C-4 Table C1.3 ITM-RIO-D-x Connector Description ...
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Page 72: C1 Itm-Rio Cpu Extension
- they are a complete, well thought-out concept. Nowhere is this more apparent than in the colourful rear I/O selection. With a choice of three full-length (80mm) plug-in modules conform- ing to the latest Inova rear I/O (D) specification and the rear I/O (C1) options, the major industrial requirements have been satisfied. -
Page 73: C1.2 Itm-Rio Rear-Panels (4Hp Or 8Hp
(rear panel). Figure C1.2 illustrates the three standard formats available (at time of press.) Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x The rear I/O options described here do not detract from the latest PICMG 2.0 R3.0 specification. -
Page 74: C1.3 Itm-Rio-D-X Transition Module
Care should be exercised when insert- ing the cables linking the COM, LPT, EIDE and floppy etc. Only those cables supplied by Inova Computers should be used. Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x Page C-4 ©2004 Inova Computers GmbH ICP-P4/PM/CM Appendix-C... -
Page 75: Table C1.3 Itm-Rio-D-X Connector Description
Example: if a FD is physically attached but the COM ports are required, then these ports will not work even if they are ICP-P4/PM/CM Appendix-C ©2004 Inova Computers GmbH Description COM2 is configured for RS232 communication COM2 is configured for RS485 communication... -
Page 76: C1.4 Com1 & Com2 Interfaces
COM ports set for RS232 communication. However, this device can be configured (J7 and J8) to observe a two-wire, non galvanically separated, RS485 protocol. The data direction is governed by control- ling the UART’s RTS signal. ©2004 Inova Computers GmbH Appendix C Note: ICP-P4/PM/CM Appendix-C... -
Page 77: C1.5 Lpt1 Interface
Figure C1.5 LPT1 Interface Pinout Table C1.5 LPT1 Connector Signals Pin No. Signal STROBE BUSY SLCT ERROR SLCTIN ICP-P4/PM/CM Appendix-C ©2004 Inova Computers GmbH Note: Pin No. AUTOFD INIT 18-25 ITM-RIO Signal Page C-7... -
Page 78: C1.6 Mouse & Keyboard Interfaces
I/O applications then they should not be used from the front- panel. Communicating from both mouse and keyboard sources is physi- cally possible but is not recommended! Signal Pin No. ©2004 Inova Computers GmbH Appendix C Signal ICP-P4/PM/CM Appendix-C... -
Page 79: C1.7 Vga Interface
Table C1.7 Video Output Connector Signals Pin No. Analog RED Analog GREEN Analog BLUE 5, 6, 7, 8 CRT Ground +5V (DDC) CRT Ground DDC-SDA HSYNC VSYNC DDC-SCL ICP-P4/PM/CM Appendix-C ©2004 Inova Computers GmbH Note: VGA are required then the twin- Signal ITM-RIO Page C-9... -
Page 80: C1.8 Fast Ethernet Interface
I/O option is used then the front-panel connection using the same controller must not be used. Doing so will disrupt the communication leading to spurious results. Signal Description Ethernet / Fast Ethernet TX0+ TX0- RX0+ RX0- ©2004 Inova Computers GmbH Appendix C ICP-P4/PM/CM Appendix-C... -
Page 81: C1.9 Usb Interface (Usb 4
Table C1.9 provide the pinout and signal description of this standard Ethernet interface respec- tively. Figure C1.9 USB Interface Pinout Table C1.9 USB Connector Signals Pin No. USB P2- USB P2+ ICP-P4/PM/CM Appendix-C ©2004 Inova Computers GmbH Signal ITM-RIO Page C-11... -
Page 82: C1.10 Eide Interface
To conform with the ATA 5 standard, only suitable, commercially available 80-strand ribbon cable should be used. Failure to do so may result in data transmission errors or even cause the CPU to crash! ©2004 Inova Computers GmbH Appendix C ICP-P4/PM/CM Appendix-C... -
Page 83: C1.12 Itm-Rio(C&D)-Fhlu Extension
HD. Likewise, a hard-disk can be swapped without having to disassemble the CPU! Two slim-line (notebook) floppy interfaces are implemented allowing the module to be compatible with existing Inova PIII CPUs (with RIO(C)) as well as the P4, PM and CM family. - Page 84 ITM-RIO Appendix C This page has been left blank intentionally. Page C-14 ©2004 Inova Computers GmbH ICP-P4/PM/CM Appendix-C...
- Page 85 Table D1.3 IPM-ATA-CF Jumper Description ... D-5 D1.4 IPM-ATA-PCMCIA ... D-6 Figure D1.4 IPM-ATA-PCMCIA Board Layout ... D-6 Table D1.4 IPM-ATA-PCMCIA Jumper Description ... D-6 D1.5 Device Compatibility ... D-7 Table D1.5 Compatibility List ... D-7 ICP-P4/PM/CM Appendix-D ©2004 Inova Computers GmbH IPM-ATA Page D-1...
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Page 86: D1 Ipm-Ata Cpu Extension
IPM-ATA D1 IPM-ATA CPU Extension Inova Plug-In Module (IPM-) offers the user the ability to exchange a hard-disk for example with- out having to remove the CPU from the CompactPCI enclosure and then dismantle it etc. Cur- rently, three units exist that provide industry with hard-disk, Compact FLASH, MicroDrive or ATA PCMCIA format mass storage capability. -
Page 87: D1.1 Rj2 Interfaces (Contd
3. Y-Cable for bringing the power from the CompactPCI backplane and to this and another device 4. Standard 80-strand, ATA-5 [UDMA-66 or higher] IDE ribbon cable (30cm) 5. Inova rear I/O module (ITM-RIO) with IDE connection Note: The IDE cabling used should conform to... -
Page 88: D1.2 Ipm-Ata-Hd
IPM-ATA-HD (the primary is on the CPU board itself). Multi Master or multi Slave configurations are not supported and will not work! Page D-4 Note: The hard disk is jumpered seperately for Master / Slave operation CompactFlash or MicroDrive in J3 Master Open Slave ©2004 Inova Computers GmbH Appendix D ICP-P4/PM/CM Appendix-D... -
Page 89: D1.3 Ipm-Ata-Cf
It should be noted that the secondary IDE channel only (from rear I/O) is available for use by the IPM-ATA-CF (the primary is on the CPU board itself). Multi Master or multi Slave configurations are not supported and will not work! ICP-P4/PM/CM Appendix-D ©2004 Inova Computers GmbH IPM-ATA CompactFlash Jumper J7... -
Page 90: D1.4 Ipm-Ata-Pcmcia
Slave Open Note: The PCMCIA device cannot and must not be removed during use. To ex- change or remove the device, first power-down the system! ©2004 Inova Computers GmbH Appendix D CompactFlash or MicroDrive in J3 Master Slave ICP-P4/PM/CM Appendix-D... -
Page 91: D1.5 Device Compatibility
Master / Slave combinations will fail to be recognised by the BIOS. To help highlight the problem, Inova have provided the test report shown in Table D1.5 which should be regarded as a guide when choosing to pick-and-mix de- vices. - Page 92 IPM-ATA Appendix D This page has been left blank intentionally. Page D-8 ©2004 Inova Computers GmbH ICP-P4/PM/CM Appendix-D...
- Page 93 Table E1.20 J4 Pinout - Contd..E-6 E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces ... E-7 Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK ... E-7 Table E1.30 J3 & J5 Interface Pinout ... E-8 E1.4 J1 Front-Panel VGA/TMDS Interface ... E-9 Figure E1.40 Standard Front-Panel VGA/TMDS Interface ...
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Page 94: E1 Agp-R7000 Cpu Extension
AGP-R7000 E1 AGP-R7000 CPU Extension The AGP-R7000 is an Inova AGP 4x ATI Radeon-based graphic extension for use with the ICP-P4, ICP-P4(M), ICP-PM and ICP-CM CPUs. By utilizing the power of the ATI Radeon 7000 equipped with 32MByte of SDRAM, a graphic performance improvement of some 50% when compared to the on board (chipset) solution. -
Page 95: E1.1 Specifications
This is the only supported mode whereby (independent) video can be produced via the front DVI-D and a rear connected analog (CRT) device. Both options support TFT - video content can be selected to be the TMDS or CRT ICP-P4/PM/CM Appendix-E ©2004 Inova Computers GmbH AGP-R7000 Colour Depth Refresh... -
Page 96: E1.2 J4 Interface
The J4 AGP interface on the graphic piggyback is electrically identical to AGP, but has a smaller form factor and uses a different connector. Table E1.20 shows the pinout of this connector. Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback Page E-4 ©2004 Inova Computers GmbH ICP-P4/PM/CM Appendix-E... -
Page 97: Table E1.20 J4 Pinout
VCC3.3 RBF# SBA0 SBA2 SB_STB VCC3.3 SBA4 SBA6 AD31 AD29 AD27 AD25 VDDQ1.5 AD_STB1 AD23 AD21 ICP-P4/PM/CM Appendix-E ©2004 Inova Computers GmbH AGP-R7000 Pin No. Signal USB6- AC_RESET# BITCLK VCC5 SDATA_IN INTA# RST# GNT# VCC3.3 PIPE# WBF# SBA1 SBA3 SB_STB# SBA5 VCC3.3... -
Page 98: Table E1.20 J4 Pinout - Contd
DEVSEL# PERR# SERR# C/BE1# VDDQ1.5 AD14 AD12 AD10 AD_STB0 VDDQ1.5 VREFCG VGA_R VGA_G VGA_B Page E-6 Signal Pin No. ©2004 Inova Computers GmbH Appendix E Signal AD22 AD20 AD18 AD16 FRAME# VDDQ1.5 TRDY# STOP# PME# AD15 AD13 VDDQ1.5 AD11 C/BE0# AD_STB0# VDDQ1.5... -
Page 99: E1.3 J3 & J5 Ibp-Gs-Multilink (Tft) Interfaces
To address an almost unlimited number of cascaded digitally connected (GigaST R) TFT displays with optional CAN control and PanelLink Slave connectivity, the Inova GigaST R transmitter pig- gyback, IPB-GS-MULTILINK needs to be installed adjacent to the AGP piggyback. This connection is made through connectors J3 and J5 on the upper side of the piggyback as shown in figure E1.30. -
Page 100: Table E1.30 J3 & J5 Interface Pinout
VSYNC VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 Information on the GigaSTAR IPB-GS-MULTILINK can be found in the respective documentation. Page E-8 J5 Connector Signal Pin No. ©2004 Inova Computers GmbH Appendix E Signal D0_B0 D1_B1 D2_B2 D3_B3 D4_B4 D5_B5 D6_B6 D7_B7... -
Page 101: E1.4 J1 Front-Panel Vga/Tmds Interface
N/C (GND) N/C (GND) DDC_DAT HSYNC VSYNC DDC_CLK ICP-P4/PM/CM Appendix-E ©2004 Inova Computers GmbH AGP-R7000 Note: A 3m length of 9-pin D-Sub to DVI-D cable is supplied with each CPU config- ured with this graphic option. Digital (TMDS) Signal TX2#... -
Page 102: Table E1.41 J2 Dip Switch Settings - Digital Tmds (Panellink) Or Dvi-D
1024 x 768 Note: If an external DDC is found then the switch settings SW1 to SW3 have no effect. This applies to the digital TMDS configuration only ©2004 Inova Computers GmbH Appendix E Comments See Note Below 60Hz 60Hz... -
Page 103: E1.5 Rear I/O Vga Interface
For this reason, the AGP piggyback is NOT available as an accessory to be added as an after thought! E1.5 Rear I/O VGA Interface Refer to the rear I/O documentation for video interfacing connectivity. ICP-P4/PM/CM Appendix-E ©2004 Inova Computers GmbH Page E-11...