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akira LCT-17HT Service Manual

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Summary of Contents for akira LCT-17HT

  • Page 1: Service Manual

    LCD Monitor Service Manual...
  • Page 2 -2 - MODEL: LCT-17HT Model No.: LCT-17HT Version: 1.0...

  • Page 3: Table Of Contents

    SPECIFICATION............................. 4 PANEL: HT17E12-200 ..........................5 8 BIT MTP MICROCONTROLLER ..................... 27 T0947 SCALER IC FPR XGA/SXGA LCD MONITORS ..............63 BLOCK DIAGRAM ..........................184 TV TUNER ............................185 EXPLODED VIEW & PART LIST...................... 186 Model No.: LCT-17HT Version: 1.0...

  • Page 4: Specification

    Resolution: 17.0 inch SXGA (1280 x 1024 @75Hz) Color display: 16,777,216 colors DPMS (Display Power Management Signaling) OSD (On Screen Display) Auto Configuration: Hot Key Speaker [L + R: 3W + 3W = 6W (max)] DDC 1/2 B: Plug & Play Model No.: LCT-17HT Version: 1.0...

  • Page 5: Panel: Ht17E12-200

    LVDS Interface with 2 pixel / clock High-speed response Low power consumption 6-bit (FRC) color depth, display 16,194,227 colors Incorporated edge type back-light (Four lamps) High luminance and contrast ratio, low reflection and wide viewing angle DE (Data Enable) mode Model No.: LCT-17HT Version: 1.0...
  • Page 6 RGB Vertical stripe Display colors 16,194,227 colors Display mode Normally White 358.5(H) × 296.5(V) × 17.0(D) type Dimensional outline Weight 1900 max. gram Back-light Top/Bottom edge side 4-CCFL type Note: 1. CCFL (Cold Cathode Fluorescent Lamp) Model No.: LCT-17HT Version: 1.0...
  • Page 7 Back-light lamp (80) Frequency Operating Temperature Storage Temperature Notes: 1. Temperature and relative humidity range are shown in the figure below. 2. Wet bulb temperature should be 39 C max and no condensation of water. Model No.: LCT-17HT Version: 1.0...
  • Page 8 3. The voltage above this value should be applied to the lamps for more than 1 second to start-up. Otherwise the lamps may not be turned on. 4. Calculated value for reference (V × I ) × 4 excluding inverter loss. Model No.: LCT-17HT Version: 1.0...
  • Page 9 Reproduction (Center) 0.324 0.354 0.384 of color Normal Note 5 0.257 0.287 0.317 Viewing Green 0.568 0.598 0.628 Angle 0.115 0.145 0.175 Blue 0.073 0.103 0.133 Response time msec Note 6 Cross talk Note 7 Model No.: LCT-17HT Version: 1.0...
  • Page 10 ) of a 25mm diameter area, with all display pixels set to a gray level, to the luminance ) of that same area when any adjacent area is driven dark. (See FIGURE 4 shown in Appendix). Model No.: LCT-17HT Version: 1.0...
  • Page 11 LVDS EVEN 2 + SIGNAL RXECLK- LVDS EVEN CLOCK – SIGNAL RXECLK+ LVDS EVEN CLOCK + SIGNAL RXE3- LVDS EVEN 3 – SIGNAL RXE3+ LVDS EVEN 3 + SIGNAL GROUND NO CONECTION NO CONECTION NO CONECTION POWER SUPPLY (+5.0V) Model No.: LCT-17HT Version: 1.0...
  • Page 12 System (Tx) TFT-LCD (Rx) Pin No. OUT0- RXO0- OUT0+ RXO0+ OUT1- RXO1- OUT1+ RXO1+ OUT2- RXO2- OUT2+ RXO2+ HSYNC VSYNC MCLK CLKOUT- RXO CLK- CLKOUT+ RXO CLK+ OUT3+ RXO3- OUT3- RXO3+ RSVD OUT0- RXE0- OUT0+ RXE0+ Model No.: LCT-17HT Version: 1.0...

  • Page 13: Out1-

    FI-X30S-HF Remark Pin No Pin No System (Tx) TFT-LCD (Rx) Pin No. OUT1- RXE1- OUT1+ RXE1+ OUT2 – RXE2- OUT2+ RXE2+ HSYNC VSYNC CLKOUT- RXE CLK- MCLK CLKOUT+ RXE CLK+ OUT3+ RXE3- OUT3 - RXE3+ RSVD Model No.: LCT-17HT Version: 1.0...
  • Page 14 CN21, 22, 23, 24: Module side connector : BHSR-02VS-1 (JST) User side connector : SM02B-BHSS-1-TB (JST) or equivalent Pin No INPUT Color Function Pin No INPUT Color Function Pink & White High voltage COLD Black & White Ground Model No.: LCT-17HT Version: 1.0...
  • Page 15 2*tRICP/7-0.4 2*tRICP/7 2*tRICP/7+0.4 nsec Input Data 3 tRIP5 3*tRICP/7-0.4 3*tRICP/7 3*tRICP/7+0.4 nsec Input Data 4 tRIP4 4*tRICP/7-0.4 4*tRICP/7 4*tRICP/7+0.4 nsec Input Data 5 tRIP3 5*tRICP/7-0.4 5*tRICP/7 5*tRICP/7+0.4 nsec Input Data 6 tRIP2 6*tRICP/7-0.4 6*tRICP/7 6*tRICP/7+0.4 nsec Model No.: LCT-17HT Version: 1.0...
  • Page 16 -16 - Model No.: LCT-17HT Version: 1.0...
  • Page 17 -17 - 7.0 SIGNAL TIMING WAVEFORMS OF INTERFACE SIGNAL 7.1 Vertical timing waveforms 7.2 Horizontal Timing Waveforms Model No.: LCT-17HT Version: 1.0...
  • Page 18 ▲ Gray Darker Scale ↑ ↑ ↑ ▲ ▼ ↓ ↓ ↓ Blue Brighter ▼ Blue Black Gray ▲ Scale Darker ▲ ↑ ↑ ↑ White ▼ ↓ ↓ ↓ & Brighter Black ▼ White Model No.: LCT-17HT Version: 1.0...

  • Page 19: Version:

    1. When the power supply VDD is 0V, Keep the level of input signals on the low or keep high impedance. 2. Do not keep the interface signal high impedance when power is on. 3. Back Light must be turn on after power for logic and interface signal are valid. Model No.: LCT-17HT Version: 1.0...
  • Page 20 There shall not be visible light from the back-lighting system around the edges of the screen as seen from a distance 50[cm] from the screen with an overhead light level of 350[lux]. The manufacture shall furnish limit samples of the panel showing the lightest leakage acceptable. Model No.: LCT-17HT Version: 1.0...
  • Page 21 8 Shock test (non-operating) Pulse width : 11ms, sine wave ± X, ± Y, ± Z Once for each direction : 150 pF, 330Ω, 15KV 9 Electrostatic discharge test Contact : 150 pF, 330Ω, 8KV Model No.: LCT-17HT Version: 1.0...
  • Page 22 Do not disassemble and/or re-assemble LCD module. Do not re-adjust variable resistor or switch etc. When returning the module for repair or etc, please pack the module not to be broken. We recommend on using the original shipping packages. Model No.: LCT-17HT Version: 1.0...
  • Page 23 -23 - 14.0 APPENDIX Figure 1. Measurement Set Up Figure 2. Average Luminance Measurement Locations & Uniformity Measurement Locations. Model No.: LCT-17HT Version: 1.0...
  • Page 24 Figure 3. Response Time Testing Figure 4. Cross Modulation Test Description Where: = Initial luminance of measured area (cd/m = Subsequent luminance of measured area (cd/m The location measured will be exactly the same in both patterns. Model No.: LCT-17HT Version: 1.0...
  • Page 25 -25 - Figure 5. TFT-LCD Module Outline Dimensions (Front View) Model No.: LCT-17HT Version: 1.0...
  • Page 26 -26 - Figure 6. TFT-LCD Module Outline Dimensions (Rear view) Model No.: LCT-17HT Version: 1.0...

  • Page 27: Bit Mtp Microcontroller

    Four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51) d. A 16-bit timer (identical to the Timer 2 of the 8052). A multi-source two-priority-level nested interrupt structure. One serial interface (UART) and g. An on-chip oscillator. Model No.: LCT-17HT Version: 1.0...

  • Page 28: Block Diagram

    -28 - 1.2 Block Diagram Model No.: LCT-17HT Version: 1.0...

  • Page 29: Pin Description

    -29 - 2.0 PIN Description 2.1 Pinout Diagram Model No.: LCT-17HT Version: 1.0...
  • Page 30 Program Memory or during accesses to external Data Memory that use A15-A8 27,26,25, 24 16-bit addresses (MOVX @ DPTR). During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register. Model No.: LCT-17HT Version: 1.0...
  • Page 31 If /EAVPP is held high, the device executes from internal program memory. /EAVPP is internal latched on reset. This pin also receives the 12V programming voltage (V during FLASH programming. 1,12,23,34 These pins should not be connected for any purpose Model No.: LCT-17HT Version: 1.0...

  • Page 32: Function Description

    DPTR, #data If ARAM_EN is set and DPTR contains 0030H, access the ARAM at address 030H rather than external memory. If ARAM_EN is set and DPTR contains 0130H, the external memory address 0130H will be accessed Model No.: LCT-17HT Version: 1.0...
  • Page 33 If desired, setting bit 0 of SFR location 8EH can disable ALE operation. With the bit set, ALE is active only during a MOVX instruction. Otherwise the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro-controller is in external execution mode. Model No.: LCT-17HT Version: 1.0...
  • Page 34 -34 - Memory Map Model No.: LCT-17HT Version: 1.0...

  • Page 35: Out2+

    The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. The internal RAM is not affected by reset. On power up the RAM content is indeterminate. Model No.: LCT-17HT Version: 1.0...
  • Page 36 Data Data Data Idle External Float Data Address Data Power Down Internal Data Data Data Data Power Down External Float Data Data Data Table 3-1. Status of the External pins During Idle and Power Down Model No.: LCT-17HT Version: 1.0...
  • Page 37 -37 - Reset Timing Model No.: LCT-17HT Version: 1.0...
  • Page 38 TCON.5 IE.1 IP.1 /INT1 External interrupt 1 TCON.3 IE.2 IP.2 Timer 1 interrupt TCON.7 IE.3 IP.3 SCON0.0 TI or RI Serial Port transmit or receive interrupt IE.5 IP.5 SCON0.1 Timer 2 interrupt T2CON.7 IE.6 IP.6 Model No.: LCT-17HT Version: 1.0...

  • Page 39: Special Function Registers

    *EB *BRG1 *BRG0 *INT2I *INT2E SCON SM1 SM2 SBUF *EX2 ET2 *PX2 PT2 T2CON EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 RCAP2L RCAP2H All register labeled with * can be only used in 68-pin package (not available now) Model No.: LCT-17HT Version: 1.0...
  • Page 40 SFR Register Initial Value Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD LEMI AUXR SCON SBUF T2CON RCAP2L RCAP2H Model No.: LCT-17HT Version: 1.0...
  • Page 41 ARAM_EN, Access Internal Auxiliary RAM Enable bit. When ARMA_EN=0, the access of external RAM will be performed by MOVX. When ARAM_EN=1, access internal auxiliary RAM rather than external RAM. GF6-GF5. General Purpose Flag bit. Reserved. Model No.: LCT-17HT Version: 1.0...

  • Page 42: Bit Description

    ET0, Enable External Timer 0. ET0=0 disables Timer 0 interrupt (TF0). ET0=1 enables interrupts generated by TF0 flag. EX0, Enable External Interrupt 0. EX0=0 disables external interrupt 0 (/INT0). EX0=1 enables interrupts generated by /INT0. Model No.: LCT-17HT Version: 1.0...
  • Page 43 0 and cleared when /INT0 is 1. In level-sensitive mode, software can not write to IE0. 0 IT0, Interrupt 0 Type Selector, /INT0 is detected on falling edge when IT0=1; /INT0 is detected as a low level when IT0=0. Model No.: LCT-17HT Version: 1.0...
  • Page 44 T0M (CKCON.3). When C/T=1, Timer 0 is clocked by T0 pin. M1-0, Timer 0 mode select bits Mode Mode 0: 13 bit counter Mode 1: 16 bit counter Mode 2: 8 bit counter with auto-reload Mode 3: Two 8 bit counter Model No.: LCT-17HT Version: 1.0...
  • Page 45 T2EX, if EXEN2=1. If either RCLK or TCLK is set to 1, CP/RL2 will not function and Timer 2 will operate in auto-reload mode following each overflow. SFR 98H: SCON Register Bit Description SM1, SM0, Serial Port 0 Mode Select bits Mode Model No.: LCT-17HT Version: 1.0...
  • Page 46 In addition to the timer/counter selection, Timer 0 and Timer 1 have four operating modes, Timer 2 has three operating modes. They are described below: Model No.: LCT-17HT Version: 1.0...
  • Page 47 Timer 0 : TL0 and TH0 indicate two 8-bit counters controlled by Timer0 and Timer1 control bit Timer 1 : off Timer2 Mode Control RCLK + TCLK CP/RL2 Operation Mode 16-bit auto-reload 16-bit capture Baud rate generator Non-active Model No.: LCT-17HT Version: 1.0...
  • Page 48 -48 - Model No.: LCT-17HT Version: 1.0...
  • Page 49 -49 - Model No.: LCT-17HT Version: 1.0...
  • Page 50 The Baud rate in Mode 1 and Mode 3 can be determined by overflow rate of Timer 1, Timer 2 or both (one for transmit and other for receive). When Timer 1 is used to generate Baud rate, it is determined by following equation: 2SMOD Baud Rate = X (Timer1Overflow Rate) Model No.: LCT-17HT Version: 1.0...
  • Page 51 Timer 1 TH1 Value for 33 TH1 Value for 25 TH1 Value for SMOD C/T Rate Mode MHz clock MHz clock 11.0592 MHz clock 57.6 Kb/s 19.2 Kb/s 9.6 Kb/s 4.8 Kb/s 2.4 Kb/s 1.2 Kb/s Model No.: LCT-17HT Version: 1.0...

  • Page 52: Electrical Specifications

    /PSEN Low to Valid Instruction In – 105 PLIV CLCL Input Instruction Hold After /PSEN PXIX /PSEN to Address Valid - 25 PXIZ CLCL Address to Valid Instruction In - 105 AVIV CLCL /RD Pulse Width – 100 RLRH CLCL Model No.: LCT-17HT Version: 1.0...
  • Page 53 Data Valid to /WR Transition – 60 QVWX CLCL Data Valid to /WR High – 150 QVWH CLCL Data Hold After /WR – 50 WHQX CLCL /RD or /WR high to ALE High + 40 WHLH CLCL Model No.: LCT-17HT Version: 1.0...
  • Page 54 -54 - Model No.: LCT-17HT Version: 1.0...
  • Page 55 -55 - Model No.: LCT-17HT Version: 1.0...
  • Page 56 Output Data Setup to Clock Rising Edge – 100 QVXH CLCL Output Data Hold After Clock Rising Edge – 100 XHQX CLCL Input Data Hold After Clock Rising Edge XHDX Clock Rising Edge to Input Data Valid – 133 XHDV CLCL Model No.: LCT-17HT Version: 1.0...
  • Page 57 The array occupies address space from 0000H to FFFFH. OTP Rows These non-volatile cells contain 2K bytes of memory that serve as a special storage space for protection data (i.e. key bytes and lock bits). Model No.: LCT-17HT Version: 1.0...
  • Page 58 The M6759 has 3 programmable lock bits that when programmed according to Table 7-2 will provide different levels of protection for the on-chip code and data. The lock bits are in the bit 4, bit 5 and bit 6 of OTPR address 0004. Refer to Figure 7-1 - OTPR arrangement. Model No.: LCT-17HT Version: 1.0...
  • Page 59 0. The status bits are in the bit1 and bit 0 of OTPR address 0004. Status bits Program Condition The bit needs to be programmed after erased. The bit needs to be programmed after protection function bytes (lock bits, key bytes) is programmed Model No.: LCT-17HT Version: 1.0...
  • Page 60 XTAL1 signal. All addresses have to be applied sequentially in order to verify the entire array. During verify, /OE must be low to enable reading the erased cells. An erased cell has a value of ‘ 1’ ; thus an erased byte contains FFh. Model No.: LCT-17HT Version: 1.0...
  • Page 61 -61 - 8.0 Packaging Information 44-pin PLCC Package Model No.: LCT-17HT Version: 1.0...
  • Page 62 -62 - 44-pin QFP Package Model No.: LCT-17HT Version: 1.0...

  • Page 63: T0947 Scaler Ic Fpr Xga/Sxga Lcd Monitors

    -63 - T0947 SCALER IC FPR XGA/SXGA LCD MONITORS SPECIFICATION Model No.: LCT-17HT Version: 1.0...

  • Page 64: New Features

    Hardware display mode detection for HDTV signal. Color space conversion for TV and HDTV (ITU BT 601 and SMPTE 240M). Auto increment of address counter for JPEG/bitmap port. Improved Gamma table programming with programmable initial address. Model No.: LCT-17HT Version: 1.0...
  • Page 65 Single pixel/clock (24 bit) or double pixels/clock (48 bit) digital RGB output. Maximum resolution of color display is 1280*1024 (SXGA). Free-run synchronization mode if sync signal disappeared. Compliant with proposed VESA FPDI-2 standard via direct connect to LVDS transceivers. Model No.: LCT-17HT Version: 1.0...
  • Page 66 High resolution TFT-LCD or smart-panel LCD monitors. Set-top box and DVD player to LCD/PDP display devices. NTSC/PAL projection systems for office presentation and home theater. LCOS or OLED displays for HMD applications. Image scaling for video format conversions. Model No.: LCT-17HT Version: 1.0...
  • Page 67 -67 - Model No.: LCT-17HT Version: 1.0...
  • Page 68 -68 - Model No.: LCT-17HT Version: 1.0...
  • Page 69 Display enable (active area of display) PVSYNC Display Vertical Sync PHSYNC Display Horizontal Sync 55,57-61,28,30 PRED[7:0] Display A port or Odd port of red data. /PY[7:0]/ODRED[7:0] The pin numbers are listed from MSB to LSB Model No.: LCT-17HT Version: 1.0...
  • Page 70 TABLE 4. Memory Control Port (Frame buffer) (32 pins) Pin # Name Description (drive) MCLK Memory clock output Memory write enable CASN Memory column address strobe RASN Memory row address strobe 72-75,86-97 MD[15:0] Memory data bus 105-110,112-1 MA[11:0] Memory address bus 15,125,126 Model No.: LCT-17HT Version: 1.0...
  • Page 71 Data inversion control for odd pixel bus (if more than half signals in the bus change state, this will be set.) CASN HMSE Data inversion control for even pixel bus RLSC R/L indication for source driver IC Model No.: LCT-17HT Version: 1.0...
  • Page 72 P2RED2 (EVRED2) P2BLU2 (EVBLU2) P2RED3 (EVRED3) P2BLU3 (EVBLU3) VSSAM PBLU4(PV4) (ODBLU4) VDDAP PBLU3(PV3) (ODBLU3) VSSAP PBLU2(PV2) (ODBLU2) PGRN1(PU1) (ODGRN1) PGRN0(PU0) (ODGRN0) INTN POWERDN PGRN5(PU5) (ODGRN5) PGRN4(PU4) (ODGRN4) VGAHS PGRN3(PU3) (ODGRN3) VDD25 PGRN2(PU2) (ODGRN2) OVCLK PRED7(PY7) (ODRED7) Model No.: LCT-17HT Version: 1.0...
  • Page 73 P2BLU5 (EVBLU5) P2GRN5 (EVGRN5) P2BLU6 (EVBLU6) P2GEN4 P2BLU7 (EVBLU7) Pin no. Pin name Pin no. Pin name P2GRN0 (EVGRN0) P2GRN1 (EVGRN1) RGHS P2GRN2 (EVGRN2) COAST P2GRN3 (EVGRN3) CSYNC VDD33 MA1(STH8) MD11 MA0(STH1) MD10 VDD33 ICLK(YUVLLC) IVSYNC Model No.: LCT-17HT Version: 1.0...
  • Page 74 MA10 (GPO1) MA9 (GPO0) IGRN7(YUVLLC2) MA8 (STV3) IRED0(YIN0/YUV0) MA7 (STV1) IRED1(YIN1/YUV1) MA6 (CLKV) IRED2(YIN2/YUV2) VDD25 IRED3(YIN3/YUV3) MA5 (SHC) IRED4(YIN4/YUV4) MA4 (RLSC) IRED5(YIN5/YUV5) MA3 (LP) IRED6(YIN6/YUV6) MA2 (POL) IRED7(YIN7/YUV7) OVI(MA13) P2RED4 IICADDR/MA12 P2RED5 CLAMP P2RED6 VDD33 P2RED7 Model No.: LCT-17HT Version: 1.0...
  • Page 75 -75 - Model No.: LCT-17HT Version: 1.0...
  • Page 76 Display A port green data. The pin numbers are listed from MSB to LSB 29-31,33-35,28-27 PBLU[7:0]/PV[7:0] Display A port blue data Reference frequency output for internal oscillator Reference frequency input for internal oscillator (should be connected to a 14.31818MHz crystal) Model No.: LCT-17HT Version: 1.0...
  • Page 77 Digital power supply (for core cells) 18,59,65,84,99 VDD33 Digital power supply (for I/O cells) 4,21,23,32,44,58,80,96,1 0 Ground VSSAM Ground pin for MCLK PLL VDDAP Power pin for PCLK and MCLK PLL VSSAP Ground pin for PCLK PLL Model No.: LCT-17HT Version: 1.0...
  • Page 78 PGRN5(PU5) PGRN4(PU4) VGAHS PGRN3(PU3) VDD25 PGRN2(PU2) OVCLK PRED7(PY7) PRED6(PY6) PRED5(PY5) OVFB PRED4(PY4) PRED3(PY3) PRED2(PY2) VDD33 RSTN PCLK PGRN1 PVSYNC PGRN0 PHSYNC VDD25 PRED1 VDD25 PRED0(PWMR0) PBLU0(PWMB0) VDD33 PBLU1 MD15 PBLU7(PV7) MD14 PBLU6(PV6) MD13 PBLU5(PV5) MD12 Model No.: LCT-17HT Version: 1.0...
  • Page 79 IVSYNC IHSYNC IBLU0(UVIN0) IBLU1(UVIN1) IBLU2(UVIN2) IBLU3(UVIN3) IBLU4(UVIN4) IBLU5(UVIN5) IBLU6(UVIN6) VDD25 IBLU7(UVIN7) MCLK VDD25 IGRN0(YUVCREF) IGRN1(YUVVREF) CASN IGRN2(YUVVREF) RASN IGRN3(YUVODD) VDD33 IGRN4 MA11 IGRN5(YUVHS) MA10 IGRN6(YUVVS) IGRN7(YUVLLC2) IRED0(YIN0/YUV0) IRED1(YIN1/YUV1) IRED2(YIN2/YUV2) VDD25 IRED3(YIN3/YUV3) IRED4(YIN4/YUV4) IRED5(YIN5/YUV5) IRED6(YIN6/YUV6) IRED7(YIN7/YUV7) Model No.: LCT-17HT Version: 1.0...
  • Page 80 All timing is measured at 1.5V logic switching threshold and VDD3 = 3.3V; VDD2 = 2.5V; VDDAP = 2.5V; T = 25 C; unless otherwise specified. min. min. SYMBOL PARAMETER UNIT setup time hold time Input signals (RGB / YUV data and overlay ports) tsu1/thd1 IAVSYNC/IAHSYNC setup/hold time Model No.: LCT-17HT Version: 1.0...
  • Page 81 IBR/IBG/IBB input data setup/hold time tsu4/thd4 control signal (VGAHS/DE/CSYNC) setup/hold time tsu5/thd5 Overlay inputs (OVR/G/B/I/FB) setup/hold time max. Output signals delay time tod1 pixel data output delay (PAR/G/B, PBR/G/B) tod2 control signal (PDE, PHS/PVS) output delay Model No.: LCT-17HT Version: 1.0...
  • Page 82 YUVF (bit 4 of INCTR1 or 02 hex) bit. TABLE 15. Signal 16-bit 4:2:2 8-bit 4:2:2 (CCIR-656) YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 UVIN7 UVIN6 UVIN5 UVIN4 UVIN3 UVIN2 UVIN1 UVIN0 FIGURE 4. Input YUV format & timing Model No.: LCT-17HT Version: 1.0...
  • Page 83 IHS falling edge. If IH_ASTART= n and IH_AWIDTH = w, then the first and the last active data are D and D respectively. If IV_ASTART=n and IV_ACTIVE = w, then the fist active line is Ln and last active line is L n+w-1. FIGURE 5. INPUT WINDOW PARAMETER: Model No.: LCT-17HT Version: 1.0...
  • Page 84 -84 - FIGURE 6. Output Window parameters. Model No.: LCT-17HT Version: 1.0...
  • Page 85 These settings are tabulated as TABLE 17. Contrast correction for MSB=0 contrast[7:0] 7f(hex) multiply value 255/128 254/128 130/128 129/128 128/128 Contrast correction for MSB=1 contrast[7:0] ff(hex) multiply value 127/128 126/128 2/128 1/128 0/128 Model No.: LCT-17HT Version: 1.0...
  • Page 86 -126 -127 -128 The block diagram is depicted as follows: FIGURE 7. Function of contrast followed by brightness control for each RGB. FIGURE 8. Data path for RGB/YUV in and RGB/YUV out Model No.: LCT-17HT Version: 1.0...
  • Page 87 F8 is the MSB of feedback 9-bit divider, OD0 (MS and OD1 (1 down to 0) & (LSB) are the control pins for output divider, and R4 to R0 are RI(4 down to 0) the pins for input 5-bit divider. Model No.: LCT-17HT Version: 1.0...
  • Page 88 OD=10(bin). Therefore, we need to program the register PLLPSET0 (BA) with a value e1(hex) and PLLPSET0 (BB) with 57. Pclk can be further divided by the factor of 4 using Pdiv4. MCLK can be turn off by program the register FBC_BYPASS (FBCTR2[6]) to “1” Model No.: LCT-17HT Version: 1.0...
  • Page 89 Note that the registers 0xEA to 0xED are for SD/SGRAM mode setting, and registers 0xE6-0xE9 are for SD/SGRAM interface setting. Besides, a frame buffer test pattern can be defined and tested by the settings in FBC_PAT register (E5H) and the bit 7 (FILL_PAT) of FBCTR0 (E0H). Model No.: LCT-17HT Version: 1.0...
  • Page 90 4.7.3 Freeze and Vertical flip of the frame When you set Freeze_FB(FBCTR2[7]) to “1”, you will enter the freeze mode and the frame is stilled. When you set V_flip(FBCTR1[7]) to “1”, you can let the frame top/bottom reversal. Model No.: LCT-17HT Version: 1.0...
  • Page 91 Red RAM table (the first 10-bit data is written into RAM at address 0 and the 256th data is written into RAM at address 255). In a similar way, we can program the tables for Green and Blue channels. Model No.: LCT-17HT Version: 1.0...
  • Page 92 11: 2 bit dithering (for the panel with 6 bit color depth DITHER_FDBK_ON x05[1] The error due to resolution change is fed back for dithering 0: feedback path is disconnected. 1: feedback path is connected for dithering. Model No.: LCT-17HT Version: 1.0...
  • Page 93 10: RNG 12 11: RNG 16 I_DITHER_FDBK_ON x1F[3] The error due to resolution change is fed back for dithering operation to FBC input 0: feedback path is disconnected. 1: feedback path is connected for dithering. Model No.: LCT-17HT Version: 1.0...
  • Page 94 -94 - FIGURE 11. Color look-up table for internal, external, and background color 4.11 Dithering and output formatter The chip supports 8-bit or 6-bit panel using dithering methods as follows: Model No.: LCT-17HT Version: 1.0...
  • Page 95 (binary). The definition of the basic 2-wire serial bus interface protocol is illustrated as follows. For detailed timing and operation protocol, please refer to the standard 2-wire serial bus specification. FIGURE12. The definition of the basic 2-wire serial bus timing protocol Model No.: LCT-17HT Version: 1.0...
  • Page 96 Vsync pulse which can be used as the COAST signal into ADC chips. Generally, these Csync signals come from Hsync plus Vsync or Hsync exclusively OR Vsync or added serration pulse. The Composite sync to coast signal generation is depicted as in the following figure. Model No.: LCT-17HT Version: 1.0...
  • Page 97 Hstart and Hend. Hstart is the first valid data and Hend is last valid data on the AMLNUM line. The RGB values of Hstart and Hend are also stored so that the value can be accessed by the host micro-controller. Model No.: LCT-17HT Version: 1.0...
  • Page 98 (counted from the H active region) and then read the same address AFZREAD sequentially. All data are updated per frame and check continuously. FIGURE 14. Inter and intra-frame SOD (sum and sum of difference) calculations Model No.: LCT-17HT Version: 1.0...
  • Page 99 15" TFT-LCD panel. The output pins of this timing controller are shared with the SDRAM control pins. To this, the functions of timing control and SDRAM control are exclusive to each other. The timing control and SDRAM control circuits can both be deactivated. Model No.: LCT-17HT Version: 1.0...
  • Page 100 -100 - Model No.: LCT-17HT Version: 1.0...
  • Page 101 The programmable LPF can be used for noise-reduction. Register for main control in peaking 35h bit 1 peaking enter 0 :enter 1 :bypass 35h bit 0 choose PEAK or LPF 0 :LPF 1 :PEAK Model No.: LCT-17HT Version: 1.0...
  • Page 102 Peaking Control LSB (34h) bit [3:0] gain_LP 0000 0001 1/16 0010 2/16 0011 3/16 0100 4/16 0101 5/16 0110 6/16 0111 7/16 1000 8/16 1001 9/16 1010 10/16 1011 11/16 1100 12/16 1101 13/16 1110 14/16 1111 Model No.: LCT-17HT Version: 1.0...
  • Page 103 As shown in above table, there are 7 fields about the row based display attributes. Note the ROW attribute is always defined in the first column of each ROW (i.e. Display RAM location, 32XN, N = .15). The following sections will explain the details of each field. Model No.: LCT-17HT Version: 1.0...
  • Page 104 For the example shown upon, EOD bits of row 4, 5, 6 and 7 must be 0 and EOD bit for row 8 should be 1 to end the display. Model No.: LCT-17HT Version: 1.0...
  • Page 105 REPRESENTATIVE EXAMPLE SHADOW MODE CODE(B4 B3 B2 B1) PATTERN South shadow (0000) West-South shadow (0000) West shadow (0010) West-North shadow (0011) North shadow (0100) Model No.: LCT-17HT Version: 1.0...
  • Page 106 Given by the flexibility of this mode, associated with SP code feature, it is already sufficient to create the window-like menu. In this mode, the background color defined by SP code takes effect from the left border of this SP code. Model No.: LCT-17HT Version: 1.0...
  • Page 107 1: stands for the double size of character height, 2 X (18 + inserted) scanning lines. CH CW FIGURE18. Four kinds of row dimension programmed by CH and CW ROW Attribute FIGURE18. Four kinds of row dimension programmed by CH and CW Model No.: LCT-17HT Version: 1.0...
  • Page 108 In total, there are 15 possible line insertion encoded by this field. The following table illustrates the repeated lines for each corresponding code. This feature associated with CH bit and Row Spacing field (see next section) will provide variable character height from 5 scanning lines to 66 scanning lines. Model No.: LCT-17HT Version: 1.0...
  • Page 109 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16/5, 6, 7, 8, 9, 10, 11, 12, 15/30 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 Model No.: LCT-17HT Version: 1.0...
  • Page 110 The remaining codes represent the lines inserted between two display rows. This feature can be used to adjust the vertical height, aspect ratio and accordingly avoid expansion distortion. The window, fade in/out feature remain valid for row spacing. Model No.: LCT-17HT Version: 1.0...
  • Page 111 15 lines inserted between two rows ROW N ROW N ROW N ROW N+1 ROW N+1 ROW N+1 ROW N+2 Without Row with 5 lines Without Spacing FIGURE 20. Spacing between two displayed rows and underline effect Model No.: LCT-17HT Version: 1.0...
  • Page 112 0, Blink, is still effective in the programmed blinking rate. The background color underneath the multi-color dot is stationary and not blinked. The following diagram illustrates Graphic Character Font in two modes, decided by the setting of Bit 1. Model No.: LCT-17HT Version: 1.0...
  • Page 113 However, if SPT bit is set, the background color will disappear and become transparent. If the color change is expected in the midway instead of the starting of SPcode domain, then, one bit, Split, in OSDCTRL register must be set illustrates the situation mentioned for this case. Model No.: LCT-17HT Version: 1.0...
  • Page 114 Each dot in the graphic character font is encoded by three bits, which are corresponding to R, G, B colors. The color definition by 3 bits (R, G, B) is shown in the following table: Model No.: LCT-17HT Version: 1.0...
  • Page 115 Bit 1, I, of character attribute. Then the dot of graphic character font with 000b can be filled by the background color, which is defined by last SPACE code. There are 16 colors for the background color, including cyan color. Model No.: LCT-17HT Version: 1.0...
  • Page 116 BXH BRIGHTNESS, CONTRAST, GAMMA, CLUT, and PLL PARAMETERS 16:9 ALPHA BLENDING CXH DEno_perV IN/OUT HS/VS PARAMETERS OSD PARAMETERS freq DXH HARDWARE MODE DETECTOR PARAMETERS KEYSTONE PARAMETERS EXH Frame buffer control and related FXH JPEG WRITE, 16:9 ZOOMING, DEINTERLACE, and PWMR0/B0 Model No.: LCT-17HT Version: 1.0...
  • Page 117 Register4 (R/W) LAY[2] LAY[1] LAY[0] (INCTR4) Output Control FID32_CL FID32_ PCLKEQI NTSC_HD RST_GT_ADR H_FLIP PWMR0ACT PWMB0AC Register3 (R/W) AMP[1] CLAMP[1] (OUTCTR3) Misc. Control GAMMAUSE DEINT_OFIF_ VHSYN_S FREEZE EOSD_EN EOSDFR BYPASS DE_DIM_E Register (R/W) 32PD 0(MISCTR0) Model No.: LCT-17HT Version: 1.0...
  • Page 118 OSD control VITOREND VINT TEST0 register0 (R/W) (OSDCTR0) OSD control SPLIT HTONE MONITOR HP IODS_EN register1 (R/W) (OSDCTR1) ID_VER (Chip ID and Version, 00H) Default ID_VER 01000001 (bin, for t0944/t0946/t0947/t0949) ID_VER 01010001 (bin, for ZiproSO/t0959) Model No.: LCT-17HT Version: 1.0...
  • Page 119 This signal is valid only if DE_ON=1. 0xx: No delay (x means do not care) 100: -2 clock delay. 101: -1 clock delay. 110: +1 clock delay. 111: +2 clock delay. Model No.: LCT-17HT Version: 1.0...
  • Page 120 11: 2 bit dithering (for the panel with 6 bit color depth per R/G/B) PHCLK_INV 0: Normal PHCLK clock output to panel 1: Inverted PHCLK clock output to panel (The relationship of PHCLK and PCLK is also defined by PHCLK_OP(1:0) and PRGB48) Model No.: LCT-17HT Version: 1.0...
  • Page 121 0: Normal Panel output 1: Output Panel is forced to Background color, the color is selected by BKCOL[3:0] BKCOL[3:0] Panel output Background color select signals. These signals share the look-up table with OSD to generate colors. Model No.: LCT-17HT Version: 1.0...
  • Page 122 ICLK and PCLK. 00: 1024 crystal clocks. 01: 2048 crystal clocks. 10: 3072 crystal clocks. 11: 4096 crystal clocks. IVS_SELEC Input VS source selection. 0: from external IVS, 1: from internal mode detection circuit. Model No.: LCT-17HT Version: 1.0...
  • Page 123 000: 0 unit delay, 001: 1 unit delay, 010: 2 units delay, 011: 3 units delay 100: 4 units delay, 101: 5 units delay, 110: 6 units delay, 111: 7 units delay. FID_INV_ Selection of the inversion of Frame Id for scaler. SCALER 0: normal, 1: inversed. Model No.: LCT-17HT Version: 1.0...
  • Page 124 Reg GCSTART ( B9h )while there is a low to high transition H_FLIP H-flip activation 0: H-flip is off. 1: H-flip is on (the preset value of the down counter, H_FLIP_COUNT, should be set before this operation.) Model No.: LCT-17HT Version: 1.0...
  • Page 125 Frame Buffer.) Note: In order to activate free-run mode, micro-controller should choose BYPASS = 0. To this, the input data can be ignored, if necessary, by setting BKFRC= 1 so background colors are sent to panel. Model No.: LCT-17HT Version: 1.0...

  • Page 126: Out1+

    STATUS1 (status Register 0, 0DH) (read only) Default RD/WR reserved reserved 5-4 reserved AFREEZE_RDY For auto adjustment, this status bit will be set to 1 as the freeze function is completed. This is a RD only status bit. Model No.: LCT-17HT Version: 1.0...
  • Page 127 OUTCTR2 and MISCTR1. VIDEO_ Free run of video mode. FREERUN 0: The VS of panel is synchronized by input video VS. 1: The VS of panel is generated by free running. Model No.: LCT-17HT Version: 1.0...
  • Page 128 01: (default) VS frame count is 1. 10: VS frame count is 2. 11: VS frame count is 3. HS_EQ_HREF The generation of internal HS signal for video display. 0: Internal HS is different from HREF input. Model No.: LCT-17HT Version: 1.0...
  • Page 129 V and H respectively. In a word, the unit of VREF delay is 2*H-line and the unit of HREF delay is 4 pixels (or 6.75MHz). For VREF delay, VREF_DELAY=00 (default) means no delay. For HREF delay, HREF_DELAY=00 (default) means no delay. Model No.: LCT-17HT Version: 1.0...
  • Page 130 Please refer to the figure of Output 31,30 01,28 Start(PH_ASTART[10:0]) Window Panel Horizontal Active 33,32 04,00 Width(PH_AWIDTH[10:0]) bit[7:4]: select high-pass mode Peaking Control LSB(PEAKING[7:0]) (0~15) for PEAKING bit[3:0]: select band-pass mode (0~15) for both PEAKING and LPF Model No.: LCT-17HT Version: 1.0...
  • Page 131 : RESET_SCALER reset the rest of blocks (except I2C, PWM, HMD) x45[2] : PWM_OUT_EN 0 : PWM output is enable 1 : PWM output is disable x45[3] : OUTPUT_SWAP 1 : Swap the A/B port output Model No.: LCT-17HT Version: 1.0...
  • Page 132 (PB_LEAD_LAG_OD, of panel background active region PBV_AOFFSET_ODD[9:0]) for odd field. The value is counted from the PV_ASTART. The MSB, PB_LEAD_LAG_OD, defines lead or lag to PV_ASTART.PB_LEAD_LAG_ OD = 1 is lag, otherwise (default) lead. Model No.: LCT-17HT Version: 1.0...
  • Page 133 OSD default setting for space code color Bit0:intensity color of space code (OSD_SPDEF[3:0]) Bit1:blue color of space code Bit2:green color of space code Bit3:red color of space code Bit5~bit4:Veritical position step Bit7~bit6:Horziontal position step Model No.: LCT-17HT Version: 1.0...
  • Page 134 5F,5E 00,FF Define the freqnency of PWM. PWM frequency = 14.318MHz/ 4 /PWM_PREIOD Note: MSB should be programmed first. PWM_PERIOD should be greater than PWM _HIGH_PERIOD. So this PWM can be programed from 55Hz to1.7MHz. Model No.: LCT-17HT Version: 1.0...
  • Page 135 SALGO = 1 selects bell shape interpolation, SALGO = 2 selects SINC (default), SALGO = 3 chooses pixel replicate. The algorithms in the order of smoothness to sharpness are SINC, bell, linear, and replicate. Model No.: LCT-17HT Version: 1.0...
  • Page 136 Clamp pulse starting setting register The starting point of clamp pulse (CLAMP_STA) setting. Counted from the falling edge of sync pulse by IACLK. Clamp pulse width setting register The width of clamp pulse by IACLK (CLAMP_WIDTH) (1.2us is suggested) Model No.: LCT-17HT Version: 1.0...
  • Page 137 SOD operation. There are five possibilities. If SOD_MASK_BIT=000, all bits are calculated. If SOD_MASK_BIT=001, the LSB 1 bit is not cared. While if SOD_MASK_BIT=1xx, the LSB4 bits are not cared. The LSB 3 bit of Model No.: LCT-17HT Version: 1.0...
  • Page 138 (horizontally) the starting and ending pixels along the Mth line. If 00 are programmed, the entire screen is covered for H_start and H_end points searching. The 1st line exceeds ARGB_MIN 8B,8A 00,00 (AVSTART[10:0]) Model No.: LCT-17HT Version: 1.0...
  • Page 139 The threshold of number of pixels that will be treated as an active line. The LSB 4-bit will be used. The default number is at least 2 pixels will be treated as an active line. Model No.: LCT-17HT Version: 1.0...
  • Page 140 69.8413*1024*XTAL_PULSE_S EL / XPULSE_BY_PCLK where XTAL_PULSE_SEL (=1, 2, 3, or 4) is defined in Register INCTR2 (06 hex) IH_TOTAL MEASURE A5,A4 00,00 The length of HS period, (IHTOTAL_BY_ICLK[10:0]) IH_TOTAL, counted by the ICLK. Model No.: LCT-17HT Version: 1.0...
  • Page 141 0, 1, till the final one entity255. Then channel G followed by channel B. GAMMA table G write Address (GGWADDR[7:0]) GAMMA table B write Address (GBWADDR[7:0]) (The table write address will be auto increased upon each writing) Model No.: LCT-17HT Version: 1.0...

  • Page 142: Out0+

    OSD/background color is activated, the final video of panel out will be equal to Video*CLUT_ALPHA[2:0]/8+C LUT* (1-CLUT_ALPHA[2:0]/8). For the case that CLUT_ALPHA[2:0]=0, the final video of panel is directly from the output of CLUT. And for Model No.: LCT-17HT Version: 1.0...
  • Page 143 IH_TOTAL * ICLK_Period = Vsf * PH_TOTAL * PCLK_Period. Panel HSync delay C7,C6 00,00 The LSB 11-bit defines the delay (PH_DELAY[10:0]) of display output HS from IVS. The value is counted by PCLK. Model No.: LCT-17HT Version: 1.0...
  • Page 144 1 : enable DRAM_MODE Select the configuration of SDRAM 0 : 512Kx2x16 1: 1Mx4x16 BASE_ADDR[16] When use SDRAM configuration of 1Mx4x16, treat this bit as the bit 16 of BASE_ADDR which is define by BC_BASE_ADDR (xE6,xE7) Model No.: LCT-17HT Version: 1.0...
  • Page 145 Wait cycles of ACK (acknowledge for receiving data) for SD/SGRAM interface. Adjust the timing of FBC to latch SD/SGRAM data. 00: 0 wait cycle, 01: 1 wait cycle, 10: 2 wait cycles 11: 3 wait cycles Model No.: LCT-17HT Version: 1.0...
  • Page 146 A frame buffer test pattern can be defined and tested by the settings in FBC_PAT register (0FH) and the bit 7 (FILL_PAT) of FBCTR0 (07H). (FBC E5H) Default FBC_JPEG_HS_NUM When JPEG_MODE = “10” (Horizontal Auto Increment Mode), set this register to the number of vertical JPEG blocks in one frame. Model No.: LCT-17HT Version: 1.0...
  • Page 147 SDRAM data timing. After setting the values for this mode register, one should set the LMR_REQ to 1 and then reset it to 0. The LMR_REQ is at bit 6 of FBCTR0 (E0hex) Model No.: LCT-17HT Version: 1.0...
  • Page 148 MSB:ODD LSB:EVEN Register E0-EF are described in Frame Buffer Control Parameters Starting address of x direction for JPEG The LSB 11-bit defines the starting F1,F0 00,00 write (JPEG_WR_X[10:0]) address of x direction for JPEG write. Model No.: LCT-17HT Version: 1.0...
  • Page 149 PBLU0.The selection is controlled by the PBLU0ACT bit 0 in OUTCTR3. The default value 00 means a low output while the value ff (hex) can be integrated by a capacitor for an almost high signal. Model No.: LCT-17HT Version: 1.0...
  • Page 150 Following is the control registers table of the ZiproSX internal OSD. The description of each register is as follows. Table1 Control Register Table REGISTER ADDR Bit Map Reset FUNCTION (HEX) Value OSDAT 59 H OSDAT OSDADL OSDADH OSDFAddr OSDFontL OSDFontM SysControl Model No.: LCT-17HT Version: 1.0...
  • Page 151 -151 - REGISTER ADDR Bit Map Reset FUNCTION (HEX) Value OSDSP-def OSDStartRow OSDHpos OSDVpos OSDCtrl2 OSDCtrl Model No.: LCT-17HT Version: 1.0...
  • Page 152 -152 - Graphic_Start Graphic_End OSDWindow_ Addr OSDWindow_ Data Table 2 OSD Window Register Table REGISTER ADDR Bit Map Reset FUNCTION (HEX) Value Win1V Win1HS Model No.: LCT-17HT Version: 1.0...
  • Page 153 -153 - WIn1HE Win2V Win2HS Win2HE Win3V Win3HS Win3HE Model No.: LCT-17HT Version: 1.0...
  • Page 154 -154 - Win4V Win4HS Win4HE Win1SH Win2SH Win3SH WiN4SH Model No.: LCT-17HT Version: 1.0...
  • Page 155 Meanwhile the internal address pointer will be increased automatically. To read the content of font RAM, a READ to OSDFontM will cause a complete Font RAM word distributed to OSDFontL and OSDFontM . After that the internal address pointer is increased automatically. Model No.: LCT-17HT Version: 1.0...
  • Page 156 For the low range (address 0 - 255), a WRITE to OSDADL will forward the address directly to the internal address pointer without offset. A READ from OSDADL will get the low nibble (bit 0 to Bit 7) of the internal address pointer. Model No.: LCT-17HT Version: 1.0...
  • Page 157 Vsync coming), will show on the Intensity pin. 3. When WinFB_N is clear, FB pin deliver High state during Characters/shadow/background or window color display. Otherwise, FB pin will always drive low when window color is displaying. Model No.: LCT-17HT Version: 1.0...
  • Page 158 Point to the first display row in the Display RAM Note: 1. The first row in the Display RAM, which will be mapped to the screen as the top display row, will be defined by OSDStartRow. Model No.: LCT-17HT Version: 1.0...
  • Page 159 In/Out Wipe In or Wipe Out is rendering WipeEna Wipe In/Out enable bit Not used Should be kept at 0 Red color of color index Green color of color index Blue color of color index Intensity color of color index Model No.: LCT-17HT Version: 1.0...
  • Page 160 Bit 0 to Bit3. OSD menu and Windows will be displayed on top of this monitor background color. Wipe In/Out = 1 WipeD = 1 Wipe In/Out = 1 WipeD = 0 Wipe In/Out = 0 WipeD = 1 Wipe In/Out = 0 WipeD = 0 Wipe In/Out Operation Model No.: LCT-17HT Version: 1.0...
  • Page 161 0: displaying or not displaying toggled per 32Vsync pulses 1: displaying or not displaying toggled per 64Vsync pulses 8. OSDE, OSD enable bit 0: OSD disabled; OSDE can be also clear by hardware after Wipe Out is performed 1: OSD enabled Model No.: LCT-17HT Version: 1.0...
  • Page 162 Data port of the OSD window register. This register was the data port when access the OSD window registers. Write data to this register will trigger a write operation to one of the 16 OSD registers selected by the OSDWindow_Addr. Model No.: LCT-17HT Version: 1.0...
  • Page 163 The ending column of Window 1 in the Display RAM H1MAX0 Win1R The Red color of window color index Win1G The Green color of window color index Win1B The Blue color of window color index Model No.: LCT-17HT Version: 1.0...
  • Page 164 It is very important to know the programmed range for Window 1 and Window 2 must be covered by the original visible domain, defined by OSDStartRow and EOD bit setting for the last display row. Model No.: LCT-17HT Version: 1.0...
  • Page 165 3 – 2 W1SHW1 - W1SHW0 The width of the window shadow W1SHH1 - W1SHH0 The height of the window shadow Note: 1. The color of the window shadow is encoded as follows: Model No.: LCT-17HT Version: 1.0...
  • Page 166 (Defining the window shadow of window 4. For the details, please refer to WIN1SH) Win1V = 8CH (Row 8 to Row 12); Win1HS = 2CH (Starting Column = 5); Win1HE = A6H (Ending Column = 20; Yellow) Model No.: LCT-17HT Version: 1.0...
  • Page 167 Win2HE = 69H (Ending Column = 13; Light Blue) SHH1 = 11; SHH2 = 11 SHW1 = 11; SHW2 = 01 SHW1 SHH1 SHW2 SHH2 SHH1 SHW1 SHH2 SHW2 FIGURE 25 .This Figure Show the OSD Window Operation Model No.: LCT-17HT Version: 1.0...
  • Page 168 HVPwth EOEnable VPW3 VPW2 VPW1 VPW0 HPW2 HPW1 HPW0 (D7H) PoutPolPos VCoast VCoast Vshift3 Vshift2 Vshift1 Vshift0 Vout- Hout- (D8H) Delay1 Delay0 HfpHigh Hfp9 Hfp8 Hfp7 Hfp6 Hfp5 Hfp4 Hfp3 Hfp2 (D9H) Model No.: LCT-17HT Version: 1.0...
  • Page 169 Vsep0 00: Csync/DE + VsyncSep 01: Hsync + VsyncSep 10: Hsync + VsyncSep XOR Vsync 11: Hsync + Vsync (if SelDE = 1, 00 is chosen, i.e. DE is treated as one kind of Csync) Model No.: LCT-17HT Version: 1.0...
  • Page 170 0: odd field/1st field; with earlier H sync 1: even field/2nd field; with lagged H sync 3 Vpresence The presence status of Vsync 0: Not present 1: Present 2 Hpresence The presence status of Hsync/Csync 0: Not present 1: Present Model No.: LCT-17HT Version: 1.0...
  • Page 171 HsyncOut; if the pulse of incoming Vsync is missing, an artificial pulse will be inserted with pulse width defined by VPW. The tailing edge of VsyncOut is also close to the tailing edge of the inputted Vsync but snapped to the leading edge of HsyncOut Model No.: LCT-17HT Version: 1.0...
  • Page 172 0: (default) even/odd flag will be disabled. 1: even/odd flag will be readable and used Vpw3 - Vpw0 There are 16 programmable values to set the pulse width of VsyncOut 2*(Vpw + 1) => 2, 4, 6, 30, 32 H lines. Model No.: LCT-17HT Version: 1.0...
  • Page 173 001: After 1 H line 010: After 2 H lines 011: After 3 H lines 100: After 4 H lines 101: After 5 H lines 110: After 6 H lines 111: After 7 H lines Model No.: LCT-17HT Version: 1.0...
  • Page 174 The low nibble of V free run period (11 - 0) Vfperiod0 Hfperiod1 - The low nibble of H free run period (9 - 0) Hfperiod0 VfpHigh (0xDB) Vfperiod11 - The high nibble of V free run period (11 - 0) Vfperiod4 Model No.: LCT-17HT Version: 1.0...
  • Page 175 STV start position (This bit also defines the CLKV start position) 0: (default) Normal start. 1: Late start. POL_MODE The toggle duration of POL (polarity output signal) pin 0: (default) toggle per H line. 1: toggle per 2H lines Model No.: LCT-17HT Version: 1.0...
  • Page 176 1: TCON is configured for 6-bit (for each RGB) panel SINGLE_HMS This register defines the operation of HMS is based on two single port (24/18 bits) or one dual port (48/36 bits) 0 : EVEN/ODD is calculated separately 1 : EVEN/ODD is calculated together Model No.: LCT-17HT Version: 1.0...
  • Page 177 23, 22 02,94 TC_GPO1_HACTIVE[10:0] duration counter value. GPO1 Vertical Start Define the GPO1 vertical start counter 25, 24 00,23 TC_GPO1_VSTART[10:0] value GPO1 Vertical End Define the GPO1 vertical end duration 27, 26 03,00 TC_GPO1_VEND[10:0] counter value. Model No.: LCT-17HT Version: 1.0...
  • Page 178 Define the STH signal horizontal start 31, 30 01,28 TC_STH_HSTART[10:0] counter value. NOTE: The active duration of STH pulse is always one-pixel width. STH Vertical End Define the STH signal vertical end 33, 32 00,23 TC_STH_VEND[10:0] counter value Model No.: LCT-17HT Version: 1.0...
  • Page 179 Define the width of STH pulse Reserved 48-4F GPO2 Horizontal Start 51, 50 01,28 Define the GPO2 horizontal start TC_GPO2_HSTART[10:0] counter value. GPO2 Horizontal Active 53, 52 02,94 Define the GPO2 horizontal active TC_GPO2_HACTIVE[10:0] duration counter value Model No.: LCT-17HT Version: 1.0...
  • Page 180 = 10: OR with TC_GPO1, = 11: select TC_GPO1 or TC_GPO2 alternately on the rising edge of HS or VS which is selected by TC_GPO2_CONTROL[4] = 0 : toggle on HS = 1: toggle on VS Reserved Model No.: LCT-17HT Version: 1.0...
  • Page 181 -181 - 8.0 PACKAGE OUTLINE 8.1 128l LQFP Model No.: LCT-17HT Version: 1.0...
  • Page 182 -182 - 8.2 160L LQFP Model No.: LCT-17HT Version: 1.0...
  • Page 183 -183 - 8.3 160 QFP Model No.: LCT-17HT Version: 1.0...

  • Page 184: Block Diagram

    -184 - BLOCK DIAGRAM Model No.: LCT-17HT Version: 1.0...

  • Page 185: Tv Tuner

    -185 - TV TUNER Model No.: LCT-17HT Version: 1.0...

  • Page 186: Exploded View & Part List

    -186 - EXPLODED VIEW AND PART LIST Model No.: LCT-17HT Version: 1.0...

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