IBM 7220 Instruction Manual page 113

Dsp lock-in amplifier
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Demodulator and Output Processing
Oscillator
Orthogonality
Drift
Acquisition Time
Internal Reference
External Reference
Reference Frequency Meter Accuracy
120 kHz > F > 40 kHz
40 kHz > F > 400 Hz
400 Hz > F > 1 mHz
Description
Output Zero Stability
Digital Outputs
Displays
Analog Outputs
Harmonic Rejection
Time Constants
Digital Outputs
Fast Outputs
Roll-off
Synchronous Filter Operation
Offset
Frequency
Range
Setting Resolution
Absolute Accuracy
Distortion (THD)
Appendix A, SPECIFICATIONS
90º ±0.0001º
< 0.01º/ºC below 10 kHz
< 0.1º/ºC above 10 kHz
instantaneous acquisition
2 cycles + 50 ms
±4 Hz
±0.8 Hz at F = 40 kHz improving to
±0.008 Hz at F = 400 Hz
±0.040 Hz at F = 400 Hz improving to
better than ±0.0001 Hz at F = 1 mHz
2 × 18-bit ADCs driving two DSP elements
managed by a powerful 68000-series host
processor
No zero drift on all settings
No zero drift on all settings
< 5 ppm/ºC
-90 dB
5 ms to 100 ks in a 1-2-5 sequence
10 µs to 640 µs in a binary sequence
6, 12, 18 and 24 dB/octave
Available for F < 20 Hz
Auto and Manual on X and Y: ±300 % FS
0.001 Hz to 120 kHz
0.001 Hz
25 ppm + 30 µHz
-80 dB at 1 kHz
A-3

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