Camera Schematic Diagram - Panasonic NV-GS30EG Service Manual

13.18. CAMERA SCHEMATIC DIAGRAM

(MAIN C B A.)
REFER TO MAIN CONNECTION
TO MAIN CN(E-7)
<TO CCD>
C6 15V
C7 -7V
C8 OUT
C13 SUB
G
C16 H2
C15 H1
C14 R
C9 V1
C10 V2
C11 V3
C12 V4
F
E
D
C
B
A
1
A1
C229
A2
0.1
A3
12.0
20
VHH VM24
IC205
MN31121SA
(CCD V DRIVE)
SUB
1
-7.6 -7.6
C203 C204 D202
16V10 16V10 RB520530
CL209
C220
0.1
C208 C206
6V10 0.01
IC202
27
C1AB00001725
(CDS/AGC/AD)
1.4 VRM
28
C213
1
2.0 VRT
29
C215
1
0.9 VRB
30
C212
1
2 7 DVDD
31
C209
0.1
DVSS
32
CAM CS 2.8 CS
33
CAM AFDR DTO 0 SDATA
SERIAL
34
INTERFACE
CAM AFDR CLK 2.8 SCK
35
ADINO 1.3 DO
36
1
1.4
2
A4 A5
C202 R204
35V1 3300
-7.1 -7.1 12.0 2.6 2.7
19 18 17 16 15 14 13
V4 V3 VH GND V3 CH2
VL V2 VM13 V1 VDC V1 CH1
2 3 4 5 6 7 8
-0.3 -0.3 3.3 0.1 2.7
R202
3300
A7 A8
C216
R206
33K 0.01
2.7 1.2 1.9 1.9 1.9 1.9
26 25 24 23 22 21 20
BIAS
GENERATOR
CDS
DC OFFSET
COMPENSATION
CIRCUIT
PGA
10BIT
ADC
TIMING
GENERATOR
OUTPUT LATCH CIRCUIT
2 3 4 5 6 7 8
1.3 1.3 1.3 1.6 1.0 0.6 0.3
3 4
A6
R210
C205
1M
1000P
2.6
12 11
V4 NC
V2 ISUB
9 10
0.1 2.7
R203 D201
3300 MA2J11100L
A9 A10
R213
0
R212
0
C217
1
2.7
19
AVSS
18
DS2 0.7
17 B1
DS1 0.7
16 B2
CPOB 0
15 B3
R209
0
PBLK 0
14
DVDD 2 7
13
ADCLK 1.3
12
DVSS
11
DRDVDD
0
10
C218
0.01
9
0.1
5
IC201
2
MN52A4
24
(CG/H DRIVE)
25 VSS
3.3
26 VDD2
1.6
A1 27 H2
28 VSS
3.3
29 VDD2
1.6
A2 30 H1
0.3
A3 31 R
C201
0.1
32 VSS
3.3
33 VDD2
2.7
34 VDD1
35 PAL/NTS
36 TEST4
TEST3
37
0
C214
4.7
R214
0
C219
6V10
NOTE:
THE MEA
DIAGRAM
6
60