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Danville Signal Processing dspstak 21262sx User Manual

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Danville Signal Processing, Inc.
dspstak™ 21262sx
User Manual
Version 1.10

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Summary of Contents for Danville Signal Processing dspstak 21262sx

  • Page 1 Danville Signal Processing, Inc. dspstak™ 21262sx User Manual Version 1.10...

  • Page 2: Contact Information

    Under the copyright laws, this manual may not be reproduced in any form without prior written permission from Danville Signal Processing, Inc. Danville Signal Processing, Inc. strives to deliver the best product to our customers. As part of this goal, we are constantly trying to improve our products. Danville Signal Processing, Inc., therefore, reserves the right to make changes to product specification or documentation without prior notice.

  • Page 3: Table Of Contents

    Table of Contents Overview ................5 Introducing dspstak™................5 dspstak™ 21262sx .................5 Introduction...................6 Hardware Description............7 Power Supply ..................7 RS-232 Interface ..................8 USB Interface..................9 Interconnect Port ...................9 Programmable Clocks ................9 JTAG Emulation Port ................10 dspstak™ 21262sx Architecture ........10 Hardware – ADSP-21262 Core ............10 DAI......................10 Parallel Port ..................13 SPI Port....................14...
  • Page 4 USB & PLD Registers ............29 Addressing USB & PLD Registers ............29 PLD Output & USB Status Registers .............29 Memory Map..................30 USB Port....................30 PLD Output Registers................32 Software................34 Schematic ...............34 Mechanical Drawings.............34 Product Warranty ............35 dspstak™ 21262sx User Manual Page 4...

  • Page 5: Overview

    You can also create your own. dspstak™ 21262sx This manual covers the dspstak 21262sx DSP Engine and is complemented by the dspstak Family Users Manual. The family manual covers topics that all dspstaks have in common. You will want to review the family manual for mechanical dimensions, system configurations, basic connector specifications, etc.

  • Page 6: Introduction

    (SPORTs) and a SPI port. The dspstak 21262sx Interconnect Port supports the complete DAI interface, SPI, general I/O, clocks and power connections. The dspstak 21262sx also includes USB and RS-232 ports for easy interfacing to the outside world. It also has a JTAG interface to facilitate program development.

  • Page 7: Hardware Description

    The dspstak 21262sx uses a standard 2.1/5.5mm coaxial power jack to provide power to itself and also any I/O modules via the Interconnect Port. From the dspstak 21262sx view, this supply may be either an AC supply or a DC supply with the center of the coaxial power plug connected as the positive pin.

  • Page 8: Rs-232 Interface

    The RS-232 port is provided by a dedicated microcontroller that also has other functions on the dspstak 21262sx. These functions are all available via the SPI port of the DSP. The API for these functions is described in the Software Section of this manual. There are also software examples on calling these functions on the CD.

  • Page 9: Usb Interface

    When the dspstak 21262sx is programmed using the RS-232 interface, only RD & TD are used. DTR, DSR & DCD are simply connected together and ignored by the dspstak. The dspstak 21262sx supports standard bauds of 9600, 19.2k, 38.4k, 57.6k, 115.2k and 230.4k.

  • Page 10: Jtag Emulation Port

    JTAG Emulation Port The dspstak 21262sx has a right angle JTAG connector (JH3) mounted on the lower edge of the pcb assembly. This connector is assessable even when a dspstak I/O Module is positioned above the dspstak 21262sx. Danville JTAG connectors are smaller than the standard ADI recommended JTAG header.
  • Page 11 Module, then you may map the DAI any way you want on the Interconnect Port. We expect that future dspstak DSP Engines will also have DAI mapped connections routed to the same connections on the Interconnect Port. Here are the DAI to Interconnect Port Mappings: A&C Name 21262sx...
  • Page 12 A&C Name Notes RFS0 DAI 7 TFS0 DAI 8 RCLK0 DAI 9 TCLK0 DAI 10 #RESET0 DTB0 DAI 11 DRB0 DAI 12 Vd+3.3 Vd+3.3 SPORT 1 – Full Duplex DRA1 DAI 13 DTA1 DAI 14 MCLK1 Programmable Clock RFS1 DAI 15 TFS1 DAI 16 RCLK1...

  • Page 13: Parallel Port

    (A23 or A15 = 0) • A low profile board will fit between the dspstak 21262sx and an I/O Module. • A special 2mm male header can be used to connect from a dspstak I/O Module to JH2 but there is no guarantee that another dspstak DSP Engine will be compatible.

  • Page 14: Spi Port

    SPI Port The SPI is used as a general purpose control bus on the dspstak 21262sx. It is connected to two onboard components, a serial flash memory and the Peripheral Microcontroller. It is also available on the Interconnect Port to control data converters and provide general purpose I/O expansion.

  • Page 15: Programming The Dspstak™ 21262Sx

    Configuration Header (JH5). The purpose of the programming modes is to establish what the dspstak 21262sx will do when it comes out of reset. Four of the programming modes are reserved for standard dspstak 21262sx functions and the remaining four are available for user programs.

  • Page 16: Configuration Jumpers

    * Jumper On = 0 Programming the Clock – Mode 7 The dspstak 21262sx uses a Cypress Semiconductor CY22393 programmable clock generator to provide clocks for the Peripheral Microcontroller, the ADSP-21262, and the Interconnect Port. The Interconnect Port clocks are SYSCLK, MCLK0 & MCLK1.
  • Page 17 • Create a new JEDEC file using CyberClocks™. The file 21262.JED is included on the CD. This is the factory default and a good place to start. • Power Up or Reset the dspstak 21262sx. You should see a Clock> prompt. You may wish to type ? to see the available commands.

  • Page 18: Uploading Programs - Mode 6

    RAM is overwritten. If the dspstak 21262sx is connected to an ASCII terminal via either RS-232 or USB and it is operating in Mode 6, you have a five second window to interrupt the boot process before the application program is automatically loaded.
  • Page 19 If USB is used, the baud settings are ignored and the interface will operate like a very fast COM port. • Power Up or Reset the dspstak 21262sx. You should see a DSP> prompt followed by moving # symbols. After about 5 seconds, the application program will boot unless you press a key to interrupt the boot process.
  • Page 20 • After the program is uploaded, a checksum is calculated and you have the opportunity to enter a description of the program. The program description is an ASCII string that you can use to identify your program. It does not impact the function of the DSP module in any way, but can be a helpful way to track program revisions.

  • Page 21: Peripheral Microcontroller Api

    Peripheral Microcontroller API The Peripheral Microcontroller communicates via the SPI bus using a 3 byte packet structure. Flag 1 serves as the SPI slave select line. The SPI bus is bi-directional. Commands are always initiated by the DSP. The Peripheral Microcontroller only responds. The Peripheral Microcontroller is not a fast device, as such you must delay transmission of each byte by 15us or more.

  • Page 22: System Commands

    System Commands Status Description: Peripheral Microcontroller Status Command: Status is automatically updated each time a packet is transmitted by the DSP. It is reported in Byte 1 in the next packet. This means that the status reported in the very first packet may not be valid.
  • Page 23 PM_Cmd_VERSION Description: Returns the firmware version of the Peripheral Microcontroller Command: 0x03 Data: Don’t Care Response: 0x00 The current version is 0x00, but future versions will increment this number. This allows you to determine what functions this particular Peripheral Microcontroller implements in the event that there are changes in a later version.
  • Page 24 PM_Cmd_RESET Description: Reset the dspstak 21262sx Command: 0x0A Data: 0xC4 Response: Don’t Care This is a software reset that acts just like a hardware reset. PM_Cmd_MODE Description: Return Mode Jumper Settings Command: 0x0B Data: Don’t Care Response: See Below Returns the mode setting selected by M2, M1, M0 in the lowest three bits of the response.

  • Page 25: Com Port Commands

    PM_Cmd_RESYNC Description: Resync the Peripheral Microcontroller Command: 0x0F Data: 0x0F Byte 3 (DSP): 0x0F Response: 0x00 This command is used in the event that packet order is somehow misaligned. After this command is executed, the Peripheral Controller will expect the next byte to be Byte 1.
  • Page 26 PM_Cmd_COM_BAUD Description: Sets the Baud rate Command: 0x04 Data: See Below Response: 0x00 Baud = (1.152 * 10^6 ) / (DATA + 1) Typical Values: 230.4K 0x04 115.2K 0x09 38.4K 0x1F 19.2K 0x3D 9600 0x79 PM_Cmd_COM_RESET Description: Resets the Com Port Command: 0x08 Data:...

  • Page 27: Ee Memory Commands

    EE Memory Commands PM_Cmd_EE_ADDR Description: Sets the EE Address Pointer Command: 0x05 Data: EE Address Response: 0x00 The EE Address pointer is auto incremented after every valid EE_WR or EE_RD operation. The valid address range is 0x00 to 0x7F (128 bytes). The EE Data at Address 0x7F is reserved by the bootloader to hold the default baud rate, so don’t overwrite this location.
  • Page 28 PM_Cmd_EE_RD Description: Read EE at current EE Address Command: 0x0D Data: Don’t Care Response: EE Data EE Data is read from the current address pointed to by the EE Address Pointer. This address is set by the EE_ADDR command and auto incremented after every EE_WR or EE_RD.

  • Page 29: Usb & Pld Registers

    USB & PLD Registers The dspstak 21262sx uses a PLD for I/O expansion. It is connected to the DSP’s Parallel Port. The USB port is also connected to the Parallel Port. It uses the PLD for part of its internal interface.

  • Page 30: Memory Map

    USB Port The USB port on the dspstak 21262sx uses an FTDI FT245BM USB transceiver. This device is a USB 2.0 compliant, full speed part (12Mb/s). This part is very easy to use since in most cases it just looks like a COM Port to the USB Master.
  • Page 31 USB Status Bits Address: 0x9000 PWREN: 0 – USB Port is enumerated TXE: 0 – Transmit FIFO can accept a byte RXF: 0 – Receive Buffer has a byte ready All other bits are Don’t Care. Reading the USB Port •...

  • Page 32: Pld Output Registers

    PLD Output Registers PLD_DAI_SPI_SELECT Description: Selects I/O or SPI SS mapping Destination: Interconnect Port Address: 0xA000 IO7/#SPISS3: 0 – IO7 1 – #SPISS3 IO6/#SPISS2: 0 – IO6 1 – #SPISS2 IO5/#SPISS1: 0 – IO5 1 – #SPISS1 All other bits are Don’t Care. This register determines whether the IO Pins on the Interconnect Port are bi- directional GP I/O Pins or SPI slave select lines.
  • Page 33 PLD_OUT1 Description: 3.3V Digital Output Destination: Interconnect Port Address: 0xC000 #RESET: 0 – Output Low #RESET1 0 – Output Low #RESET0: 0 – Output Low LED4: 0 – Output Low All other bits are Don’t Care. This register causes the LED4 and the RESET lines on the Interconnect Port to be driven.

  • Page 34: Software

    If you are designing your own I/O Module or want to mount the dspstak 21262sx in an unusual configuration, you may want to check with us for suggestions, design review, etc. We also have PCB templates available to help you get started on an I/O Module layout.

  • Page 35: Product Warranty

    If Danville Signal Processing receives notice of such defects during the warranty period, Danville Signal Processing shall, at its option, either repair or replace software media or firmware, which do not execute their programming instructions due to such defects.

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