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Omega PCI-DAS1602/16 User Manual

Multifunction measurement and control board
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PCI-DAS1602/16

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Summary of Contents for Omega PCI-DAS1602/16

  • Page 1 User's Guide http://www.omega.com e-mail: info@omega.com PCI-DAS1602/16...

  • Page 2: Table Of Contents

    4.2 Connecting Signals to the PCI-DAS1602/16 ........

  • Page 3: Introduction

    Even the connector has changed. New, denser connectors allow up to 100 signal lines where once 37 was the the standard. Because of the improvements in technology, the PCI-DAS1602/16 is easier to install and use than any previous DAS16. There is not a single switch or jumper on the board, so go ahead and install the PCI-DAS1602/16 into your computer then turn your computer on.

  • Page 4: Instacal

    After installing InstaCal you should re-start your computer to take advantage of changes made to the AUTOEXEC and CONFIG files. The PCI-DAS1602/16 does not have to be installed in order for InstaCal to run, but must be in order to test or calibrate the board.

  • Page 5: Running Instacal

    IN and OUT statements can write and read the PCI-DAS1602/16 registers by reference to the base address and the offset from base address corresponding to the chart of registers located elsewhere in this manual.

  • Page 6: Testing The Installation

    Not only that, but if you install another PCI board in a computer after the PCI-DAS1602/16 addresses have been assigned, those addresses may be moved by the plug & play software when the second board is installed.

  • Page 7: Hardware Connections

    4.0 HARDWARE CONNECTIONS 4.1 Connector Pin Diagram The PCI-DAS1602/16 employs the new 100 pin connector. Please make accurate notes and pay careful attention to wire connections. In a large system a misplaced wire may create hours of work ‘fixing’ problems that do not exist before the wiring error is found.

  • Page 8: Connecting Signals To The Pci-Das1602/16

    The C100-FF-2 cable is a pair of 50 pin ribbon cables. At one end they are joined together with a 100 pin connector. From the 100 pin connector designed to mate with the PCI-DAS1602/16 connector, the two 50 pin ribbon cables diverge and are terminated at the other end with standard 50 pin header connectors.
  • Page 9 Signal High (CH# HI), Signal Low (CH# LO) and Signal Ground (LLGND). A differential connection allows you to connect the PCI-DAS1602/16 to a signal source with a ground that is different, but not isolated from the PC ground, but less than 10V difference, and still make a true measurement of the signal between CH# HI and CH# LO.

  • Page 10: Features And Functions Overview

    5.0 Features and Functions Overview The PCI-DAS1602/16 is a multifunction measurement and control board. The design of the board may be simplified into several blocks containg the major functions of the board. Please take a moment to examine the diagram here.

  • Page 11: Programming & Applications

    DAS family, there is no correspondence between registers. Software written at the register level for the other DAS's will not work with the PCI-DAS1602/16. This includes any driver or library where the target board is other than a PCI-DAS1602/16.

  • Page 12: Self-Calibration Of The Pci-Das1602/16

    All adjustments are made via 8-bit calibration DACs or digital potentiometers referenced to an on-board factory calibrated standard. The PCI-DAS1602/16 is shipped fully-calibrated from the factory with cal coefficients stored in nvRAM.

  • Page 13: Analog Output Calibration

    7.2 Analog Output Calibration The analog output circuits are calibrated for both gain and offset. Coarse and Fine offset adjust- ments are made in the output buffer section. The tuning range of these adjustments allows for maximum DAC and output buffer offsets. Coarse and Fine gain calibration is performed via adjustments to the DAC reference.

  • Page 14: Pci-Das1602/16 Register Description

    8.0 PCI-DAS1602/16 Register Description The PCI-DAS1602/16 operation registers are mapped into the PC I/O address space. Unlike its ISA counterpart, this board has several base addresses each corresponding to a reserved block of addresses in I/O space. Of six Base Address Regions (BADR) available in the PCI 2.1 specifica-...
  • Page 15 INT[1:0] General Interrupt Source selection bits. INT1 INT0 Source External End of Channel Scan AD FIFO Half Full AD FIFO Not Empty INTE Enables interrupt source selected via the INT[1:0] bits. 1 = Selected interrupt Enabled. 0 = Selected interrupt Disabled DAHFIE Enables DAC FIFO Half-Full signal as interrupt source.
  • Page 16 DAEMCL A write-clear to reset DAEM interrupt status. 1= Clear DAEM interrupt. 0 = No effect. NOTE: It is not necessary to reset any write-clear bits after they are set. READ DAEMI LADFUL ADNE ADNEI ADHFI EOBI XINTI EOAI DAHFI Write operations to this register allow you to check status of the selected interrupts and ADC FIFO flags.

  • Page 17: Adc Channel Mux And Control Register

    ADNEI Status bit of ADC FIFO Not-Empty interrupt. Used to indicate ADC conversion complete in single conversion applications. 1 = Indicates an ADC FIFO Not-Empty interrupt has been latched and that one data word may be read from the FIFO. 0 = Indicates an ADC FIFO Not-Empty interrupt has not occurred. FIFO has been cleared, read until empty or ADC conversion still in progress.
  • Page 18 Range 2.5V 1.25V SEDIFF Selects measurement configuration for the Analog Front-End. 1 = Analog Front-End in Single-Ended Mode. This mode supports up to 16 channels. 0 = Analog Front-End in Differential Mode. This mode supports up to 8 channels. UNIBIP Selects offset configuration for the Analog Front-End.

  • Page 19: Trigger Control/Status Register

    Note: For ADPS[1:0] = 00 case, SW conversions are initiated via a word write to BADR2 + 0. Data is 'don't care.' READ Real-time, non-latched status of ADC End-of-Conversion signal. 1 = ADC DONE 0 = ADC BUSY 8.2.3 Trigger Control/Status Register BADR1 + 4 This register provides control bits for all ADC trigger modes.
  • Page 20 This bit selects whether external ADC control signal is an edge or a level. Use TGPOL signal to create rising edge or high level input. 1 = Edge triggered. 0 = Level triggered. TGEN This bit is used to enable External Trigger/Gate function 1 = Selected Trigger Source enabled.
  • Page 21 Note that the CHI Threshold is set by DAC1, CLO Threshold is set by DAC0. HMODE CHI >= CLO by definition. CHI_EN CLO_EN HMODE Analog Trigger/Gate Function Mode Signal goes HIGH when ATRIG is more positive than Negative CHI. Signal goes low when ATRIG becomes more Hysteresis negative than CLO.

  • Page 22: Calibration Register

    PRTRG FFM0 ARM is set... FIFO Mode Sample CTR Starts on... Via SW when remaining # Samples >1 FIFO count <1 FIFO Normal Mode ADHF ------------------------ ---------------------------------- Via SW immediately 1/2 FIFO < # Samples < 1 FIFO Normal Mode ADC Pacer Via SW immediately # Samples <1/2 FIFO...
  • Page 23 WRITE CALEN CSRC2 CSRC1 CSRC0 SEL08 SEL8402 SEL8800 CD[7:0] These 8 bits are the D/A code inputs for the analog-front DAC08 offset calibration DAC. Complimentary current outputs of the DAC08 are equal at mid-scale, 7Fh. This should be the default, non-calibrated value. SEL8800 This bit enables the 8-bit trim DACs for the following circuits: DAC Channel...

  • Page 24: Dac Control/Status Register

    CSRC[2:0] These bits select the different calibration sources available to the ADC front end. CSRC2 CSRC1 CSRC0 Cal Source AGND 7.0V 3.5V 1.75V 0.875V -10.0V VDAC0 VDAC1 CALEN This bit is used to enable Cal Mode. 1 = Selected Cal Source, CSRC[2:0], is fed into Analog Channel 0. 0 = Analog Channel 0 functions as normal input.
  • Page 25 This bit enables the Analog Out features of the board. 1 = DAC0/1 enabled. 0 = DAC0/1 disabled. START This bit starts FIFO'd DAC operations. If used with DAXTRG, the external trigger signal, the START bit is used to arm the operation. 1 = Start/Arm FIFO operations.

  • Page 26: Badr2

    READ LDAEM LDAEM This is the latched version of the DAC FIFO_EMPTY signal. This bit must be write-write cleared with the DAEMCL bit. 1 = DAC FIFO was emptied at some point during FIFO'd operations. Incorrect data may have been clocked into the selected DAC(s). 0 = DAC FIFO did not empty during FIFO'd operations.

  • Page 27: Badr3

    The I/O Region defined by BADR3 contains data and control registers for the ADC Pacer, DAC Pacer, Pre/Post-Trigger Counters and High-Drive Digital I/O bytes. The PCI-DAS1602/16 has two 8254 counter/timer devices. These are referred to as 8254A and 8254B and are assigned as...

  • Page 28: High-Drive Digital I/O Data And Control Registers

    8254 data sheet, available from Intel or Harris. 8.4.2 High-Drive Digital I/O Data and Control Registers The 24 High-Drive DIO lines on the PCI-DAS1602/16 are grouped as three byte-wide I/O ports. Port assignment and functionality is identical to that of the industry standard 8255 Peripheral Interface operating in Mode 0.
  • Page 29 8255 in Mode 0. WRITE Note: Bits 3,5-7 are hardwired to the values shown (Mode 0). Actual writes to these bit positions are "don't care." The following table summarizes the possible I/O Port configurations for the PCI-DAS1602/16 HDIO: Page 28...

  • Page 30: Dac Pacer Clock Data And Control Registers

    PORT A PORT C PORT B PORT C UPPER LOWER 8.4.3 DAC Pacer Clock Data and Control Registers 8254B COUNTER 0 DATA - ADC PRE-TRIGGER INDEX COUNTER BADR3 + 8 READ/WRITE Counter 0 of the DAC 8254 device is actually used as the ADC Pre-Trigger index counter. This counter serves to mark the boundary between pre- and post-trigger samples when the ADC is operating in Pre-Trigger Mode.

  • Page 31: Badr4

    8254B COUNTER 2 DATA - DAC PACER DIVIDER UPPER BADR3 + Ah READ/WRITE Counter 1 provides the lower 16 bits of the 32-bit pacer clock divider. Its output is fed to the clock input of Counter 2 which provides the upper 16-bits of the pacer clock divider. The clock input to Counter 1 is a precision 10MHz oscillator source.
  • Page 32 WRITE DA15 DA14 DA13 DA12 DA11 DA10 DA[15:0] These bits represent the DAC data word. Format is dependent upon offset mode as described below: Bipolar Mode: Offset Binary Coding 0000 h = -FS 7FFFh = Mid-scale (0V) FFFFh = +FS - 1LSB Unipolar Mode: Straight Binary Coding 0000 h = -FS (0V) 7FFFh = Mid-scale (+FS/2)

  • Page 33: Dac Fifo Clear Register

    8.5.2 DAC FIFO Clear Register BADR4 + 2 DAC FIFO Clear register. A Write-only register. A write to this address location clears the DAC FIFO. Data is don't care. The DAC FIFO should be cleared before all new DAC operations. Page 32...

  • Page 34: Electrical Specifications

    9.0 Electrical Specifications PCI-DAS1602/16 Typical for 25 DegC unless otherwise specified. Analog input section A/D converter type AD976ABN Resolution 16 bits Programmable ranges ±10V, ±5V, ±2.5V, ±1.25V, 0 - 10V, 0 - 5V, 0 - 2.5V, 0 - 1.25V A/D pacing...
  • Page 35 Analog Output: Resolution 16 bits Number of channels D/A type AD669BR Voltage Ranges ±10V, ±5V, 0-5V, 0-10V. Independently selectable between channels. Offset error ±100uV max, all ranges (calibrated) Gain error ±30.5ppm max (calibrated) Differential nonlinearity ±1LSB max Integral nonlinearity ±1LSB max Monotonicity 16 bits at 25 DegC D/A Gain drift...

  • Page 36: Power Consumption

    Counter section Counter type 82C54 Configuration Two 82C54 devices. 3 down counters per 82C54, 16 bits each 82C54A: (Counters 1, 2, & 3) Counter 0 - ADC residual sample counter. Source: ADC Clock. Gate: Programmable source. Output: End-of-Acquisition interrupt. Counter 1 - ADC Pacer Lower Divider Source: 10 MHz oscillator Gate:...
  • Page 37 For Your Notes Page 36...
  • Page 38 EC Declaration of Conformity PCI-DAS1602/16 High speed analog I/O board for the PCI bus Part Number Description to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents: EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.

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