Table of Contents
Advertisement
HU430 NLX Motherboard User Guide
Appendix A.
Main Jumper Block, PL10
BF1 and BF0 set the processor bus/core multiplier ratio on P54C and P55C processors, and
BF2 is present to support the K6. The FS jumper selects a processor bus speed of 60 or 66
MHz.
The VGA jumper enables/disables the on-board VGA controller as follows:
VGA = IN
VGA = OUT
The AUDIO jumper enables/disables the on-board audio (if fitted) as follows:
AUD = IN
AUD = OUT
Note that the BIOS auto-detects a video card plugged into an expansion slot and disables the
on-board video. The VGA jumper provided disables the on-board VGA controller in
hardware in case there is a problem with the auto-disable function.
The PW3-0 jumpers select the value of the processor core voltage. This is necessary as P54C,
P55C and K6 processors require different core voltages. The board cannot automatically
detect the core voltage that is required by the processor and so this must be set manually.
The table below shows supported CPUs with their configuration jumper settings; note that the
presence of any processor type or speed in the table does not imply that it is or will be
available:
CPU
Core/bus
speeds
P54C
90/60 MHz
P54C
100/66 MHz
P54C
120/60 MHz
P54C
133/66 MHz
P54C
150/60 MHz
P54C
166/66 MHz
P55C
166/66 MHz
K6
166/66 MHz
P54C
200/66 MHz
P55C
200/66 MHz
K6
200/66 MHz
P55C
233/66 MHz
K6 0.35µm
233/66 MHz
K6 0.25µm
233/66 MHz
K6 0.25µm
266/66 MHz
K6 0.25µm
300/66 MHz
Mitsubishi Electric PC Division
Jumpers And Switches
Enable on-board VGA controller
Disable on-board VGA
controller
Enable on-board audio
Disable on-board audio
Ratio
PCI/ISA bus
BF2
speeds
3/2
30/7.5 MHz
OUT
3/2
33/8.33 MHz
OUT
2/1
30/7.5 MHz
OUT
2/1
33/8.33 MHz
OUT
5/2
30/7.5 MHz
OUT
5/2
33/8.33 MHz
OUT
5/2
33/8.33 MHz
OUT
5/2
33/8.33 MHz
OUT
3/1
33/8.33 MHz
OUT
3/1
33/8.33 MHz
OUT
3/1
33/8.33 MHz
OUT
7/2
33/8.33 MHz
OUT
7/2
33/8.33 MHz
OUT
7/2
33/8.33 MHz
OUT
4/1
33/8.33 MHz
IN
9/2
33/8.33 MHz
IN
BF1
BF0
FS
Pw2
Pw1
1
1
IN
IN
1
1
OUT
IN
1
0
IN
IN
1
0
OUT
IN
0
0
IN
IN
0
0
OUT
IN
0
0
OUT OUT OUT OUT
0
0
OUT
IN
OUT OUT
0
1
OUT
IN
0
1
OUT OUT OUT OUT
0
1
OUT
IN
OUT OUT
1
1
OUT OUT OUT OUT
1
1
OUT
IN
OUT OUT
1
1
OUT OUT
1
0
OUT OUT
0
0
OUT OUT
124575UG Revision 2
Pw0
Pw3
Cor
V
IN
IN
IN
3.5
IN
IN
IN
3.5
IN
IN
IN
3.5
IN
IN
IN
3.5
IN
IN
IN
3.5
IN
IN
IN
3.5
IN
2.8
IN
3.2
IN
IN
IN
3.5
IN
2.8
IN
3.2
IN
2.8
IN
3.2
IN
OUT OUT
2.2
IN
OUT OUT
2.2
IN
OUT OUT
2.2
Page 15 of 21
Advertisement
Table of Contents
