1. Manuals
  2. Brands
  3. Freescale Semiconductor Manuals
  4. PCI Card
  5. C29x
  6. User manual

Freescale Semiconductor C29x User Manual

Pcie card
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
C29x PCIe Card User Guide
Document Number: C29xPCIeUG
Rev 0, 10/2013

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the C29x and is the answer not in the manual?

Questions and answers

Summary of Contents for Freescale Semiconductor C29x

  • Page 1 C29x PCIe Card User Guide Document Number: C29xPCIeUG Rev 0, 10/2013...
  • Page 2 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 3: Table Of Contents

    3.3 Power Block Diagram...............................21 Chapter 4 On-Board Resources 4.1 DDR Memories.................................23 4.2 IFC....................................24 4.2.1 NOR Flash Memory.............................24 4.2.2 NAND Flash Memory............................25 4.3 SerDes....................................26 4.4 Ethernet.....................................27 4.4.1 eTSEC1................................27 4.4.2 eTSEC2................................27 4.5 eSPI....................................28 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 4 Watchdog Control and Status Register (CPLD_WDCSR)..................48 7.2.8 Watchdog Kick Register (CPLD_WDKICK)......................48 7.2.9 Fan Control and Status Register (CPLD_FANCSR)...................49 7.2.10 Panel LED Control and Status Register (CPLD_LEDCSR)................49 7.2.11 Miscellanies Control and Status Register (CPLD_MISCCSR)................50 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 5 7.2.14 Boot Configuration Register 2 (CPLD_BOOTCFG2)..................51 7.2.15 Boot Configuration Register 3 (CPLD_BOOTCFG3)..................52 7.2.16 Boot Configuration Register 4 (CPLD_BOOTCFG4)..................53 Chapter 8 Programming U-Boot 8.1 Programming U-Boot on a Board having no U-Boot Installed..................55 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 6 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 7: Acronyms

    Chapter 1 Introduction The C29x PCIe is a PCIe card with a Freescale C29x crypto coprocessor system-on-chip (SoC)/processor. 1.1 Acronyms The table below lists and explains the acronyms used in this document. Table 1-1. Acronyms Term Description Common On-Chip Processor...

  • Page 8: Related Documentation

    Explains the procedure to build, configure, and use different software components for the Freescale C29x crypto coprocessor device. C29x PCIe Card Getting Started Explains C29x PCIe board settings and physical connections needed to boot the board. Guide Freescale C29x Crypto Coprocessor...

  • Page 9: Chapter 1 Introduction

    JTAG 2x DUART 2x I2C eSPI, GPIO SEC2 4-lane 5 GHz SerDes SEC3 Figure 1-1. C29x block diagram The figure below shows the block diagram of the C29x PCIe card. RGMII GE PHY Magnetics TSEC1 VSC8641 DDR3 Reset Watch Dog...

  • Page 10: Board Drawing And Top View

    • POR configuration • Supports critical POR settings through DIP switches available on the board 1.4 Board Drawing and Top View The figure below shows C29x PCIe top side reference drawing. C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 11 Chapter 1 Introduction Figure 1-3. Top side reference drawing The C29x PCIe card measures 168 mm x 111 mm. It can be installed into a PCIe-x4, PCIe-x8, or PCIe-x16 slot on the PCIe motherboard. The figure below shows the top view of the C29x PCIe card.
  • Page 12 Board Drawing and Top View for Fan ETH0 TSEC1 ETH1 TSEC2 Switch UART Power ON/OFF JTAG Switch PCIe x4 Gold-finger 2x3 ATX Power Connector Figure 1-4. C29x PCIe card top view C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 13: Pcie Use Cases

    Perform the following steps to use the C29x PCIe card in the PCIe endpoint mode: 1. Connect the heat sink fan power line to J18. 2. Plug C29x PCIe into the PCIe slot on the motherboard. C29x PCIe supports x1, x2, and x4 configurations.

  • Page 14: Standalone Host Mode

    SW7[1] ON, cfg_cpu_boot=0 • SW7[5] ON, cfg_host_agt=0 The table below shows dual in-line package (DIP) switch settings of the C29x PCIe card in PCIe endpoint mode (800 MHz core, 400 MHz platform, PCIe-x4 configuration). Table 2-1. PCIe endpoint mode DIP switch settings SW4[1..8]...
  • Page 15 • Flow control: Hardware/None 6. Connect network cable to TSEC1. 7. Turn on ON/OFF switch to power on C29x PCIe. Now, you will see C29x PCIe boot up message on the computer console. Following are the device configurations required for this use case by setting DIP switch: •...

  • Page 16: Pkcal/Skmm Mode

    SW8[8] to 0. To enable the SKMM mode, set SW8[8] to 1. The PKCAL mode can be started from the PCIe endpoint mode. In PKCAL mode, a C29x processor only uses internal SDRAM, instead of DDR3/NOR flash/NAND flash. Therefore, DDR/NOR flash/NAND flash should not be initialized in the source code. In addition, the PKCAL mode requires the board to be booted from the PCIe slot.
  • Page 17 C29x supply Secure Boot mode to protect customer system. The customer can put secured encoded u-boot and other image into flash, and put the secure key into C29x silicon. If secured keys are matched, the image can be loaded and run. The secure boot mode can be enabled by setting SW7[6] to ON and cfg_sb_dis to 0.
  • Page 18 Secure Boot Mode C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 19: Clocks, Resets, And Power Control

    Chapter 3 Clocks, Resets, and Power Control 3.1 Clocks The figure below shows the C29x PCIe input clocks. C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 20: Resets

    • DDR_CLK is 100 MHz external clock • SD_REFCLK is 100 MHz, required for PCIe interface • TSEC_RX_CLK is 125 MHz, required for GE port • CPLD_REFCLK is 32.768 kHz, required for CPLD to work C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 21: Power Block Diagram

    Chapter 3 Clocks, Resets, and Power Control 3.2 Resets All resets for the C29x PCIe card are handled by CPLD. A power-on-reset is initiated by pressing the power switch, if the board is in a chassis. A warm reset is initiated by pressing SW1 on the board.
  • Page 22 (XVDD) (LDO) 3V3@4A ISL8204M For C29x: 2V5: LVDD 3V3: OVDD, 02VDD, BVDD, CVDD 2.5V MAX8869 (LDO) PS_VTT_EN TPS51200 MVREF 1V5/1V35@4A PS_GVDD_EN ISL8204M GVDD (GVDD) Figure 3-3. Power block diagram C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 23: On-Board Resources

    All these on-board resources are described, one by one, in the subsections that follow. 4.1 DDR Memories The C29x PCIe card supports DDR3 and DDR3L memories. The memory interface on the board is configured as DDR3/DDR3L. The DDR3/DDR3L memory and ECC are implemented as a single bank discrete chipset (x16).

  • Page 24: Ifc

    • NOR flash memory • NAND flash memory 4.2.1 NOR Flash Memory The C29x PCIe card provides NOR flash memory of 64 MB with 16-bit port size. The figure below shows the hardware connection between the C29x PCIe card and NOR flash memory.

  • Page 25: Nand Flash Memory

    SW5[7:8]. 4.2.2 NAND Flash Memory The C29x PCIe provides NAND flash memory of 4 GB with 8-bit port size. The figure below shows the hardware connectivity between the C29x PCIe card and NAND flash memory.

  • Page 26: Serdes

    BY_N signal to IFC_RB1_N. 4.3 SerDes On the C29x PCIe card, the SerDes module implements link serialization/deserialization and PCS functions for a PCI express link, operating at 2.5 or 5 Gbaud. The table below shows the different settings for SerDes.

  • Page 27: Ethernet

    These interfaces are compliant with the PCI Express Base Specification Revision 2.0, which supports root complex (RC) and endpoint (EP) configurations. 4.4 Ethernet The C29x PCIe card supports a maximum of two Ethernet ports. 4.4.1 eTSEC1 eTSEC1 10/100/1000 BaseT operates in the RGMII mode, and is directly connected to a Vitesse RGMII PHY (VSC8641), as shown in the figure below.

  • Page 28: Etsec2

    The eSPI is a full-duplex, synchronous, character-oriented channel that supports a four- wire interface (receive, transmit, clock, and slave select). The C29x processor has the ability to boot from an SPI serial flash device, in addition to supporting other peripheral devices conforming to the SPI standard.
  • Page 29 RJ45 pin number RS-232 signal DB9 female pin number Before powering up the C29x PCIe card, configure the serial port of the attached computer with the following values: • Data rate: 115200 bps C29x PCIe Card User Guide, Rev. 0, 10/2013...
  • Page 30 RS-232 • Number of data bits: 8 • Parity: None • Number of stop bits: 1 • Flow control: Hardware/None C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 31: Board Connectors, Led, And Push Button

    Chapter 5 Board Connectors, LED, and Push Button 5.1 Connectors The below table details all the connectors on the C29x PCIe card. Table 5-1. Connector settings Reference designator Description Notes GE1 and GE2 Ethernet ports First port: TSEC1 (RGMII) -> VSC8641 Second port: TSEC2 (RGMII) ->...

  • Page 32: Jtag/Cop Connector

    The JTAG connection is provided by a direct connection to the appropriate header connector. COP is a part of the C29x's JTAG module and is implemented as a set of additional instructions and logic. This port can connect to a dedicated emulator for extensive system debugging.

  • Page 33: Led

    Not connected. CKSTP_OUT Connected directly between the processor and JTAG/COP connector. Connected to ground. 5.5 LED The table below details LED settings for the C29x PCIe card. Table 5-5. LED settings Reference designator Used for Notes Indicating the status of C29x PCIe Sold green: Power-on is ok C29x PCIe Card User Guide, Rev.

  • Page 34: Push Button

    Table 5-5. LED settings Reference designator Used for Notes Flash green: Software boot is ok 5.6 Push Button The push button SW1 on the C29x PCIe card is used for reset. C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 35: Por Configuration

    Chapter 6 POR Configuration The C29x PCIe card has user selectable switches or registers, for evaluating different frequency and boot configuration for this device. The table below shows how POR configuration is done through switches. Table 6-1. POR configuration through switches...
  • Page 36 Reserved SW6[4] cfg_ddr_speed[0] 1588_CLK_OUT DDR complex speed cfg_ddr_speed[0]: configuration input SW6[5] cfg_ddr_speed[1] 1588_PULSE_O ON (0): DDR data rate is less than 967 MHz. Table continues on the next page... C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 37 GHz) SW7[3] cfg_io_port[1] IFC_AD14 SW7[2:4] ON ON OFF (001): PCIe-x4 SW7[4] cfg_io_port[2] IFC_BCTL (2.5 GHz) SW7[2:4] ON OFF ON (010): PCIe-x2 (5 GHz) Table continues on the next page... C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 38 1588_ALARM_OUT NC (1) Different voltage 0: DDR3L 1.35V, CKE low at reset level from 1: DDR3 1.5V, CKE low at reset DDR3L Table continues on the next page... C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 39 0: Lower order address bits are bits are multiplexed with data on multiplexed with IFC_AD[0:15] IFC data if NOR flash is used for booting Table continues on the next page... C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 40: Por Settings In Different Boot Location Modes

    800 MHz DDR, PCIe-x4 agent). Table 6-3. NOR flash POR settings for 800 MHz core SW4[1..8] 0101 1000 ON OFF ON OFF OFF ON ON ON Table continues on the next page... C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 41: Nand Flash Por Settings

    Table 6-6. NAND flash POR settings SW4[1..8] 0101 1000 ON OFF ON OFF OFF ON ON ON ON ON OFF ON ON OFF ON ON SW5[1..8] 0010 0100 Table continues on the next page... C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 42: Spi Flash Por Settings

    SW7[1..8] 1001 0111 OFF ON ON OFF ON OFF OFF OFF SW8[1..8] 0000 1011 ON ON ON ON OFF ON OFF OFF SPI flash POR DIP setting: • SW5[1..4]=0110 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 43: Cpld Specification

    Chapter 7 CPLD Specification This section describes the CPLD specification and register user interface in the C29x PCIe card. 7.1 Key Features The key features of CPLD are: • C29x reset signal generation and distribution • System reset features: • Power on and manual reset (PON_RST_N) •...

  • Page 44: Cpld Memory Map/Register Definition

    Boot Configuration Register 4 (CPLD_BOOTCFG4) 7.2.16/53 7.2.1 Chip ID1 Register (CPLD_CHIPID1) Address: 0h base + 0h offset = 0h Read CHIPID1 Write Reset CPLD_CHIPID1 field descriptions Field Description 0–7 Chip ID1. CHIPID1 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 45: Chip Id2 Register (Cpld_Chipid2)

    * Notes: • x depends on actual board setting.x = Undefined at reset. CPLD_HWVER field descriptions Field Description 0–7 Hardware version. The version field of the hardware board. HW_VER C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 46: Software Version Register (Cpld_Swver)

    GE1RST No reset occurs GE PHY1 reset signal is produced 2–6 This field is reserved. Reserved. Software reset. Write 1 to clear. SW_RST No reset occurs CPU reset occurs C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 47: Flash Control And Status Register (Cpld_Flhcsr)

    NOR flash bank select from CPLD override is disabled NOR flash bank select from CPLD override is enabled Boot from 16 bit NOR flash BOOT_SEL Boot from 8 bit NAND flash C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 48: Watchdog Control And Status Register (Cpld_Wdcsr)

    7.2.8 Watchdog Kick Register (CPLD_WDKICK) Address: 0h base + 13h offset = 13h Read Write WD_KICK Reset * Notes: • x depends on actual board setting.x = Undefined at reset. C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 49: Fan Control And Status Register (Cpld_Fancsr)

    Address: 0h base + 15h offset = 15h Read Reserved Write Reset CPLD_LEDCSR field descriptions Field Description Light emitting device. Panel LED is on Panel LED flashes at 0.5 s 1–7 This field is reserved. Reserved. C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 50: Miscellanies Control And Status Register (Cpld_Misccsr)

    Reset CPLD_BOOTOR field descriptions Field Description Boot override. BOOT_OR Boot configuration from CPLD override is disabled Boot configuration from CPLD override is enabled 1–7 This field is reserved. Reserved. C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 51: Boot Configuration Register 1 (Cpld_Bootcfg1)

    Chapter 7 CPLD Specification 7.2.13 Boot Configuration Register 1 (CPLD_BOOTCFG1) NOTE For more information on BOOTCFG1 register, refer to C29x datasheet. Address: 0h base + 18h offset = 18h Read cfg_core_ cfg_sys_ cfg_core_pll[0:2] cfg_sys_pll[0:2] Write speed speed Reset CPLD_BOOTCFG1 field descriptions...

  • Page 52: Boot Configuration Register 3 (Cpld_Bootcfg3)

    Configuration DDR speed. cfg_ddr_ speed[0:1] 5–7 Configuration DDR PLL. cfg_ddr_pll[0:2] 7.2.15 Boot Configuration Register 3 (CPLD_BOOTCFG3) NOTE For more information on BOOTCFG3 register, refer to C29x datasheet. Address: 0h base + 1Ah offset = 1Ah Read cfg_cpu_ cfg_svr[0:1] cfg_sb_dis cfg_rom_loc[0:3]...

  • Page 53: Boot Configuration Register 4 (Cpld_Bootcfg4)

    Chapter 7 CPLD Specification 7.2.16 Boot Configuration Register 4 (CPLD_BOOTCFG4) NOTE For more information on BOOTCFG4 register, refer to C29x datasheet. Address: 0h base + 1Bh offset = 1Bh Read Reserved cfg_eng_use[0:1] cfg_gpinput[0:3] Write Reset CPLD_BOOTCFG4 field descriptions Field Description 0–1...
  • Page 54 CPLD Memory Map/Register Definition C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 55: Programming U-Boot

    2. Connect 110V/220 power to power adapter. 3. Connect RJ45 console line to UART port. 4. Connect network cable into Ethernet port. 5. Connect USB TAP to JTAG port on C29x PCIe. 6. Open the CodeWarrior IDE for Power Architecture, and select P1010 processor with P1010RDB_core_init.tcl 7.
  • Page 56 Programming U-Boot on a Board having no U-Boot Installed C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 57 # bit 8 - 23 - BASE_ADDR mem [CCSR 0x0] = 0x000ff700 set CCSRBAR 0xff700000 ###################################################################### # invalidate BR0 # CSPR0 mem [CCSR 0x1E010] = 0x00000100 # ABIST off # L2ERRDIS[MBECCDIS]=1 L2ERRDIR[SBECCDIS]=1 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 58 [CCSR 0xCE8] = 0x00000000 mem [CCSR 0xCF0] = 0x00000000 #disable LAW 8 mem [CCSR 0xD08] = 0x00000000 mem [CCSR 0xD10] = 0x00000000 #disable LAW 9 mem [CCSR 0xD28] = 0x00000000 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 59 [CCSR 0x2110] = 0xC70C0000 #wait for DRAM data initialization wait 500 #SPI init # SPMODE mem [CCSR 0x7000] = 0x80000403 # SPIM - catch all events mem [CCSR 0x7008] = 0x00000000 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 60 # put a valid opcode at debug and progrm exception vector address mem v:0x00000700 = 0x48000000 mem v:0x00001500 = 0x48000000 ############################################################################## apply_e500v2_workaround # enable floating point reg ${SSPR}MSR = 0x02001200 ############ # time base enable & MAS7 update C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 61 {} { # Environment Setup #radix x config hexprefix 0x config MemIdentifier v config MemWidth 32 config MemAccess 32 config MemSwap off #------------------------------------------------------------------------------- # Main #------------------------------------------------------------------------------- envsetup init_P1010 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 62 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.

  • Page 63: Revision History

    Appendix B Revision History The table below provides revision history of this document. Table B-1. Document revision history Revision number Date Change description Rev. 0 10/2013 Initial public release C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 64 C29x PCIe Card User Guide, Rev. 0, 10/2013 Freescale Semiconductor, Inc.
  • Page 65 Freescale, the Freescale logo, and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related...

Table of Contents