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SST SST65P542R User Manual

Remote controller
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Programming User's Manual

Remote Controller

SST65P542R
©2003 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S74004-00-000
4/03
SoftPartition is a trademark of Silicon Storage Technology, Inc.
1
These specifications are subject to change without notice.

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  • Page 1: Remote Controller

    Programming User’s Manual Remote Controller SST65P542R ©2003 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S74004-00-000 4/03 SoftPartition is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.

  • Page 2: Table Of Contents

    9.2 IDLE Mode ............... 24 ©2003 Silicon Storage Technology, Inc.
  • Page 3 13.0 PACKAGING DIAGRAMS ............. . 39 ©2003 Silicon Storage Technology, Inc.

  • Page 4: Introduction

    SST65P542R Programming Reference Manual 1.0 INTRODUCTION The SST65P542R is a member of SST’s 8-bit, application-specific microcontroller family targeting IR remote con- troller applications. The SST65P542R microcontroller provides high-functionality to infrared remote controller products. The device offers flexibility to store different remote control configurations for controlling multiple appliances. The configura- tions are either programmed at the factory during the manufacturing process or updated through a web download procedure using the serial interface.

  • Page 5: Block Diagram

    Interrupt IRQ# Control MCU Core SuperFlash EEPROM 352K x8 16K x8 Port A Carrier Modulator Transmitter Port B Port C Timer/Counter Interrupt Real-Time Counter Core Timer / Counter COP Watchdog Timer 4004 B2.5 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 6: Pin Assignments

    Interrupt Request: The IRQ# is negative edge-sensitive triggered. An internal Schmitt trigger is included in the IRQ# pin to improve noise immunity. Power Supply: Supply Voltage Ground: Circuit ground. (0V reference) T3-1.5 4004 1. I = Input O = Output ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 7: Memory Organization

    4.0 MEMORY ORGANIZATION The SST65P542R has a total of 64 KByte of addressable memory. A memory map is shown in Figure 4-1. The memory consists of 32 Bytes of I/O registers, 352 Bytes of SRAM, 16 KByte of user flash memory, and 128 Bytes of user vectors.

  • Page 8: Mcu Core And Instruction Set

    PROGRAM COUNTER 0 0 0 0 0 0 0 0 STACK POINTER ACCUMULATOR INDEX REGISTER PSW REGISTER Unused Unused Unused Half Carry Interrupt Disable Negative Zero Carry 4004 F01.4 FIGURE 5-1: P ROGRAMMING ODEL ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 9: Accumulator (A)

    256 (decimal) locations. If 64 locations are exceeded, i.e. if stack pointer is pointing to 00C0H and stacking operation carried out, the stack pointer wraps around to 00FFH and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 10: Processor Status Word (Psw)

    These instructions are one byte long. 5.2.2 Immediate (IMM) In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. EA = PC+1; PC PC+2 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 11: Direct (Dir)

    EA = (X)+[(PC+1):(PC+2)]; PC PC+3 Address bus high byte (PC+1)+K; Address bus low byte (X)+(PC+2) where K = the carry from the addition of (X) and (PC+2) ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 12: Relative (Rel)

    EA1 = (PC+1); PC PC+2 Address bus high byte 0; Address bus low byte (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 13: Instruction Set

    Branch on H = 0 BHCS Branch if half carry set – – – – – Branch on H = 1 Branch if higher – – – – – Branch if accumulator is higher than memory (unsigned) ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 14 – – – – – Clear carry flag – – – – 0 Clear interrupt mask – 0 – – – bit 0 Clear INH (A) – – 0 1 – INH (X) ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 15 Jump to new location – – – – – (PC + 1) (PC + 2) Jump to new location – – – – – saving return address PC + 2 (PC + 1) (PC + 2) ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 16 Rotate one bit right INH (A) – – N Z C through carry (memory INH (X) or accumulator) Reset stack pointer – – – – – Return from interrupt PC; P ? ? ? ? ? ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 17 – – – – – to index X Test for negative or INH (A) – – N Z – zero INH (X) Transfer index X to – – – – – accumulator T5-1.5 4004 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 18 OR function & AND function Exclusive OR function load PSW from stack not affected Machine cycle is two oscillator clock cycles. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 19: I/O Registers Definition

    Serial Interface Data Register (SIDAT) 001BH Serial Interface Status Register (SISTA) 001CH Serial Interface Baud-Rate Register (SIBDR) 001DH Serial Interface Control Register (SICON_AP) 001EH Serial Interface Control Register (SICON_ENSI) 001FH IR Input Control Register T6-1.3 4004 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 20 Register 2(MDR2) 0017H Modulator Data Register 3(MDR3) 0018H Power Saving STOP Control Register (PSCR) 0019H Serial Interface Control Register X = Reserved (Recommended to write “0” to reserved bits for future compatibility) T6-2.5 4004 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 21 X = Reserved (Recommended to write “0” to reserved bits for future compatibility) T6-2.5 4004 Please see Section 10.0 for Core Timer and Section 11.0 for CMT register definitions. All other register definitions are described in detail in the SST65P542R data sheet. ©2003 Silicon Storage Technology, Inc. S74004-00-000...

  • Page 22: Interrupts

    If interrupt is recognized, before the Program counter jumps to one of the address vectors, the Program Counter, Index Register, Accumulator, and the Process Status Word Register are pushed on to the stack (see Figure 5-2). ©2003 Silicon Storage Technology, Inc. S74004-00-000...

  • Page 23: Resets And Clocks

    Programming Reference Manual 8.0 RESETS AND CLOCKS SST65P542R has two sources for external reset: LPRST# and RESET#. After LPRSET# switches from low to high, 4064 clock cycles are counted before the reset vector address appears on the internal address bus. RESET# immediately resets the MCU without counting the 4064 clock cycles.

  • Page 24: Power-Down Modes

    SST65P542R Programming Reference Manual 9.0 POWER-DOWN MODES SST65P542R offers two modes to reduce system power consumption. 9.1 STOP Mode To enter the STOP Mode, write 01H to the Power Saving Control Register (PSCR - 0018H). Upon completion of the Write operation to the PSCR, the internal oscillator is turned off, halting all internal processing, including CMT and timer operations.

  • Page 25: The Core Timer

    Status Register 0008h COP Watchdog Timer (÷8) Interrupt Circuit To Reset To Interrupt Logic Logic 4004 F12.5 Note: 1. Internal Peripheral Clock is oscillator clock divided by two. FIGURE 10-1: C IMER LOCK IAGRAM ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 26: Computer Operating Properly Watchdog Timer Control Register (Cwtc)

    10.2.6 Real-Time Interrupt Flag Clear (RTFC) RTIF is cleared when RTFC bit is written to as “1”. Writing a “0” to RTFC has no effect on RTIF. RTFC has “0” as default. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 27: Real-Time Interrupt Rate Select (Rt1-Rt0)

    10.5 Timer During IDLE Mode The MCU clock is stopped during IDLE mode, but the timer remains active. If interrupts are enabled, a timer inter- rupt will cause the processor to exit IDLE mode. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 28: Carrier Modulator Transmitter (Cmt)

    FSK protocols without MCU intervention. When the BASE bit in the modulator control and status register (MCSR) is set, the carrier output to the modulator is held high continuously to allow for the gen- eration of baseband protocols. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 29: Time Counter

    In the general case, the carrier generator output frequency is: ÷ (Highcount + Lowcount) Hz where: 0< Highcount < 64 and 0< Lowcount < 64 The duty cycle of the carrier signal is: Highcount Duty cycle ---------------------------------------------------------- - Highcount Lowcount ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 30: Carrier Generator Data Registers (Chr1, Clr1, Chr2, And Clr2)

    These bits contain the number of input clocks for the carrier high and low time periods. When operating in time mode, this register pair is never selected. When operating in FSK mode, the modulator alternately selects this register pair and the primary register pair. The secondary carrier high and low ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 31: Modulator

    (BASE bit in MCSR is set to 1), the modulator output will be force to 1 for the duration of the mark period and force to 0 for the duration of a space period. ©2003 Silicon Storage Technology, Inc. S74004-00-000...

  • Page 32: Fsk Mode

    Here are equations to calculate mark and space period for FSK mode: MBUFF ------------------------------- sec Tmark SBUFF -------------------- - sec Tspace Where f is the frequency output from the carrier generator. Setting the DIV2 bit in the MCSR will double mark and space times. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 33: Extended Space Operation

    SBUFF, i.e., the end of the modulator cycle. This flag is cleared by a read of the MCSR follow by an access of MDR2 or MDR3. The EOC flag is cleared by reset. 0: Current modulation cycle in progress 1: End of modulator cycle ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 34 When this is set to 0, the current modulator cycle will be allowed to be completed and the modulator output will be forced to low. This bit is cleared by reset. 0: Modulator and carrier generator disabled 1: Modulator and carrier generator enabled ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 35: Modulator Period Data Register (Mdr1, Mdr2, And Mdr3)

    Pending or new CMT interrupt will bring the chip out of idle mode. 11.2.5.3 Stop Mode Operation During stop mode, the CMT halts all operation and no registers are affected. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 36: Programming Flow Diagram

    MCU halt for Erase complete done done Next instruction Next instruction *After Chip-Erase all flash memory contents will be erased. MCU should execute Chip-Erase program in SRAM only. 4004 F17.3 FIGURE 12-2: I PPLICATION RASE ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 37 Wait for end of Program (T BP , RY/BY#) Program Completed 4004 F13.4 FIGURE 12-3: E XTERNAL LASH ROGRAM LGORITHM FOR XTERNAL LASH ROGRAMMING Note: Please refer to the SST65P542R data sheet for more information. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...
  • Page 38 (T SE, RY/BY#) Chip erased Sector erased to FFFFH to FFFFH 4004 F15.3 FIGURE 12-4: C ECTOR RASE OMMAND EQUENCE FOR XTERNAL LASH ROGRAMMING Note: Please refer to the SST65P542R data sheet for more information. ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

  • Page 39: Packaging Diagrams

    4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. (SOIC) MALL UTLINE NTEGRATED IRCUIT SST P : SG ACKAGE Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03...

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