Related Manuals for AMD HYPERTRANSPORT 8151
Summary of Contents for AMD HYPERTRANSPORT 8151
- Page 1 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision Publication # Issue Date: Guide 25912 Revision: 3.06 March 2006...
- Page 2 Trademarks AMD, the AMD Arrow logo, and combinations thereof, and AMD-8151 are trademarks of Advanced Micro Devices, Inc. PCI-X and PCI Express are registered trademarks of PCI-SIG. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
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Page 3: Revision History
25912 Rev. 3.06 March 2006 Revision History Date Revision March 2006 3.06 August 2004 3.04 June 2003 3.00 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Description Added erratum #28. Added erratum #27. Initial public release. Revision History Revision Guide... - Page 4 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel 25912 Rev. 3.06 March 2006 Revision Guide Revision History...
- Page 5 Graphics Tunnel Revision Guide The purpose of the AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision Guide is to communicate updated product information on the AMD-8151™ HyperTransport™ AGP3.0 graphics tunnel to designers of computer systems and software developers. This guide consists of three major sections: •...
- Page 6 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision Guide Revision Determination The BIOS checks the PCI revision ID register at DevA:0x08 to determine the version of silicon as shown in Table 1. Table 1. AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision IDs Sequence Revision DevA:0x08 DevB:0x08 Revision Determination 25912 Rev.
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Page 7: Product Errata
25912 Rev. 3.06 March 2006 Product Errata This section documents AMD-8151™ HyperTransport™ AGP3.0 graphics tunnel product errata. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. - Page 8 DevA:0xA4[Host translation#] is a read-only bit, fixed in the high state in the graphics tunnel. Per the AGP specification, this indicates that core logic does not translate host transactions addressed to the Graphics Aperature through the GART. However, on AMD platforms that use the graphics tunnel, such host transactions can be translated through the GART.
- Page 9 The A-side link should be configured to operate at 600 MHz instead of 800 MHz. Alternatively, more restrictive system board layout rules for the A-side link may be employed. See the AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Motherboard Design Guide, order# 25617 for details.
- Page 10 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel 25912 Rev. 3.06 March 2006 Revision Guide 24 Deadlock Scenario With Peer-To-Peer Traffic Description Some PCI cards generate peer-to-peer posted-write traffic targeting the AGP bridge (from the PCI bus, through the graphics tunnel, to the host, back to the graphics tunnel to the AGP bus). The combination of such cards and some AGP cards can generate traffic patterns that result in a system deadlock.
- Page 11 25912 Rev. 3.06 March 2006 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision Guide 25 Input Leakage Parameter Out Of Spec Description When operating with AGP2.0 signaling, the input leakage current (I ) is specified to be limited to less than ±10 µA. However, input leakage current may be as much as ±20 µA in some graphics tunnel parts.
- Page 12 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel 25912 Rev. 3.06 March 2006 Revision Guide 26 DevB:0x00[DevID] Is Read Only Description The four LSBs of DevB:0x00[DevID] should be "write once". However, they are "read only" instead. Potential Effect on System A generic graphics driver may be loaded even if the platform does not support the generic driver.
- Page 13 25912 Rev. 3.06 March 2006 27 Failure When B-Side Link Is Directed Toward The Host Description The AMD-8151 does not master abort a transaction with the HyperTransport COMPAT bit set if all of the following conditions apply: • HyperTransport link B is connected toward the host •...
- Page 14 Mode 2 or PCI Express capable device and is not required to support the MMIO BAR. However, using a device with an MMIO BAR and an AMD-8151 on the same HyperTransport™ link of the processor may cause firmware/software problems. Suggested Workaround...
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Page 15: Documentation Support
AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Data Sheet, order# 24888 • HyperTransport™ I/O Link Specification (www.hypertransport.org) See the AMD Web site at www.amd.com for the latest updates to documents. For documents subject to a non-disclosure agreement, please contact your local sales representative. AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel... - Page 16 AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel 25912 Rev. 3.06 March 2006 Revision Guide Documentation Support...