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2-2-4. EMI ESD Filter (F500)
This system uses the EMI ESD filter (F500) to protect the device from noises from IF CONNECTOR part.
2-2-5. IF connetor (IFC500)
It has 20-pin. They are designed to allocate not only 'power and data lines'(VBAT, V_EXT_CHARGE, USB_D+, +VBUS,
USB_D-, TXD1, RXD1, AUX_ON, EXT1, EXT2 and GND) but also Earphone lines(EAMMIC_P/N, EARSPK_R/L,
EAR_SWITCH, EARSPK_COM and EAR_ADC). They connected to power supply IC, microprocessor, signal processor IC
and Earphone.
2-2-6. Battery Charge Management
D820 has a complete constant-current/constant-voltage linear charger for single cell lithium-ion batteries inside.
If Travel Adapter is connected, "V_EXT_CHARGE" begins to provide the charger IC (to battery) with power (current).
When the charging operation is done, "END_OF_CHG" informs it to PCF5213EL1 to stop the operation. "CHG_ON"
signal enables the charger IC to operate in adequate circumstances.
2-2-7. Audio - Part
D820 has several audio-outputs such as stereo speaker, receiver, earphone, etc. HFR P/N signals from CPU are connected
to the receiver. MIC_CP/N are connected to the main MIC and MIC_CP2/N2 as well.
SAPA1D2 is a Class-D amplifier for outputting sounds that are used by mobile phones including MP3 playback, melodies,
voice output on speaker phone mode and so on..
STG3699(U515) is an analog switch to connect SAPA1D2 input port to main DSP or CODEC Chip.
2-2-8. Memory (UME307)
D820 has KBH10PD00M-D414 as a memory module.
The KBH10PD00M-D414 is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR
Flash Memory and 1Gbit OneNAND Flash and 256Mbit Synchronous Burst UtRAM.
It has 16 bit data line, HD[0~15] which is connected to PCF5213 and CL8522S5(Multi-media chip), also has 24 bit
address lines, HA[1~24]. There are 3 chip select signals, CS0n_FLASH, CS1n_RAM, and CS4n_NAND.
In the writing process, WEn is fallen to low and it enables writing process to operate. During reading process,
OEn is fallen to low and it enables reading process to operate. Each chip select signals in the PCF5213EL1 choose
different types of memory.
2-2-9. PCF5213EL1 (UCP200)
The PCF5213EL1 is mainly composed of embeded DSP and ARM core. The DSP subsystem includes the Saturn
DSP core with embedded RAM and ROM, and a set of peripherals. It has 24k×16 bits PRAM, 104k×16 bits,
32k×16 XYRAM and 63k×16 XYROM in the DSP.
The ARM946E-S consists of an ARM9E-S processor core, 8 kbyte instruction cache and 8 kbyte data cache,
tightly-coupled ITCM (Instruction Tightly Coupled Memory) and DTCM (Data Tightly Coupled Memory) memories, a
memory protection unit, and an AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance
Bus) bus interface with a write buffer. HD(0:15), data lines and HA(0:23), address lines are connected to
KBH10PD00M-D414(memory) and CL8522S5(Multi-media chip)
. It has 64 kbyte SC RAM (0.5 Mbit) and 32 kbyte SC program ROM for bootstrap loader in the ARM core.
SAMSUNG Proprietary-Contents may change without notice
This Document can not be used without Samsung's authorization
2-3
Circuit Description
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