Oki MSM85C154HVS User Manual
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Oki MSM85C154HVS User Manual

Oki MSM85C154HVS User Manual

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MSM80C154S
MSM83C154S
MSM85C154HVS
USER'S MANUAL

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  • Page 1 MSM80C154S MSM83C154S MSM85C154HVS USER'S MANUAL...
  • Page 2 Copyright 1988, OKI ELECTRIC INDUSTRY COMPANY, LTD. OKI makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

  • Page 3: Table Of Contents

    2.2 MSM80C154S/MSM83C154S Pin Layout ............12 2.2.1 MSM80C154S/MSM83C154S external dimensions ........15 2.2.2 MSM85C154HVS pin layout and external dimensions ......17 2.3 MSM80C154S Block Diagram ................18 2.4 MSM83C154S Block Diagram ................19 2.5 MSM85C154HVS Block Diagram ..............20 2.6 Timing and Control ................... 21 2.6.1...
  • Page 4 3. CONTROL 3.1 Oscillators [XTAL1 .2] ..................43 3.2 CPU Resetting ....................45 3.2.1 Outline .......................45 3.2.2 Reset Schmitt trigger circuit ...............50 3.2.3 CPU internal status by reset ..............51 3.3 EA(CPU Memory Separate) ................52 3.3.1 Outline .......................52 (1) Internal ROM mode ................52 (2) External ROM mode ................
  • Page 5 4.5.2.5.7 Caution about use of timer counters 0 and 1 ........90 4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power down mode................91 4.5.3 Timer/counter 2 ..................92 4.5.3.1 Outline ....................92 4.5.3.2 Timer 2 control register (T2CON) ............92 4.5.3.3 Timer/counter 2 operation modes ............93 4.5.3.3.1 16-bit auto reload mode ..............
  • Page 6 4.6.4.2 Multi-processor systems ..............128 4.7 Interrupt ......................129 4.7.1 Outline .....................129 4.7.2 Interrupt enable register (IE) ..............131 4.7.3 Interrupt priority register (IP) ..............132 4.7.3.1 Priority interrupt routine flow ..............133 4.7.3.2 Interrupt routine flow when priority circuit is stopped ......134 4.7.3.3 Interrupt priority when priority register (IP) contents are all “0”...
  • Page 7 5.7 High Impedance Input Port Setting of Each Quasi-bidirectional Port 1, 2, and 3 ....................207 5.8 100 kW Pull-Up Resistance Setting for Quasi-bidirectional Input Ports 1, 2, and 3 .....................207 5.9 Precautions When Driving External Transistors by Quasi-bidirectional Port Output Signals ..................208 5.10 Port Output Timing ..................210 1) One machine cycle instruction output timing ..........

  • Page 8: Introduction

    1. INTRODUCTION...
  • Page 9 MSM80C154S/83C154S/85C154HVS...

  • Page 10: Msm80C154S/Msm83C154S/Msm85C154Hvs Outline

    Apart from being without the internal program memory (ROM), MSM80C154S is identical to MSM83C154S. And the difference between MSM85C154HVS and MSM83C154S is that the internal program memory (ROM) in MSM83C154S is replaced by an external ROM connected to MSM85C154HVS by using a piggy-back package.
  • Page 11 CPUs. With this great line-up of functions and with EASE80C51mkII capable of developing programs in a very short time, MSM80C154S/MSM83C154S/MSM85C154HVS give a highly integrated high performance solution.

  • Page 12: Msm80C154S/Msm83C154S Features

    INTRODUCTION 1.2 MSM80C154S/MSM83C154S Features • Full static circuitry • Internal program memory (ROM) 16384 words 8 bits (MSM83C154S) • External program memory (ROM) Connectable up to 64K bytes • Internal data memory (RAM) 256 words 8 bits • External data memory (RAM) Connectable up to 64K bytes •...
  • Page 13 MSM80C154S/83C154S/85C154HVS • Timer/counters (three 16-bit timer/counters) (1) 8-bit timer with 5-bit prescalar (2) 16-bit timer (3) 8-bit timer with 8-bit auto-reloader (4) 8-bit separate timer (5) 16-bit timer with 16-bit auto-reloader (6) 16-bit capture timer (7) 16-bit baud rate generator timer (8) 32-bit timer •...

  • Page 14: Additional Features In Msm80C154S/Msm83C154S/Msm85C154Hvs

    1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS In addition to the basic operations of MSM80C31F/MSM80C51F, the MSM80C154S/ MSM83C154S/MSM85C154HVS devices also include the following functions. • ROM capacity increased from 4K bytes to 16K bytes • RAM capacity increased from 128 bytes to 256 bytes •...
  • Page 15 MSM80C154S/83C154S/85C154HVS...

  • Page 16: System Configuration

    2. SYSTEM CONFIGURATION...
  • Page 17 MSM80C154S/83C154S/85C154HVS...

  • Page 18: Msm80C154S/Msm83C154S/Msm85C154Hvs Logic Symbols

    SYSTEM CONFIGURATION 2. SYSTEM CONFIGURATION 2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols XTAL1 P0.0 P0.1 P0.2 P0.3 PORT 0 (BUS PORT) XTAL2 P0.4 P0.5 P0.6 P0.7 RESET RESET P1.0 P1.1 T2EX P1.2 P1.3 PORT 1 P1.4 ADDRESS LATCH P1.5 ENABLE P1.6 PSEN PROGRAM STORE P1.7...

  • Page 19: Msm80C154S/Msm83C154S Pin Layout

    MSM80C154S/83C154S/85C154HVS 2.2 MSM80C154S/MSM83C154S pin layouts MSM80C154SRS/MSM83C154SRS (Top View) 40 Pin Plastic DIP P1.0/T2 40 V P1.1/T2EX 39 P0.0 P1.2 38 P0.1 P1.3 37 P0.2 P1.4 36 P0.3 P1.5 35 P0.4 P1.6 34 P0.5 P1.7 33 P0.6 RESET 32 P0.7 31 EA P3.0/RXD P3.1/TXD 30 ALE...
  • Page 20 SYSTEM CONFIGURATION MSM80C154SJS/MSM83C154SJS (Top View) 44 Pin Plastic QFJ 6 5 4 3 2 1 44 43 42 41 40 P1.5 39 P0.4 P1.6 38 P0.5 P1.7 37 P0.6 RESET 36 P0.7 35 EA P3.0/RXD 34 NC P3.1/TXD 33 ALE 32 PSEN P3.2/INT0 P3.3/INT1...
  • Page 21 Applicable Packages MSM80C154S RS 40-Pin Plastic DIP (DIP40-P-600-2.54) MSM83C154S-XXX RS MSM80C154S JS 44-Pin Plastic QFJ (QFJ44-P-S650-1.27) MSM83C154S-XXX JS MSM80C154S GS-2K 44-Pin Plastic QFP (DFP44-P-910-0.80-2K) MSM83C154S-XXX GS-2K MSM80C154S TS-K 44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K) MSM83C154S-XXX TS-K 40-Pin Ceramic Piggy Back (ADIP40-C-600-2.54) MSM85C154HVS...

  • Page 22: Msm80C154S/Msm83C154S External Dimensions

    SYSTEM CONFIGURATION 2.2.1 MSM80C154S/MSM83C154S external dimensions MSM80C154SRS/MSM83C154SRS 40-pin Plastic DIP (DIP40-P-600-2.54) MSM80C154SGS/MSM83C154SGS 44-Pin Plastic QFP (QFP44-P-910-0.80-2K) MSM80C154SJS/MSM83C154SJS 44-Pin Plastic QFJ (QFJ44-P-S650-1.27) Figure 2-3 MSM80C154S/MSM83C154S external dimensions...
  • Page 23 MSM80C154S/83C154S/85C154HVS MSM80C154STS/MSM83C154STS 44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K)

  • Page 24: Msm85C154Hvs Pin Layout And External Dimensions

    M85C154H 2764/27128 JAPAN XXXX Pin 1 for 2764, 27128 * The MSM85C154HVS pin layout of bottom side is the same as the pin layout for MSM83C154SRS. * The 27C64/128 device should be used for EPROM. 40-Pin Ceramic Piggy Back (ADIP40-C-600-2.54)

  • Page 25: Msm80C154S Block Diagram

    P2.0 P2.7 CONTROL SIGNAL SIGNAL P0.0 SPECIAL FUNCTION REGISTER P0.7 ADDRESS DECODER XTAL1 PCHL PCLL XTAL2 PSEN C-ROM RESET R/W AMP T2CON TIMER/ P1.0 COUNTER 2 256WORD RCAP RCAP RAMDP 8bit P1.7 P3.0 SBUF SBUF TMOD TCON SCON P3.7 INTERRUPT TIMER/COUNTER 0&1 SERIAL IO...

  • Page 26: Msm83C154S Block Diagram

    P2.0 P2.7 CONTROL SIGNAL SIGNAL P0.0 SPECIAL FUNCTION 16KWORD REGISTER P0.7 8bit ADDRESS DECODER XTAL1 PCHL PCLL XTAL2 SENSE AMP PSEN C-ROM RESET R/W AMP T2CON TIMER/ P1.0 COUNTER 2 256WORD RCAP RCAP RAMDP 8bit P1.7 P3.0 SBUF SBUF TMOD TCON SCON P3.7...

  • Page 27: Msm85C154Hvs Block Diagram

    P2.0 SOCKET P2.7 CONTROL SIGNAL SIGNAL EXTERNAL P0.0 SPECIAL FUNCTION REGISTER P0.7 ADDRESS 16KWORD DECODER XTAL1 8bit PCHL PCLL XTAL2 D0 ... D7 PSEN C-ROM RESET R/W AMP T2CON TIMER/ P1.0 COUNTER 2 256WORD RCAP RCAP RAMDP 8bit P1.7 P3.0 SBUF SBUF TMOD...

  • Page 28: Timing And Control

    SYSTEM CONFIGURATION 2.6 Timing and Control 2.6.1 Outline of MSM80C154S/MSM83C154S timing The MSM80C154S/MSM83C154S devices are both equipped with a built-in oscillation inverter (see Figure 2-8) for use in the generation of clock pulses by external crystal or ceramic resonator. These clock pulses are passed to the timing counter and control circuits where the basic timing and control signals required for internal control purposes are generated.
  • Page 29 MSM80C154S/83C154S/85C154HVS Figure 2-9 MSM80C154S/MSM83C154S fundamental timing...

  • Page 30: Major Synchronizing Signals

    SYSTEM CONFIGURATION 2.6.2 Major synchronizing signals (1) ALE (Address Latch Enable) The ALE signal is used as a clock signal where the address signals 0 thru 7 output from CPU port 0 can be latched externally when external program or external data memory (RAM) is used.

  • Page 31: Msm80C154S Fundamental Operation Time Charts

    MSM80C154S/83C154S/85C154HVS 2.6.3 MSM80C154S fundamental operation time charts (1) External program memory read cycle timing chart M1 or M2 XTAL1 PSEN INST IN INST IN INST IN INST IN INST IN PORT–0 PCH OUT PCH OUT PCH OUT PCH OUT PCH OUT PORT–2 Figure 2-10 MSM80C154S external program memory read cycle timing chart (2) MOVX A, @Rr...

  • Page 32: Movx @Rr, A

    SYSTEM CONFIGURATION (3) MOVX @Rr, A XTAL1 PSEN INST IN INST IN PORT–0 ACC DATA OUT PCH OUT PCH OUT PORT 2 LATCH DATA OUT PCH OUT PORT–2 Figure 2-12 MSM80C154S MOVX @Rr, A execution (4) MOVX A, @DPTR XTAL1 PSEN INST IN RAM DATA IN...

  • Page 33: Movx @Dptr, A

    MSM80C154S/83C154S/85C154HVS (5) MOVX @DPTR, A XTAL1 PSEN INST IN INST IN PORT–0 ACC DATA OUT PCH OUT PCH OUT DPH OUT PCH OUT PORT–2 Figure 2-14 MSM80C154S MOVX @DPTR, A execution (6) MOV direct, PORT [0, 1, 2, 3] execution XTAL1 PSEN PORT 0,1,2,3...

  • Page 34: Msm83C154S Fundamental Operation Time Charts

    SYSTEM CONFIGURATION 2.6.4 MSM83C154S fundamental operation time charts (1) MOVX A, @Rr XTAL1 PSEN RAM DATA IN FLOATING EXT RAM PORT–0 PORT 0 LATCH DATA DATA PORT 2 LATCH DATA OUT PORT–2 Figure 2-16 MSM83C154S MOVX A, @Rr execution (2) MOVX @Rr, A XTAL1 PSEN FLOATING...

  • Page 35: Movx A, @Dptr

    MSM80C154S/83C154S/85C154HVS (3) MOVX A, @DPTR XTAL1 PSEN RAM DATA IN FLOATING EXT RAM PORT–0 PORT 0 LATCH DATA DATA PORT 2 LATCH PORT 2 LATCH DATA OUT DPH OUT PORT–2 DATA OUT Figure 2-18 MSM83C154S MOVX A, @DPTR execution (4) MOVX @DPTR, A XTAL1 PSEN FLOATING...

  • Page 36: Mov Direct, Port[0, 1, 2, 3] Execution

    SYSTEM CONFIGURATION (5) MOV direct, PORT [0, 1, 2, 3] execution XTAL1 PSEN PORT 0,1,2,3 PIN DATA PIN DATA STABLE CPU DATA SAMPLED Figure 2-20 MSM83C154S MOV direct, PORT[0, 1, 2, 3] execution...

  • Page 37: Instruction Register (Ir) And Instruction Decoder (Pla)

    MSM80C154S/83C154S/85C154HVS 2.7 Instruction Register (IR) and Instruction Decoder (PLA) MSM80C154S/MSM83C154S operations are based on an instruction code address method. Hence, in addition to the instruction code instruction register (IR) and instruction decoder (PLA), these devices also include an instruction register (AIR) and register manipulation decoder (PLA) for data addresses and bit addresses.

  • Page 38: Arithmetic Operation Section

    SYSTEM CONFIGURATION 2.8 Arithmetic Operation Section (1) Outline The MSM80C154S/MSM83C154S arithmetic operation section consists of (1) an arithmetic operation instruction decoder, and (2) an arithmetic and logic unit [ALU]. (2) Arithmetic operation instruction decoder: Arithmetic operation instructions are passed to the instruction register (IR) and then to the PLA where they are converted into control signals.

  • Page 39: Program Counter

    MSM80C154S/83C154S/85C154HVS 2.9 Program Counter The MSM80C154S/MSM83C154S program counter has a 16-bit configuration PC thru , as shown in Figure 2-23. ENABLE ROM MSM83C154S INTERNAL ROM 16KWORD 8BIT EXTERNAL ROM MODE PC+1 CPU INTERNAL DATA BUS Figure 2-23 MSM80C154S/MSM83C154S program ounter This program counter is a binary up-counter which is incremented by 1 each time one byte of instruction code is fetched.

  • Page 40: Program Memory And External Data Memory

    SYSTEM CONFIGURATION 2.10 Program Memory and External Data Memory 2.10.1 MSM80C154S/MSM83C154S program area and external ROM connections Since MSM80C154S/MSM83C154S are equipped with a 16-bit program counter, these devices can execute programs of up to 64K bytes (including both internal and external programs).
  • Page 41 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 LATCH P2.0 64kW 8BIT P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN OUTPUT ENABLE...

  • Page 42: Procedures And Circuit Connections Used When External Data Memory (Ram) Is Accessed By Data Pointer (Dptr)

    SYSTEM CONFIGURATION 2.10.2 Procedures and circuit connections used when external data memory (RAM) is accessed by data pointer (DPTR) The MSM80C154S/MSM83C154S can be connected to an external 64K word 8-bit data memory (RAM) when accessing the memory by data pointer (DPTR). The data pointer (DPTR) consists of DPL and DPH registers.
  • Page 43 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 LATCH P2.0 64kW 8BIT P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7...
  • Page 44 SYSTEM CONFIGURATION Figure 2-27 DPTR external data memory access timing...

  • Page 45: Procedures And Circuit Connections Used When External Data Memory (Ram) Is Accessed By Registers R0 And R1

    MSM80C154S/83C154S/85C154HVS 2.10.3 Procedures and circuit connections used when external data memory (RAM) is accessed by registers R0 and R1 The MSM80C154S/MSM83C154S can be connected to an external 256 word ¥ 8-bit data memory (RAM) when addressing the memory according to the contents of registers R0 and R1 in the internal data memory (RAM).
  • Page 46 SYSTEM CONFIGURATION MSM74HC373 MSM80C154S/MSM83C154S Figure 2-28 Connection circuit for external data memory addressed by register R0 or R1...
  • Page 47 MSM80C154S/83C154S/85C154HVS Figure 2-29 Register R0/R1 external data memory access timing...

  • Page 48: Control

    3. CONTROL...
  • Page 49 MSM80C154S/83C154S/85C154HVS...

  • Page 50: Oscillators [Xtal1 .2]

    CONTROL 3. CONTROL 3.1 Oscillators: XTAL1 XTAL2 An oscillator is formed by connecting a crystal or ceramic resonator between the XTAL1 and XTAL2 pins of the MSM80C154S/MSM83C154S devices. If an external clock is applied to XTAL1, the input should be at 50% duty and C-MOS level. IDLE MODE CPU CONTROL CLOCK PD &...
  • Page 51 MSM80C154S/83C154S/85C154HVS IDLE MODE CPU CONTROL CLOCK PD & HPD MODE TIMER, S I/O & INTERRUPT XTAL1 XTAL2 MSM80C154S/MSM83C154S * The capacity of the compensating capacitor depends on the ceramic resonator. * The XTAL1·2 frequency depends on V Figure 3-2 Ceramic resonator connection diagram IDLE MODE CPU CONTROL CLOCK PD &...

  • Page 52: Cpu Resetting

    CONTROL 3.2 CPU Resetting 3.2.1 Outline If a reset signal (kept at “1” level for at least 1 sec) is applied to the RESET pin when the correct voltage (in respect to the various specifications) is applied to the MSM80C154S/ MSM83C154S V pin, a reset signal is stored in the CPU even if the XTAL1·2 oscillators have been stopped.
  • Page 53 MSM80C154S/83C154S/85C154HVS Figure 3-5 Reset execution time chart (internal ROM mode)
  • Page 54 CONTROL Figure 3-6 Reset execution time chart (external ROM mode)
  • Page 55 MSM80C154S/83C154S/85C154HVS Figure 3-7 Reset release time chart (internal ROM mode)
  • Page 56 CONTROL Figure 3-8 Reset release time chart (external ROM mode)

  • Page 57: Reset Schmitt Trigger Circuit

    MSM80C154S/83C154S/85C154HVS 3.2.2 Reset Schmitt trigger circuit The Schmitt trigger circuit connected to the RESET pin shown in the MSM80C154S/ MSM- 83C154S reset circuit block diagram in Figure 3-4 operates in the following way when the V power supply voltage is +5V. If the voltage of the reset signal applied to the RESET pin exceeds 3V when the level of that signal is changed from “0”...

  • Page 58: Cpu Internal Status By Reset

    CONTROL 3.2.3 CPU internal status by reset When a reset signal is applied to the CPU with normal voltage applied to the MSM80C154S/ MSM83C154S V power supply pin, ports 0, 1, 2, and 3 are set to “1” (input mode) even if XTAL1·2 oscillation has been stopped.

  • Page 59: Ea(Cpu Memory Separate)

    If the EA pin is connected to V and a “1” reset signal is applied to the RESET pin to reset the CPU, an internal program memory (ROM) is executed from address 0. (MSM83C154S, MSM85C154HVS) (2) External ROM mode If the EA pin is connected to V and a “1”...

  • Page 60: Internal Specifications

    4. INTERNAL SPECIFICATIONS...
  • Page 61 MSM80C154S/83C154S/85C154HVS...

  • Page 62: Internal Data Memory (Ram) And Special Function Registers

    INTERNAL SPECIFICATIONS 4. INTERNAL SPECIFICATIONS 4.1 Internal Data Memory (RAM) and Special Function Registers 4.1.1 Outline MSM80C154S/MSM83C154S operation is based on an instruction code address method where operations are specified in an instruction code (OP) section, and the data memory (RAM) and special function registers (ACC, B, TCON, P0..
  • Page 63 MSM80C154S/83C154S/85C154HVS IOCON 0FFH~0F8H 248 (0F8H) 0F7H~0F0H 240 (0F0H) 0E7H~0E0H 224 (0E0H) 0D7H~0D0H 208 (0D0H) 205 (0CDH) 204 (0CCH) RCAP2H 203 (0CBH) RCAP2L 202 (0CAH) T2CON 0CFH~0C8H 200 (0C8H) 0BFH~0B8H 184 (0B8H) 0B7H~0B0H 176 (0B0H) 0AFH~0A8H 168 (0A8H) 0A7H~0A0H 160 (0A0H) USER DATA RAM SBUF 153 (99H)

  • Page 64: Internal Data Memory (Ram)

    INTERNAL SPECIFICATIONS 4.2 Internal Data Memory (RAM) 4.2.1 Internal data memory (RAM) The storage capacity of the MSM80C154S/MSM83C154S data memory is 256 words ¥ 8 bits. The layout diagram is shown in Figure 4-2. The data memory can be accessed (R/W) in four different ways - direct register designation, indirect register designation, data addressing, and bit addressing.
  • Page 65 MSM80C154S/83C154S/85C154HVS 0FFH USER DATA RAM USER DATA RAM 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48...

  • Page 66: Internal Data Memory Registers R0 Thru R7

    INTERNAL SPECIFICATIONS 4.2.2 Internal data memory registers R0 thru R7 Four banks of registers group exist in the data memory (RAM) between memory addresses 00 thru 1FH. Banks are specified by RS0 and RS1 bit combinations within the program status word (PSW).

  • Page 67: Stack

    MSM80C154S/83C154S/85C154HVS 4.2.3 Stack The stack data save (storage) area is in the internal data memory (RAM), and is specified by stack pointer (SP 81H). Although 07H data is automatically set in the stack pointer when the CPU is reset, any desired data can be set by software to enable the data memory to be used as stack from any address.

  • Page 68: Internal Data Memory (Ram) Operating Procedures

    INTERNAL SPECIFICATIONS 4.3 lnternal Data Memory (RAM) Operating Procedures 4.3.1 Internal data memory indirect addressing Operation of the internal data memory indirect increment instruction is described here as an example. This instruction (INC @Rr) is a 1-byte 1-machine cycle instruction (see Figure 4- 4).

  • Page 69: Internal Data Memory Register R0 Thru R7 Designation

    MSM80C154S/83C154S/85C154HVS 4.3.2 Internal data memory register R0 thru R7 designation Operation of the internal data memory register decrement instruction is described here as an example. This instruction (DEC Rr) is a 1-byte 1-machine cycle instruction (see Figure 4-5). Register R0 thru R7 is specified by r , and r data of instruction code bit 0, 1, and 2.

  • Page 70: Internal Data Memory 1-Bit Data Designation

    INTERNAL SPECIFICATIONS 4.3.3 Internal data memory 1-bit data designation In the MSM80C154S/MSM83C154S, 1-bit data manipulations (test, reset, set, complement, transfer) can be executed directly between internal data memory addresses 20 thru 2FH by bit manipulation instructions. The operation of a bit reset instruction is described below as an example.
  • Page 71 MSM80C154S/83C154S/85C154HVS Table 4-4 Bit designation table Bit name Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 4-5 Addressing combination table RAM address...

  • Page 72: Special Function Registers(Tcon, Scon

    INTERNAL SPECIFICATIONS 4.4 Special Function Registers (TCON, SCON,..ACC, B) 4.4.1 Outline As can be seen from the configuration shown in Table 4-6, the MSM80C154S/ MSM83C154S special function registers consist of 27 8-bit registers. Special function registers can be accessed (R/W) by either data addressing or bit addressing. All 27 registers can be specified by data addressing.
  • Page 73 MSM80C154S/83C154S/85C154HVS Table 4-6 List of special function registers Bit address Register Data address name IOCON 0F8H(248) 0F0H(240) 0E0H(224) 0D0H(208) 0CDH(205) 0CCH(204) RCAP2H 0CBH(203) RCAP2L 0CAH(202) T2CON 0C8H(200) 0B8H(184) 0B0H(176) 0A8H(168) 0A0H(160) SBUF 99H(153) SCON 98H(152) 90H(144) 8DH(141) 8CH(140) 8BH(139) 8AH(138) TMOD 89H(137) TCON...

  • Page 74: Special Function Registers

    INTERNAL SPECIFICATIONS 4.4.2 Special function registers 4.4.2.1 Timer mode register (TMOD) Name Address TMOD GATE GATE Bit location Flag Function TMOD.0 Timer/counter 0 mode setting 8-bit timer/counter with 5-bit prescalar 16-bit timer/counter TMOD.1 8-bit timer/counter with 8-bit auto reloading Timer/counter 0 separated into TL0 (8-bit) timer/counter and TH0 (8-bit) timer/counter.

  • Page 75: Power Control Register (Pcon)

    MSM80C154S/83C154S/85C154HVS 4.4.2.2 Power control register (PCON) Name Address PCON SMOD — Bit location Flag Function PCON.0 IDLE mode set when this bit is set to "1". CPU operations are stopped when IDLE mode is set, but XTAL1·2, timer/counters 0, 1, and 2, the interrupt circuits, and serial port remain active.

  • Page 76: Timer Control Register (Tcon)

    INTERNAL SPECIFICATIONS 4.4.2.3 Timer control register (TCON) Name Address TCON Bit location Flag Function TCON.0 External interrupt 0 signal used in level detect mode when this bit is "0", and in trigger detect mode when "1". TCON.1 Interrupt request flag for external interrupt 0. Bit is reset automatically when interrupt is serviced.

  • Page 77: Serial Port Control Register (Scon)

    MSM80C154S/83C154S/85C154HVS 4.4.2.4 Serial port control register (SCON) Name Address SCON Bit location Flag Function SCON.0 "End of serial port reception" interrupt request flag. This flag must be reset by software during interrupt service routine. This flag is set after the eighth bit of data has been received when in mode 0, or by the STOP bit when in any other mode.

  • Page 78: Interrupt Enable Register (Ie)

    INTERNAL SPECIFICATIONS 4.4.2.5 Interrupt enable register (IE) Name Address 0A8H — Bit location Flag Function IE.0 Interrupt control bit for external interrupt 0. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.1 Interrupt control bit for timer interrupt 0. Interrupt disabled when bit is "0".

  • Page 79: Interrupt Priority Register (Ip)

    MSM80C154S/83C154S/85C154HVS 4.4.2.6 Interrupt priority register (IP) Name Address 0B8H — Bit location Flag Function IP.0 Interrupt priority bit for external interrupt 0. Priority is assigned when bit is "1". IP.1 Interrupt priority bit for timer interrupt 0. Priority is assigned when bit is "1". IP.2 Interrupt priority bit for external interrupt 1 .

  • Page 80: Program Status Word Register (Psw)

    INTERNAL SPECIFICATIONS 4.4.2.7 Program status word register (PSW) Name Address 0D0H Bit location Flag Function PSW.0 Accumulator (ACC) parity indicator. "1" when the "1" bit number in the accumulator is an odd number, and "0" when an even number. PSW.1 User flag which may be set to "0"...

  • Page 81: I/O Control Register (Iocon)

    MSM80C154S/83C154S/85C154HVS 4.4.2.8 I/O control register (IOCON) Name Address IOCON 0F8H — SERR P3HZ P2HZ P1HZ Bit location Flag Function IOCON.0 If CPU power down mode (PD, HPD) is activated with this bit set to "1", the outputs from ports 0, 1, 2, and 3 are switched to floating status.

  • Page 82: Timer 2 Control Register (T2Con)

    INTERNAL SPECIFICATIONS 4.4.2.9 Timer 2 control register (T2CON) Name Address TMOD 0C8H EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 Bit location Flag Function T2CON.0 CP/RL2 Capture mode is set when TCLK+RCLK="0" and CP/RL2 16-bit auto reload mode is set when TCLK+RCLK="0" and CP/RL2="0". CP/RL2 is ignored when TCLK+RCLK="1".

  • Page 83: Timer/Counters 0, 1, And 2

    MSM80C154S/83C154S/85C154HVS 4.5 Timer/Counters 0, 1 and 2 4.5.1 Outline Timer/counters 0, 1 and 2 are all equipped with 16-bit binary up-counting and Read/Write functions, and can be operated independently. All control of timer/counters 0 and 1 is handled by the timer control register (TCON 88H) and the timer mode register (TMOD 89H).
  • Page 84 INTERNAL SPECIFICATIONS Figure 4-7 Overall clock input control circuit for timer/counters 0 and 1...

  • Page 85: Timer/Counter 0 And 1 Count Clock Designation

    MSM80C154S/83C154S/85C154HVS 4.5.2.3 Timer/counter 0 and 1 count clock designation Designation of count clock inputs to timer/counters 0 and 1 is controlled by bit 2 and 6, C/T, in the timer mode register (TMOD 89H). Timer/counter 0 is controlled by bit 2, C/T, and timer/counter 1 is controlled by bit 6, C/T. The internal clock is passed to the timer/counter when the C/T bit is “0”.

  • Page 86: External Clock Detector Circuit For Timer/Counters 0 And 1

    INTERNAL SPECIFICATIONS 4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1 The detector circuit shown in Figure 4-8 is inserted between the timer/counters and the external clock pin. This detector circuit operates in the following way. When the external clock applied to the T0 and T1 pins is changed from “1”...

  • Page 87: Counting Control Of Timer/Counters 0 And 1 By Int Pin

    MSM80C154S/83C154S/85C154HVS M1 or M2 XTAL1 T0 or T1 COUNT IN F/F1Q F/F2Q TIMER COUNT Figure 4-9 Detector circuit operational time chart 4.5.2.4 Counting control of timer/counters 0 and 1 by INT pin In addition to control by TR0 and TR1 bits of timer control register (TCON), timer/counter 0 and 1 counting start and stop can also be controlled by the signal level applied to the external interrupt pin in accordance with the GATE data values of bits 3 and 7 in the timer mode register (TMOD 89H) indicated in Table 4-9.
  • Page 88 INTERNAL SPECIFICATIONS XTAL 1 TIMER 0 TIMER 1 T0 or T1 DETECTOR CLOCK C/ T INT0 or INT1 GATE TR0 or TR1 Figure 4-10 INT0 and INT1 timer/counter start/stop control circuit Table 4-10 GATE·INT·TR timer/counter control tables TIMER 0 TIMER 1 GATE GATE INT0...

  • Page 89: Timer/Counters 0/1 Timer Modes

    MSM80C154S/83C154S/85C154HVS 4.5.2.5 Timer/counters 0/1 timer modes 4.5.2.5.1 Outline The timer/counter 0 and 1 timer modes are set by combinations of M0 and M1 bit data in the timer mode register (TMOD 89H) shown in Table 4-11. The timer modes which can be set are 0, 1, 2, and 3.
  • Page 90 INTERNAL SPECIFICATIONS XTAL 1 DETECTOR Q0------Q4 Q0------Q7 T0 PIN DETECTOR (5BITS) (8BITS) (PORT 3.4) C/ T GATE INT0 PIN DATA (PORT 3.2) LATCH Figure 4-11 Timer/counter 0 mode 0 XTAL 1 DETECTOR Q0------Q4 Q0------Q7 T1 PIN DETECTOR (5BITS) (8BITS) (PORT 3.5) C/ T S I/O CLOCK GATE...

  • Page 91: Mode 1

    MSM80C154S/83C154S/85C154HVS 4.5.2.5.3 Mode 1 In mode 1, timer/counters 0 and 1 both become 16-bit timer/counters by the circuit connection shown in Figures 4-13 and 4-14. TL0 and TL1 in timer/counters 0 and 1 serve as the counter for the eight lower bits, and TH0 and TH1 serve as the counter for the eight upper bits.
  • Page 92 INTERNAL SPECIFICATIONS XTAL 1 DETECTOR Q0------Q7 Q0------Q7 T0 PIN DETECTOR (8BITS) (8BITS) (PORT 3.4) C/ T GATE INT0 PIN DATA (PORT 3.2) LATCH Figure 4-13 Timer/counter 0 model XTAL 1 DETECTOR Q0------Q7 Q0------Q7 T1 PIN DETECTOR (8BITS) (8BITS) (PORT 3.5) C/ T S I/O CLOCK GATE...

  • Page 93: Mode 2

    MSM80C154S/83C154S/85C154HVS 4.5.2.5.4 Mode 2 In mode 2, timer/counters 0 and 1 both become 8-bit timer/counters with 8-bit auto reloader registers by the circuit connection shown in Figures 4-15 and 4-16. TH0 and TH1 in timer/ counters 0 and 1 serve as the 8-bit auto reloader section, and TL0 and TL1 serve as the timer/ counter section.
  • Page 94 INTERNAL SPECIFICATIONS XTAL 1 DETECTOR Q0------Q7 T0 PIN DETECTOR (8BITS) (PORT 3.4) C/ T Q0------Q7 GATE RELOAD DATA (8BITS) INT0 PIN DATA (PORT 3.2) LATCH Figure 4-15 Timer/counter 0 mode 2 S I/O CLOCK XTAL 1 DETECTOR Q0------Q7 T1 PIN DETECTOR (8BITS) (PORT 3.5)

  • Page 95: Mode 3

    MSM80C154S/83C154S/85C154HVS 4.5.2.5.5 Mode 3 In mode 3, timer/counter 0 TL0 and TH0 become independent 8-bit timer/counters by the circuit connection shown in Figure 4-17. Timer/counter 1 does not operate when mode 3 is set. The TL0 8-bit timer/counter is controlled in the same way as the regular timer/counter 0, TF0 being set if a carry signal is generated by TL0.

  • Page 96: 32-Bit Timer Mode

    INTERNAL SPECIFICATIONS 4.5.2.5.6 32-bit timer mode When “1” is set in bit 6 (T32) of the I/O control register (IOCON 0F8H), timer/counters 0 and 1 are connected serially as indicated in Figure 4-18 to become a 32-bit timer/counter. This 32-bit timer/counter is started by the following procedure. First, “0” is set in TR0, TR1, TF0, and TF1 of the timer control register (TCON 88H) to stop the timer/counter and reset the timer flag.

  • Page 97: Caution About Use Of Timer Counters 0 And 1

    MSM80C154S/83C154S/85C154HVS 4.5.2.5.7 Caution about use of timer counters 0 and 1 Since the internal clock stops operation during soft power down mode (PD), the auto-reload operation is not executed if timer/counters 0 and 1 are set to mode 2 or mode 3. If the power down mode is to be cancelled by the timer, timer/counters 0 and 1 must be set to mode 0 or mode 1.

  • Page 98: Caution About Use Of Timer Counters 0 And 1 When Setting Software Power Down Mode

    INTERNAL SPECIFICATIONS 4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power down mode When setting sofware power down mode, if the value of a timer counter by which a timer interrupt is set is immediately before overflow, the software power down mode can not be set. (Example) Timer 0 is in mode 1 of external clock.

  • Page 99: Timer/Counter 2

    MSM80C154S/83C154S/85C154HVS 4.5.3 Timer/counter 2 4.5.3.1 Outline Timer/counter 2 is equipped with 16-bit binary counting and Read/Write functions. This timer/ counter is controlled entirely by timer 2 control register (T2CON 0C8H). The operating modes are 16-bit auto reload mode, capture mode, and baud rate generator mode.

  • Page 100: Timer/Counter 2 Operation Modes

    INTERNAL SPECIFICATIONS EXF2 Timer/counter 2 external flag bit which is set when the T2EX pin level (bit 1 of port 1) is changed from “1” to “0” at EXEN2=1. This flag serves as the timer interrupt 2 request signal. When an interrupt is generated, this flag must be reset to “0”...

  • Page 101: 16-Bit Capture Mode

    MSM80C154S/83C154S/85C154HVS XTAL 1 RCLK=0 TCLK=0 CP/ RL2=0 Q0------Q7 Q0------Q7 C/ T2 8 BIT 8 BIT DETECTOR RCAP2L RCAP2H [PORT 1.0] DETECTOR T2EX TIMER 2 DETECTOR INTERRUPT [PORT 1.1] DETECTOR EXF2 EXEN2 Figure 4-20 Timer/counter 2 16-bit auto reload mode circuit 4.5.3.3.2 16-bit capture mode The 16-bit capture mode is set by making the connections shown in Figure 4-21 with the following timer 2 control register (T2CON) bit conditions, viz.

  • Page 102: 16-Bit Baud Rate Generator Mode

    INTERNAL SPECIFICATIONS XTAL 1 RCLK=0 TCLK=0 CP/ RL2=1 Q0------Q7 Q0------Q7 C/ T2 8 BIT 8 BIT DETECTOR RCAP2L RCAP2H [PORT 1.0] DETECTOR T2EX TIMER 2 DETECTOR INTERRUPT DETECTOR EXF2 [PORT 1.1] EXEN2 Figure 4-21 Timer/counter 2 16-bit capture mode circuit 4.5.3.3.3 16-bit baud rate generator mode The 16-bit baud rate generator mode is set by making the connections shown in Figure 4-22 with the following timer 2 control register (T2CON) bit conditions, viz.
  • Page 103 SMOD[PCON bit 7] *RCLK+TCLK=1 CP/ RL2= TIMER 1 OVERFLOW RX CLOCK [MODE1, 3] XTAL 1 RCLK Q0------Q7 Q0------Q7 C/ T2 8 BIT 8 BIT TX CLOCK [MODE1, 3] DETECTOR RCAP2L RCAP2H [PORT 1.0] TCLK T2EX DETECTOR DETECTOR EXF2 TIMER 2 INTERRUPT [PORT 1.1] EXEN2...

  • Page 104: Timer/Counter 2 Detector Circuit

    INTERNAL SPECIFICATIONS 4.5.3.4 Timer/counter 2 detector circuit 4.5.3.4.1 T2 (timer/counter 2 external clock detector) The T2 detector circuit block diagram is shown in Figure 4-23. Operation of this circuit is outlined below. When the level of the signal applied to T2 (bit 0 of port 1) is changed from “1” to “0”, output of F/Fl becomes “1”.

  • Page 105: Timer/Counter Carry Signal Detector Circuit

    MSM80C154S/83C154S/85C154HVS 4.5.3.5 Timer/counter carry signal detector circuit The detector circuit shown in Figure 4-25 is inserted between the MSM80C154S/ MSM83C154S timer/counter carry output and the timer flag. The purpose of this detector is to prevent timer flags being set by the timer carry signal during execution of OR, AND, EOR, RESET bit, SET bit, or MOV bit instruction on the contents of the timer control register (TCON), and thereby prevent loss of timer flags by manipulated data by the time execution of instruction has been completed.

  • Page 106: Serial Port

    INTERNAL SPECIFICATIONS 4.6 Serial Port 4.6.1 Outline MSM80C154S/MSM83C154S is equipped with a serial port which can be used in I/O extension and UART (Universal Asynchronous Receiver/Transmitter) applications. I/O extension mode • Input and output of 8-bit serial data synchronized with the MSM80C154S/MSM83C154S output clock.
  • Page 107 INTERNAL BUS MULTIPLEXER SBUF (T) TXD (P3.1) TIMER/COUNTER1 SHIFT CLOCK OVERFLOW TIMER/COUNTER2 TX CONTROL OVERFLOW 1/2OSC. (PCON.7) (T2CON.4) (T2CON.5) (IOCON.5) SCON SMOD TCLK RCLK SERR RX CONTROL INPUT SHIFT RXD (P3.0) Note: REGISTER MULTIPLEXER : Internal bus connection : Serial data flow and SBUF (R) shift clock : Control coupling...

  • Page 108: Special Function Registers For Serial Port

    INTERNAL SPECIFICATIONS 4.6.2 Special function registers for serial port 4.6.2.1 SCON (Serial Port Control Register) SCON is an 8-bit special function register consisting of control bits for specifying serial port operation modes and enabling/disabling data reception, storage bits for the ninth data bit transmitted and received during 11-bit frame UART mode, and the serial port status flag.
  • Page 109 MSM80C154S/83C154S/85C154HVS Table 4-15 SCON Symbol Function "End of reception" flag. This is the interrupt request flag set by hardware when reception of one frame has been completed. The interrupt is generated by ORing with the T1 flag. Since the flag cannot be cleared by hardware, it must be cleared by software.

  • Page 110: Sbuf

    INTERNAL SPECIFICATIONS Table 4-16 Serial port operation modes Mode Function Baud rate I/O extension 1/12 F 10-bit frame UART Vareable 11-bit frame UART 1/32 F or 1/64 F 11-bit frame UART Vareable Note: F denotes frequency of fundamental oscillator (XTAL1·2). 4.6.2.2 SBUF (serial port buffer register) SBUF is an 8-bit special function register used to store transmitting and receiving data.

  • Page 111: Smod

    MSM80C154S/83C154S/85C154HVS 4.6.2.5 SMOD SMOD controls the division of the baud rate clock source when the serial port is in UART mode (mode 1, 2, or 3). If SMOD is cleared when in mode 1 or 3, the timer/counter 1 overflow frequency divided by 2 becomes the baud rate clock source.

  • Page 112: Serr

    INTERNAL SPECIFICATIONS 4.6.2.6 SERR SERR is the status flag set when a framing error or overrun error is generated during UART mode (mode 1, 2, or 3). Framing error: The SERR flag is set when no stop bit is detected in UART mode. Framing error is detected irrespective of the data reception conditions set by SM2.

  • Page 113: Operating Modes

    MSM80C154S/83C154S/85C154HVS 4.6.3 Operating modes 4.6.3.1 Mode 0 4.6.3.1.1 Outline Mode 0 is the I/O extension mode where input and output of 8-bit data via RXD (P3.0) is synchronized with the output clock from TXD (P3.1). The baud rate in mode 0 is fixed to 1/12th of the fundamental oscillator (XTAL1·2) frequency to enable the serial port to operate synchronized with the basic MSM80C154S/MSM83C154S timing.
  • Page 114 INTERNAL BUS SHIFT CLOCK WRITE START SBUF TO SBUF ENABLE SERIAL PORT INTERRUPT START INPUT SHIFT REG. SBUF INTERNAL BUS...
  • Page 115 MSM80C154S/83C154S/85C154HVS Figure 4-29 Serial port (mode 0) timing chart...
  • Page 116 INTERNAL SPECIFICATIONS Figure 4-30 Serial port (mode 0) timing and corresponding basic MSM80C154S/ MSM83C154S timing...

  • Page 117: Mode 1

    MSM80C154S/83C154S/85C154HVS 4.6.3.2 Mode 1 4.6.3.2.1 Outline Mode 1 is the 10-bit frame UART mode (with one start bit, eight data bits, and one stop bit) where the baud rate may be set to any value depending on the timer/counter 1 or timer/ counter 2 setting.

  • Page 118: Mode 1 Transmit Operation

    INTERNAL SPECIFICATIONS B = f 65536-D RCAP2 where B is the baud rate, f the fundamental frequency (XTAL1·2), and D RCAP2 contents of RCAP2L and RCAP2H (expressed in decimal). 4.6.3.2.3 Mode 1 transmit operation The transmit basic clock (TXCLOCK in Figure 4-31) is obtained from the overflow of a hexadecimal free-run counter where the timer/counter 1 or timer/counter 2 overflow is used as the clock.

  • Page 119: Mode 1 Uart Error Detection

    MSM80C154S/83C154S/85C154HVS 4.6.3.2.5 Mode 1 UART error detection If the following two conditions are satisfied when the hexadecimal counter is in state 10 during reception of the stop bit, it is assumed that new data is received before processing of the previously received data has been completed.
  • Page 120 INTERNAL BUS WRITE START SBUF TO SBUF TCLK BAUD RATE CLOCK TCLK=1 1/16 COUTER TCLK=0 SERIAL PORT INTERRUPT START SERR SAMPLE INPUT SHIFT REG. LOGIC RCLK BAUD RATE CLOCK RCLK=1 1/16 RECEIVE DATA SBUF COUTER NEGLECT LOGIC TIMER/COUNTER2 RCLK=0 OVERFLOW SMOD INTERNAL BUS SMOD=1...
  • Page 121 MSM80C154S/83C154S/85C154HVS Figure 4-32 Serial port (mode 1) timing chart...

  • Page 122: Mode 2

    INTERNAL SPECIFICATIONS 4.6.3.3 Mode 2 4.6.3.3.1 Outline Mode 2 is an 11-bit frame UART mode (with one start bit, eight data bits, one multipurpose data bit, and one stop bit) where the baud rate is 1/64th or 1/32nd of the fundamental oscillator (XTAL1·2) frequency.

  • Page 123: Mode 2 Uart Error Detection

    MSM80C154S/83C154S/85C154HVS When this “1” to “0” RXD change is detected, the hexadecimal counter which had been stopped in reset status commences to count up. When the hexadecimal counter is in state 7, 8, and 9, the start bit is sampled, and is accepted as valid if at least two of the three sampled values are “0”, thereby enabling data reception to continue.
  • Page 124 INTERNAL BUS WRITE START SBUF TO SBUF SMOD BAUD RATE CLOCK SMOD=1 1/16 XTAL1·2 COUTER SMOD=0 SERIAL PORT INTERRUPT START SERR SAMPLE INPUT SHIFT REG. LOGIC BAUD RATE CLOCK 1/16 RECEIVE DATA SBUF COUTER NEGLECT LOGIC INTERNAL BUS...
  • Page 125 MSM80C154S/83C154S/85C154HVS Figure 4-34 Serial port (mode 2) timing chart...

  • Page 126: Mode 3

    INTERNAL SPECIFICATIONS 4.6.3.4 Mode 3 4.6.3.4.1 Outline Mode 3 is another 11-bit frame UART mode (with one start bit, eight data bits, one multi- purpose data bit, and one stop bit). Whereas the baud rate is 1/64th or 1/32nd of the fundamental oscillator frequency in mode 2, the mode 3 baud rate can be freely selected according to the timer/counter 1 or timer/counter 2 setting.

  • Page 127: Mode 3 Transmit Operation

    MSM80C154S/83C154S/85C154HVS B = f 65536-D RCAP2 where B is the baud rate, f the fundamental oscillator (XTAL1·2) frequency, and D RCAP2 the contents of R and R (expressed in decimal). CAP2L CAP2H 4.6.3.4.3 Mode 3 transmit operation The transmit basic clock (TXCLOCK in Figure 4-36) is obtained from a hexadecimal free-run counter overflow where timer/counter 1 or timer/counter 2 overflow is used as the clock.

  • Page 128: Mode 3 Uart Error Detection

    INTERNAL SPECIFICATIONS If the above conditions are not satisfied when the hexadecimal counter is in state 10 during the multi-purpose data bit interval, the received data is disregarded, the SBUF, RB8, and RI flags remain unchanged, and the receive circuit is initialized when the hexadecimal counter is in state 10 during the stop bit interval.
  • Page 129 INTERNAL BUS WRITE START SBUF TO SBUF TCLK BAUD RATE CLOCK TCLK=1 1/16 COUTER TCLK=0 SERIAL PORT INTERRUPT START SERR SAMPLE INPUT SHIFT REG. LOGIC RCLK BAUD RATE CLOCK RCLK=1 1/16 RECEIVE DATA SBUF COUTER NEGLECT LOGIC TIMER/COUNTER2 RCLK=0 OVERFLOW SMOD INTERNAL BUS SMOD=1...
  • Page 130 INTERNAL SPECIFICATIONS Figure 4-36 Serial port (mode 3) timing chart...

  • Page 131: Serial Port Application Examples

    MSM80C154S/83C154S/85C154HVS 4.6.4 Serial port application examples 4.6.4.1 I/O extension I/O extension can be achieved by using the serial port in mode 0. An input extension example is shown in Figure 4-37 and the corresponding timing chart is shown in Figure 4-38. Following output of the latch pulse from PX.X, REN=“1”...
  • Page 132 INTERNAL SPECIFICATIONS An output extension example is shown in Figure 4-39 and the corresponding timing chart is shown in Figure 4-40. After output data has been written into SBUF and the output sequence completed, the latch pulse output from PX.X is obtained and the 74LS164 data is shifted to 74LS373.
  • Page 133 MSM80C154S/83C154S/85C154HVS OUTPUT 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 74LS373 OUTPUT PX.X CONTROL 8D 7D 6D 5D 4D 3D 2D 1D MSM80C154S MSM83C154S QHQG QF QE QDQC QB QA 74LS164 74LS126 SHIFT/ LOAD INPUT SERIAL IN PX.X CONTROL CLOCK 74LS165 INHIBIT H G F E D C B A...
  • Page 134 INTERNAL SPECIFICATIONS In all examples, additional multiple bit I/O extension is made possible by multiple cascade connections of 74LS164 or 74LS165. Figure 4-42 lnput/output extension example timing chart...

  • Page 135: Multi-Processor Systems

    MSM80C154S/83C154S/85C154HVS 4.6.4.2 Multi-processor systems Multi-processor systems can be formed with MSM80C154S/MSM83C154S by using the serial port in mode 2 or mode 3 for inter-processor communications. If reception data bit 9 (multi-purpose data bit) is “1” when SM2 is set in mode 2 or 3, reception data is received and an interrupt is generated.

  • Page 136: Interrupt

    4.7 Interrupt 4.7.1 Outline MSM80C154S/MSM83C154S is equipped with six interrupts. INT0 External interrupt 0 TM0 Timer interrupt 0 INT1 External interrupt 1 TM1 Timer interrupt 1 SI/O Serial port interrupt TM2 Timer interrupt 2 These six interrupts are controlled by interrupt enable register (IE) and interrupt priority register (IP).
  • Page 137 INTERRUPT REQUEST INTERRUPT ENABLE INTERRUPT PRIORITY FLAG REGISTER REGISTER REGISTER SOURCE ENABLE TCON.1 IE0 EXTERNAL INTERRUPT 0 IE.0 IP.0 INTERRUPT ADDRESS DATA TCON.5 TF0 TIMER INTERRUPT 0 IE.0 IP.1 NORMAL TCON.3 IE1 INTERRUPT EXTERNAL INTERRUPT 1 IE.0 IP.2 HIGH PRIORITY TCON.7 TF1 INTERRUPT TIMER INTERRUPT 1...

  • Page 138: Interrupt Enable Register (Ie)

    INTERNAL SPECIFICATIONS 4.7.2 Interrupt enable register (IE) The function of the interrupt enable register (IE, 0A8H) is to enable or disable interrupt processes when an interrupt is requested. To execute the intended interrupt routine, the interrupt is first enabled by setting “1” in the corresponding interrupt bit in the interrupt enable register, and the routine then is executed when the interrupt is requested.

  • Page 139: Interrupt Priority Register (Ip)

    MSM80C154S/83C154S/85C154HVS 4.7.3 Interrupt priority register (IP) The function of the interrupt priority register (IP, 0B8H) is to allocate rights to commence interrupt routines on a priority basis when an interrupt is requested. Interrupt priority can be programmed by setting the bit corresponding to the interrupt request in the interrupt priority register (IP) to “1”.

  • Page 140: Priority Interrupt Routine Flow

    INTERNAL SPECIFICATIONS 4.7.3.1 Priority interrupt routine flow The flow of interrupt processing when a priority interrupt is generated and processed after a routine has been commenced by a non-priority interrupt generated during execution of a main routine program is outlined in Figure 4-45 below. This diagram shows the flow chart up to the point of return to the main routine.

  • Page 141: Interrupt Routine Flow When Priority Circuit Is Stopped

    MSM80C154S/83C154S/85C154HVS 4.7.3.2 Interrupt routine flow when priority circuit is stopped When bit 7 (PCT) of the priority register (IP 0B8H) is set to “1”, all interrupt control is transferred to the interrupt enable register (IE 0A8H). When this mode is set, the interrupt disable instruction (CLR EA) must always be placed at the beginning of the interrupt routine to prevent any other interrupt from being generated.

  • Page 142: Interrupt Priority When Priority Register (Ip) Contents Are All "0

    INTERNAL SPECIFICATIONS 4.7.3.3 Interrupt priority when priority register (IP) contents are all “0” The interrupt priority when the priority register (IP, 0B8H) contents are all “0” indicates the priority in which a certain interrupt is processed in preference to other interrupts when interrupt requests are generated simultaneously.

  • Page 143: Detection Of External Interrupt Signals Int0 And Int1

    MSM80C154S/83C154S/85C154HVS 4.7.4 Detection of external interrupt signals INT0 and INT1 4.7.4.1 Outline of INT signal detection Detect modes of the external interrupt signals 0 and 1 can be set to level-detect or trigger- detect mode by the IT0 and IT1 data values in the timer control register (TCON 88H) as indicated in Table 4-22.

  • Page 144: External Interrupt Signal 0 And 1 Trigger Detection

    INTERNAL SPECIFICATIONS 4.7.4.3 External interrupt signal 0 and 1 trigger detection When bit 0 (IT0) in the timer Control register (TCON 88H) is “1”, external interrupt 0 is edge- activated. And when bit 2 (IT1) is “1”, external interrupt 1 is also edge-activated. With the external interrupt signals in trigger-detect mode, external interrupts 0 and 1 are trigger- detected by the equivalent circuit shown in Figure 4-48.

  • Page 145: Msm80C154S/Msm83C154S Interrupt Response Time Charts

    MSM80C154S/83C154S/85C154HVS 4.7.5 MSM80C154S/MSM83C154S interrupt response time charts 4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied during execution of ordinary instructions in main routine If interrupt conditions are satisfied during execution of an ordinary instruction (which does not manipulate IE or IP) in the main routine, the MSM80C154S/MSM83C154S calls the interrupt address in the next cycle following completion of the ordinary instruction.
  • Page 146 INTERNAL SPECIFICATIONS Figure 4-49 lnterrupt response time chart when interrupt conditions are satisfied during execution of ordinary instruction in main routine...

  • Page 147: Interrupt Response Time Chart When Interrupt Conditions Are Satisfied During Execution Of Ie Or Ip Register Operation Instruction In Main Routine

    MSM80C154S/83C154S/85C154HVS 4.7.5.2 Interrupt response time chart when interrupt conditions are satisfied during execution of IE or IP register operation instruction in main routine If interrupt conditions are satisfied during execution of an instruction used to manipulate the interrupt enable register (IE) or the interrupt priority register (IP) in the main routine, the MSM80C154S/MSM83C154S reactivates the interrupt mask circuit in the next cycle follow- ing completion of the register manipulation instruction.
  • Page 148 INTERNAL SPECIFICATIONS Figure 4-50 Interrupt response time chart when interrupt conditions are satisfied during execution of IE or IP register manipulating instruction in main routine...

  • Page 149: Interrupt Response Time Chart When An Ordinary Instruction Is Executed After Temporarily Returning To The Main Routine From Continuous Interrupt Processing

    MSM80C154S/83C154S/85C154HVS 4.7.5.3 Interrupt response time chart when an ordinary instruction is executed after temporarily returning to the main routine from continuous interrupt processing If an ordinary instruction (which does not manipulate IE or IP) is executed after returning to the main routine following execution of the interrupt routine end instruction RETI, and if the next interrupt conditions have been met during execution of a previous interrupt routine, the MSM80C154S/MSM83C154S calls the interrupt address in the next cycle following execu- tion of one main routine instruction.
  • Page 150 INTERNAL SPECIFICATIONS Figure 4-51 Interrupt response time chart when ordinary instruction is executed after returning to main routine during continuous interrupt processing...

  • Page 151: Interrupt Response Time Chart When An Ie Or Ip Manipulating Instruction Is Executed After Temporarily Returning To The Main Routine From Continuous Interrupt Processing

    MSM80C154S/83C154S/85C154HVS 4.7.5.4 Interrupt response time chart when an IE or IP manipulating instruction is executed after temporarily returning to the main routine from continuous interrupt processing If the next interrupt conditions are satisfied during execution of an interrupt processing routine and the interrupt terminating instruction RETI is then executed and followed by a return to the main routine where an instruction which manipulates the interrupt enable register (IE) or interrupt priority register (IP) is executed, the MSM80C154S/MSM83C154S activates the...
  • Page 152 INTERNAL SPECIFICATIONS Figure 4-52 Interrupt response time chart when IE or IP manipulating instruction is executed after returning to main routine during continuous interrupt processing...

  • Page 153: Cpu "Power Down

    MSM80C154S/83C154S/85C154HVS 4.8 CPU “Power Down” 4.8.1 Outline Since the internal MSM80C154S/MSM83C154S circuits have been designed as completely static circuits, all internal information (register data) is preserved if XTAL1·2 oscillation is stopped. This feature is utilized to incorporate a fuller range of power down modes. In idle mode (IDLE) where “1”...
  • Page 154 INTERNAL SPECIFICATIONS XTAL 2 TIMER, S-I/O & INTERRUPT CPU CONTROL CLOCK XTAL 1 CONTROL PCON, 87H — SMOD • Figure 4-53 ldle mode equivalent circuit...
  • Page 155 MSM80C154S/83C154S/85C154HVS Table 4-23 CPU pin details in idle mode Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output P1.4 Port data output Port data output...
  • Page 156 INTERNAL SPECIFICATIONS Figure 4-54 Idle mode setting time chart (internal ROM mode)
  • Page 157 MSM80C154S/83C154S/85C154HVS Figure 4-55 Idle mode setting time chart (external ROM mode)

  • Page 158: Soft Power Down Mode (Pd) Setting

    INTERNAL SPECIFICATIONS 4.8.3 Soft power down mode (PD) setting Soft power down mode (PD) is set when “1” is set in bit 1 (PD) of the power control register (PCON 87H). The circuit connection involved in this setting is shown in Figure 4-56. Soft power down mode cancellation conditions can be set through manipulation of bit 5 (RPD) of the power control register.
  • Page 159 XTAL 2 CPU CLOCK XTAL 1 CONTROL I/O FLOATING PCON 87H — SMOD • IOCON 0F8H — SERR P3HZ P2HZ P1HZ •...
  • Page 160 INTERNAL SPECIFICATIONS PCON5(RPD) IE0 or 1 PDRESET INT0 or INT1 RESET M END Figure 4-57 Power down cancellation circuit at INTERRUPT level input INT0 or INT1 PCON5(RPD) IE0 or 1 PDRESET W TCON RESET Figure 4-58 Power down cancellation circuit at INTERRUPT edge input...
  • Page 161 MSM80C154S/83C154S/85C154HVS TIMER0, 1 F/F1 F/F2 F/F1 F/F2 PDRESET T0 or T1 RESET RESET TF0 or 1 PCON5(RPD) Figure 4-59 TIMER0, 1 power down cancellation circuit...
  • Page 162 INTERNAL SPECIFICATIONS Table 4-24 CPU pin details (ALF=0) in soft power down mode (PD) Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output...
  • Page 163 MSM80C154S/83C154S/85C154HVS Figure 4-60 Soft power down mode setting time chart (internal ROM mode)
  • Page 164 INTERNAL SPECIFICATIONS Figure 4-61 Soft power down mode setting time chart (external ROM mode)
  • Page 165 MSM80C154S/83C154S/85C154HVS Table 4-25 CPU pin details (ALF=1) in soft power down mode (PD) Name Internal ROM External ROM P1.0/T2 Floating Floating P1.1/T2EX Floating Floating P1.2 Floating Floating P1.3 Floating Floating P1.4 Floating Floating P1.5 Floating Floating P1.6 Floating Floating P1.7 Floating Floating RESET...
  • Page 166 INTERNAL SPECIFICATIONS Figure 4-62 Soft power down mode setting and I/O floating time chart (internal ROM mode)
  • Page 167 MSM80C154S/83C154S/85C154HVS Figure 4-63 Soft power down mode setting and I/O floating time chart (external ROM mode)

  • Page 168: Hard Power Down Mode (Hpd) Setting

    INTERNAL SPECIFICATIONS 4.8.4 Hard power down mode (HPD) setting To set hard power down mode (HPD), “1” is set in bit 6 (HPD) of the power control register (PCON 87H) in advance to attain the circuit connections shown in Figure 4-61. Hard power down mode is set when the level of the power failure detect signal applied to the HPDI pin (bit 5 of port 3) is changed from level “1”...
  • Page 169 XTAL 2 CPU CLOCK XTAL 1 HPDI CONTROL I/O FLOATING PCON 87H — SMOD • • IOCON 0F8H — SERR P3HZ P2HZ P1HZ •...
  • Page 170 INTERNAL SPECIFICATIONS Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD) Name Internal ROM External ROM P1.0/T2 Port data output Port data output P1.1/T2EX Port data output Port data output P1.2 Port data output Port data output P1.3 Port data output Port data output...
  • Page 171 MSM80C154S/83C154S/85C154HVS Figure 4-65 Hard power down mode setting time chart (internal ROM mode)
  • Page 172 INTERNAL SPECIFICATIONS Figure 4-66 Hard power down mode setting time chart (external ROM mode)
  • Page 173 MSM80C154S/83C154S/85C154HVS Table 4-27 CPU pin details (ALF=1) in hard power down mode (HPD) Name Internal ROM External ROM P1.0/T2 Floating Floating P1.1/T2EX Floating Floating P1.2 Floating Floating P1.3 Floating Floating P1.4 Floating Floating P1.5 Floating Floating P1.6 Floating Floating P1.7 Floating Floating RESET...
  • Page 174 INTERNAL SPECIFICATIONS Figure 4-67 Hard power down mode setting and I/O floating time chart (internal ROM mode)
  • Page 175 MSM80C154S/83C154S/85C154HVS Figure 4-68 Hard power down mode setting andl/Of loating time chart (external ROM mode)

  • Page 176: Cpu Power Down Mode (Idle, Pd, And Hpd) Cancellation (Cpu Activation)

    INTERNAL SPECIFICATIONS 4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) 4.9.1 Outline CPU power down mode (IDLE, PD, and HPD) can be cancelled (CPU activation) in the following two ways. The CPU is reset when a “1” reset signal is applied to the CPU RESET pin, and the program is executed from address 0.
  • Page 177 MSM80C154S/83C154S/85C154HVS Figure 4-69 Restart from idle mode by reset (internal ROM mode)
  • Page 178 INTERNAL SPECIFICATIONS Figure 4-70 Restart from idle mode by reset (external ROM mode)
  • Page 179 MSM80C154S/83C154S/85C154HVS Figure 4-71 Restart from soft power mode by reset (internal ROM mode)
  • Page 180 INTERNAL SPECIFICATIONS Figure 4-72 Restart from soft power mode by reset (external ROM mode)
  • Page 181 MSM80C154S/83C154S/85C154HVS Figure 4-73 Restart from hard power down mode by reset (internal ROM mode)
  • Page 182 INTERNAL SPECIFICATIONS Figure 4-74 Restart from hard power down mode by reset (external ROM mode)

  • Page 183: Cancellation Of Cpu Power Down Mode(Idle, Pd)By Interrupt Signal

    MSM80C154S/83C154S/85C154HVS 4.9.3 Cancellation of CPU power down mode (IDLE, PD) by interrupt signal When idle mode (IDLE) and soft power down mode (PD) are cancelled by interrupt signal, power down mode cancellation condition is determined by bit 5 (RPD) of the power control register (PCON 87H) shown in Table 4-29.
  • Page 184 INTERNAL SPECIFICATIONS IE0 [TCON.1] IE.0 TF0 [TCON.5] IE.1 IE1 [TCON.3] IE.2 IDLE, PD MODE TF1 [TCON.7] INTERRUPT & IE.3 RESTART RI/TI [SCON.0, 1] IE.4 EXF2/TF2[T2CON.6, 7] IE.5 IE.7 Figure 4-75 Equivalent circuit for, DLE and PD mode rancellation by interrupt signal...
  • Page 185 MSM80C154S/83C154S/85C154HVS Figure 4-76 Restart from idle mode by interrupt INT0 or 1 (internal ROM mode)
  • Page 186 INTERNAL SPECIFICATIONS Figure 4-77 Restart from idle mode by interrupt INT0 or 1 (external ROM mode)
  • Page 187 MSM80C154S/83C154S/85C154HVS Figure 4-78 Restart from soft power down mode by Interrupt INT0 or 1 (internal ROM mode)
  • Page 188 INTERNAL SPECIFICATIONS Figure 4-79 Restart from soft power down mode by interrupt INT0 or 1 (external ROM mode)

  • Page 189: Cancellation Of Cpu Power Down Mode (Idle, Pd) By Interrupt Request Signal And Restart From Next Address Of Stop Address

    MSM80C154S/83C154S/85C154HVS 4.9.3.2 Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal and restart from next address of stop address To cancel idle mode (IDLE) or soft power down mode (PD) by interrupt request signal and then resume execution from the next address after the stop address, “1” is set in bit 5 (RPD) of the power control register.
  • Page 190 INTERNAL SPECIFICATIONS Figure 4-81 Restart from idle mode by INT0 or 1 (internal ROM mode)
  • Page 191 MSM80C154S/83C154S/85C154HVS Figure 4-82 Restart from idle mode by INT0 or 1 (external ROM mode)
  • Page 192 INTERNAL SPECIFICATIONS Figure 4-83 Restart from soft power down mode by INT0 or 1 (internal ROM mode)
  • Page 193 MSM80C154S/83C154S/85C154HVS Figure 4-84 Restart from soft power down mode by INT0 or 1 (external ROM mode)

  • Page 194: Msm80C154S/83C154S Battery Backup With Hard Power Down Mode

    INTERNAL SPECIFICATIONS 4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode Figures 4-85-1/2 and 2/2 show the examples of the MSM80C154S/83C154S battery backup circuits with hard power down mode. The hard power down mode serves to retain data stored in the CPU and external RAM if the AC 100V power failure occurs. Figure 4-85-1/2 shows the CPU, power failure detector, and external RAM control unit.
  • Page 195 MSM80C154S/83C154S/85C154HVS 3N-100AAL SN74NS138 RRB51A05W 5.1K MSM80C154S/83C154S 74HC08 1000 5.1K 5.1K 5.1K ICL3211 Figure 4-85-1/2 MSM80C154S/83C154S battery back up with hard power down mode...
  • Page 196 INTERNAL SPECIFICATIONS SN74LS373 Figure 4-85-2/2 MSM80C154S/83C154S battery back up with hard power down mode...

  • Page 197: Input/Output Ports

    MSM80C154S/83C154S/85C154HVS 5. INPUT/OUTPUT PORTS...
  • Page 198 INPUT/OUTPUT PORTS...

  • Page 199: Outline

    MSM80C154S/83C154S/85C154HVS 5. INPUT/OUTPUT PORTS 5.1 Outline MSM80C154S/MSM83C154S is equipped with four 8-bit input/output ports. The functions of these four ports (port 0, 1, 2, and 3) are listed below. Port 0: Input/output bus port, address output port, and data input/output port. Port 1: Quasi-bidirectional input/output port and control input pin.
  • Page 200 INPUT/OUTPUT PORTS INTERNAL BUS PORT 0 READ MODIFY Figure 5-2 Port 0 input/Output port equivalent circuit in internal ROM mode INTERNAL BUS PC0~7 RA0~7 ACC0~7 PORT 0 READ Figure 5-3 Port 0 equivalent circuit during address and data input/output in external ROM/RAM mode...
  • Page 201 MSM80C154S/83C154S/85C154HVS Table 5-1 Port 0 pin table PORT0 Accumulator bit Address P0.0 ACC.0 RA –0 P0.1 ACC.1 RA –1 P0.2 ACC.2 RA –2 P0.3 ACC.3 RA –3 P0.4 ACC.4 RA –4 P0.5 ACC.5 RA –5 P0.6 ACC.6 RA –6 P0.7 ACC.7 RA –7...

  • Page 202: Port 1

    INPUT/OUTPUT PORTS 5.3 Port 1 Port 1 is a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-4. A “quasi-bidirectional port” refers to a port which has internal pull-up resistance when used as an input port.
  • Page 203 MSM80C154S/83C154S/85C154HVS INTERNAL CONTROL MODIFY PORT 1 READ Figure 5-4 Port 1 internal equivalent circuit...
  • Page 204 INPUT/OUTPUT PORTS R=500 R=500 R=10k R=10k R=100k R=100k INTERNAL INTERNAL READ READ (A) When accelerator circuit is activated (B) When "1" data is held R=500 R=10k R=100k INTERNAL READ (C) When "0" data is held Figure 5-5 Quasi-bidirectional port equivalent circuit...
  • Page 205 MSM80C154S/83C154S/85C154HVS XTAL1 PSEN W-PORT CPU-BUS PORT-OUT PORT DATA="0" PORT DATA="1" *P1·2·3TR-ON Figure 5-6 Quasi-bidirectional port accelerator circuit operation time chart...
  • Page 206 INPUT/OUTPUT PORTS R=100k R=10k INTERNAL READ (A) "1" data writing equivalent circuit R=100k R=10k INTERNAL READ (B) "1" data input equivalent circuit R=100k R=10k INTERNAL READ (C) "0" data input equivalent circuit Figure 5-7 Quasi-bidirectional port input equivalent circuit...
  • Page 207 MSM80C154S/83C154S/85C154HVS Table 5-2 Port 1 CPU control pin table PORT1 Function P1.0 T2 [TIMER COUNTER 2 EXTERNAL CLOCK] P1.1 T2EX [TIMER COUNTER 2 EXTERNAL CONTROL] Table 5-3 Port 1 pin table PORT1 Accumulator bit P1.0 ACC.0 P1.1 ACC.1 P1.2 ACC.2 P1.3 ACC.3 P1.4...

  • Page 208: Port 2

    INPUT/OUTPUT PORTS 5.4 Port 2 Port 2 can function as a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-8. It can also be used for output of addresses 8 thru 15 in external ROM and external RAM (using DPTR) modes. When port 2 is used as a quasi-bidirectional port, it functions in much the same way as port 1.
  • Page 209 MSM80C154S/83C154S/85C154HVS PC/DATA PC8~15 RA8~15 (DPH) PORT 2 Figure 5-9 Port 2 address output equivalent circuit for external memory Table 5-4 Port 2 pin table PORT2 Accumulator bit Address P2.0 ACC.0 RA –8 P2.1 ACC.1 RA –9 P2.2 ACC.2 RA –10 P2.3 ACC.3 RA –11...

  • Page 210: Port 3

    INPUT/OUTPUT PORTS 5.5 Port 3 Port 3 can function as a quasi-bidirectional port capable of handling input and output of 8-bit data in the circuit configuration outlined in Figure 5-10, and can also be used as a CPU control pin. When port 3 is used as a quasi-bidirectional port, all functions are identical to those described for port 1.
  • Page 211 MSM80C154S/83C154S/85C154HVS Table 5-5 Port 3 CPU control pin function table PORT3 PORT 3 PIN ALTERNATE FUNCTION P3.0 RXD [SERIAL INPUT PORT] P3.1 TXD [SERIAL OUTPUT PORT] INT0 [EXTERNAL INTERRUPT 0] P3.2 INT1 [EXTERNAL INTERRUPT 1] P3.3 P3.4 [TIMER/COUNTER 0 CLOCK] [TIMER/COUNTER 1 CLOCK] P3.5 HPDI [HARD POWER DOWN INPUT]...

  • Page 212: Port 0, 1, 2, And 3 Output And Floating Status Settings In Cpu Power Down Mode (Pd, Hpd)

    INPUT/OUTPUT PORTS 5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down Mode (PD, HPD) The port 0, 1, 2, and 3 output status can be set to either data output or floating when MSM80C154S/MSM83C154S is in power down mode (PD, HPD).
  • Page 213 MSM80C154S/83C154S/85C154HVS MODIFY PORT1, 2, 3 P2-10k P3-100k W PORT READ INTERNAL BUS POWER DOWN [IOCON 0F8H] Flag — SERR P3HZ P2HZ P1HZ • • • • • Figure 5-11 Control circuit for ports 0, 1, 2, 3 by lOCON...

  • Page 214: High Impedance Input Port Setting Of Each Quasi-Bidirectional Port 1, 2, And 3

    INPUT/OUTPUT PORTS 5.7 High Impedance Input Port Setting of Each Ouasi-bidirectional Port 1, 2, and 3 Each of the quasi-bidirectional input ports 1, 2, and 3 can be set as high impedance input ports. This high impedance condition is achieved by setting “1” in bits 1 (P1HZ), 2 (P2HZ), and 3 (P3HZ) of the I/O control register (IOCON 0F8H) shown in Figure 5-11.

  • Page 215: Precautions When Driving External Transistors By Quasi-Bidirectional

    MSM80C154S/83C154S/85C154HVS 5.9 Precautions When Driving External Transistors by Ouasi-bidirectional Port Output Signals The following points must be carefully considered when quasi-bidirectional ports are used to drive a transistor by the circuit shown in Figure 5-12. Even though the CPU output in this circuit is at “1” level, the port output pin level may be clamped by the base-emitter voltage V (0.7V) of an external NPN transistor, resulting in a pin level of “0”.
  • Page 216 INPUT/OUTPUT PORTS 100k CPU "1" OUT Figure 5-13 Drive circuit for NPN transistor by level shifter CPU "0" OUT Figure 5-14 PNP transistor direct connection drive circuit...

  • Page 217: Port Output Timing

    MSM80C154S/83C154S/85C154HVS 5.10 Port Output Timing One machine cycle instruction output timing XTAL1 1M CYCLE OP W-PORT PORT-OUT PORT OLD DATA PORT NEW DATA INC data address XCH A, data address DEC data address CPL bit address MOV data address, A CLR bit address ORL data address, A SETB bit address...

  • Page 218: Two Machine Cycle Instruction Output Timing

    INPUT/OUTPUT PORTS Two machine cycle instruction output timing XTAL1 2M CYCLE OP W-PORT PORT-OUT PORT OLD DATA PORT NEW DATA MOV data address, # data MOV data address 1, data address 2 ORL data address, # data MOV bit address, C ANL data address, # data XRL data address, # data JBC bit address, code address...

  • Page 219: Port Data Manipulating Instructions

    MSM80C154S/83C154S/85C154HVS 5.11 Port Data Manipulating Instructions The MSM80C154S/MSM83C154S port operation instructions for ports 0, 1, 2, and 3 are divided into two groups-one where external signals applied to the port pin are used according to the instruction to be used, and the other where port latch data uneffected by the external signals is used.
  • Page 220 INPUT/OUTPUT PORTS...

  • Page 221: Electrical Characteristics

    MSM80C154/83C154/85C154 6. ELECTRICAL CHARACTERISTICS...
  • Page 222 ELECTRICAL CHARACTERISTICS...

  • Page 223: Absolute Maximum Ratings

    –40~+85 °C temperature *1 Dpends on the specifications for the oscillator or ceramic resonator. The MSM85C154HVS is guaranteed for operation at frequencies of up to 22 MHz. *2 The MSM85C154HVS is guaranteed for operation at ordinary temperatures. (ms) EXTCLK (MHz)

  • Page 224: Dc Characteristics

    ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics 1 =4.0 to 6.0V,V =0V, Ta=–40 C to +85 C) Measuring Parameter Symbol Conditions Unit Circuit Input Low Voltage — –0.5 — 0.2V –0.1 Except XTAL1, EA Input High Voltage 0.2V — +0.5 and RESET +0.9 XTAL1 and EA Input High Voltage...
  • Page 225 MSM80C154/83C154/85C154 Maximum Power Supply Current Normal Operation I (mA) Freq. 1MHz 3MHz 12MHz 12.0 16.0 20.0 16MHz 16.0 20.0 25.0 20MHz 19.0 25.0 30.0 4.5V Freq. 24MHz 25.0 29.0 35.0 Maximum Power Supply Current Idle Mode I (mA) Freq. 1MHz 3MHz 12MHz 16MHz...
  • Page 226 ELECTRICAL CHARACTERISTICS DC Characteristics 2 =2.2 to 4.0 V, V =0 V, Ta=-40 to +85°C) Meas- uring Parameter Condition Min. Typ. Max. Unit Symbol circuit Input Low Voltage — –0.5 — 0.25 V –0.1 Except XTAL1, EA, Input High Voltage 0.25 V +0.9 —...
  • Page 227 MSM80C154/83C154/85C154 Measuring circuits Note 2 Note 1 Note Note 2 Note Note Note 1 : Repeated for specified input pins. 2 : Repeated for specified output pins. 3 : Input logic for specified status.

  • Page 228: External Program Memory Access Ac Characteristics

    ELECTRICAL CHARACTERISTICS 6.4 External Program Memory Access AC Characteristics =2.2 to 6.0V, V =0V, Ta=–40 C to +85 C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load Variable clock from Parameter Symble Unit 1 to 24 MHz Min.
  • Page 229 MSM80C154/83C154/85C154 External program memory read cycle tLHLL tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tPXAV tPXIZ tLLAX tAZPL tPXIX PORT 0 A0~A7 INSTR IN A0~A7 tAVIV PORT 2 A8~A15 A8~A15 A0~A7...

  • Page 230: External Data Memory Access Ac Characteristics

    ELECTRICAL CHARACTERISTICS 6.5 External Data Memory Access AC Characteristics VCC=2.2 to 6.0V, VSS=0V, Ta=–40 C to +85 C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load Variable clock from Parameter Symbol Unit 1 to 24 MHz Min.
  • Page 231 MSM80C154/83C154/85C154 External data memory read cycle tLHLL tWHLH PSEN tLLDV tLLWL tRLRH tRHDZ tAVLL tLLAX tRLDV tRHDX tAZRL INSTR A0~A7 A0~A7 A0~A7 PORT 0 DATA IN RrorDPL tAVWL tAVDV PORT 2 A8~A15 PCH P2.0~P2.7 DATA or A8~A15 PCH A8~A15 PCH External data memory write cycle tLHLL tWHLH...

  • Page 232: Serial Port (I/O Extension Mode) Ac Characteristics

    ELECTRICAL CHARACTERISTICS 6.6 Serial Port (I/O Extension Mode) AC Characteristics =2.2 to.0V, V =0V, Ta=–40 C to 85 C Parameter Symbol Unit Serial Port Clock Cycle Time tXLXL 12tCLCL — Output Data Setup to Clock Rising Edge tQVXH 10tCLCL–133 — Output Data Hold After Clock Rising Edge tXHQX 2tCLCL–75...
  • Page 233 MACHINE CYCLE tXLXL SHIFT CLOCK tQVXH tXHQX OUTPUT DATA tXHDV tXHDX INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID...

  • Page 234: Ac Characteristics Measuring Conditions

    ELECTRICAL CHARACTERISTICS 6.7 AC Characteristics Measuring Conditions Input/output signal TEST POINT * The input signals in AC test mode are either V (logic “1”) orV (logic “0”). Timing measurements are made atV (logic “1”) and V (10gic “0”). 2. Floating Floating * The port 0 floating interval is measured from the time the port 0 pin Voltage drops below after sinking to GND at 2.4mA when switching to floating status from a “1”...

  • Page 235: Xtal1 External Clock Input Waveform Conditions

    MSM80C154/83C154/85C154 6.8 XTAL1 External Clock Input Waveform Conditions Parameter Symbol Unit Oscillator Freq. 1/tCLCL High Time tCHCX — Low Time tCLCX — Rise Time tCLCH — Fall Time tCHCL — –0.5 0.7V EXTERMINAL 0.2V –0.1 OSCILLATOR 0.45V tCHCX tCHCX tCLCH SIGNAL tCHCL tCLCL...

  • Page 236: Description Of Instructions

    7. DESCRIPTION OF INSTRUCTIONS...
  • Page 237 MSM80C154S/83C154S/85C154HVS...

  • Page 238: Outline

    DESCRIPTION OF INSTRUCTIONS 7. DESCRIPTION OF INSTRUCTIONS 7.1 Outline MSM80C154S/MSM83C154S is a microcontroller designed for parallel processing in an 8-bit ALU. The instructions consist of 8-bit units of data, and are available as 1-word 1 - machine, 2-machine, and 4-machine cycle instructions as well as 2-word 1-machine and 2-machine cycle instructions and 3-word 2-machine cycle instructions.

  • Page 239: Description Of Instruction Symbols

    MSM80C154S/83C154S/85C154HVS 7.2 Description of Instruction Symbols The instruction symbols have the following meanings. Accumulator Register pair Auxiliary carry Arithmetic operation register Carry (the bit 7 carry represented by CY is changed to C in Chapter 7.) DPTR Data pointer Program counter Register representation (r=0/1, or r=0 thru 7) Stack pointer Logical AND...

  • Page 240: List Of Instructions

    DESCRIPTION OF INSTRUCTIONS 7.3 List of Instructions MSM80C154S/MSM83C154S instruction table...

  • Page 241: Simplified Description Of Instructions

    Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 A, Rr 0 0 1 0 1 r (AC),(OV),(C),(A) (A)+(Rr) r=0~7 0 0 1 0 0 1 0 1 A, direct (AC),(OV),(C),(A) (A)+(direct address) A, @Rr 0 0 1 0 0 1 1 (AC),(OV),(C),(A) (A)+((Rr))
  • Page 242 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 1 0 0 (A) 0 1 1 1 1 0 1 0 0 (A) (A) 0 0 1 0 0 0 1 1 Accumulator 0 0 1 1 0 0 1 1 Accumulator...
  • Page 243 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 (A) (A)+1 0 0 0 0 1 r (Rr) (Rr)+1 r=0~7 0 0 0 0 0 1 0 1 direct (direct address) (direct address)+1 0 0 0 0 0 1 1...
  • Page 244 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 A, #data (A) (A)OR#data 0 1 0 0 0 0 1 0 direct, A (direct address) (direct address)OR(A) 0 1 0 0 0 0 1 1 direct,#data (direct address) (direct address)OR#data...
  • Page 245 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 1 1 @Rr, #data ((Rr)) #data r=0 or 1 1 0 0 1 0 0 0 0 DPTR, (DPTR) #data #data 1 1 0 0 0 0 1 1...
  • Page 246 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 0 0 1 0 (bit address) (bit address) A, Rr 1 1 1 0 1 r (A) (Rr) r=0~7 1 1 1 0 0 1 0 1 A, direct (A) (direct address)
  • Page 247 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 A, Rr 0 0 0 1 1 r (A) (Rr) r=0~7 1 1 0 0 0 1 0 1 A, direct (A) (direct address) A, @Rr 1 1 0 0 0 1 1 (A) ((Rr))
  • Page 248 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 RETI 0 0 1 1 0 0 1 0 ) ((SP)) 8~15 (SP) (SP)–1 ) ((SP)) (SP) (SP)–1 *INTERRUPT ENABLE 0 0 0 0 1 (PC) (PC)+2 AJMP addr 11...
  • Page 249 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 CJNE A, #data, rel 1 0 1 1 0 1 0 0 (PC) (PC)+3 (A) #data THEN (PC) (PC)+relative offset (A)<#data THEN (C) 1 ELSE (C) 0 CJNE...
  • Page 250 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 CJNE @Rr, #data, 1 0 1 1 0 1 1 (PC) (PC)+3 ((Rr)) #data r=0 or 1 THEN (PC) (PC)+relative offset ((Rr))<#data r=0 or 1 THEN (C) 1 ELSE...
  • Page 251 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 0 0 (PC) (PC)+2 (A) 0 THEN (PC) (PC)+relative offset 0 1 0 0 0 0 0 0 (PC) (PC)+2 (C)=1 THEN...
  • Page 252 Instruction code Classifi- Mnemonic Byte Cycle Description Page cation D7 D6 D5 D4 D3 D2 D1 D0 MOVX A, @Rr 1 1 1 0 0 0 1 (A) ((Rr)) EXTERNAL RAM r=0 or 1 MOVX A, @DPTR 1 1 1 0 0 0 0 0 (A) ((DPTR)) EXTERNAL RAM MOVX @Rr, A...

  • Page 253: Detailed Description Of Msm80C154S/Msm83C154S Instructions

    MSM80C154S/83C154S/85C154HVS 7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions Note: “direct address” is represented as “data address” in this detailed description. 1. ACALL code address (Absolute call within 2K bytes page) Instruction code Byte 1 Call address Byte 2 Operations (PC) (PC)+2 (SP) (SP)+1 ((SP)) (PC (SP) (SP)+1...
  • Page 254 DESCRIPTION OF INSTRUCTIONS 2. ADD A, #data (Add immediate data) Instruction code Byte 1 #data Byte 2 Operation (A) (A)+#data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description An 8-bit immediate data value is added to the accumulator. The result is placed in the accumulator, and the flags are updated.
  • Page 255 MSM80C154S/83C154S/85C154HVS 3. ADD A, @Rr (Add indirect address) Instruction code Byte 1 Operation (A) (A)+((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The data memory location contents addressed by the register r contents are added to the accumulator.
  • Page 256 DESCRIPTION OF INSTRUCTIONS 4. ADD A, Rr (Add register) Instruction code Byte 1 Operation (A) (A)+(Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The register r contents are added to the accumulator. The result is placed in the accumulator, and the flags are updated.
  • Page 257 MSM80C154S/83C154S/85C154HVS 5. ADD A, data address (Add memory) Instruction code Byte 1 Data address Byte 2 Operation (A) (A)+(data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The specified data address contents are added to the accumulator.
  • Page 258 DESCRIPTION OF INSTRUCTIONS 6. ADDC A, #data (Add carry plus immediate data to accumulator) Instruction code Byte 1 #data Byte 2 Operation (A) (A)+(C)+#data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag is added to the accumulator, and an 8-bit immediate data is added to that result.
  • Page 259 MSM80C154S/83C154S/85C154HVS 7. ADDC A, @Rr (Add carry plus indirect address to accumulator) Instruction code Byte 1 Operation (A) (A)+(C)+((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag is added to the accumulator, and the contents of data memory location addressed by the register r contents are added to the accumulator.
  • Page 260 DESCRIPTION OF INSTRUCTIONS 8. ADD A, Rr (Add carry plus register to accumulator) Instruction code Byte 1 Operation (A) (A)+(C)+(Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag is added to the accumulator,and the register r contents are added to the result.
  • Page 261 MSM80C154S/83C154S/85C154HVS 9. ADDC A, data address (Add carry plus memory to accumulator) Instruction code Byte 1 Data address Byte 2 Operation (A) (A)+(C)+(data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag is added to the accumulator,and the specified data address contents are added to that result.
  • Page 262 DESCRIPTION OF INSTRUCTIONS 10. AJMP code address (Absolute jump within 2K byte page) Instruction code Byte 1 Call address Byte 2 Operations (PC) (PC)+2 0~10 0~10 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description After an increment ,the program counter PC is replaced by 0~10 11-bit page address data A...
  • Page 263 MSM80C154S/83C154S/85C154HVS 11. ANL A, #data (Logical AND immediate data to accumulator) Instruction code Byte 1 #data Byte 2 Operation (A) (A) AND #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical AND between an 8-bit immediate data value and the accumulator contents is determined.
  • Page 264 DESCRIPTION OF INSTRUCTIONS 12. ANL A, @Rr (Logical AND indirect address to accumulator) Instruction code Byte 1 Operation (A) (A) AND ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical AND between the accumulator contents and the data memory location contents addressed by the register r contents is determined.
  • Page 265 MSM80C154S/83C154S/85C154HVS 13. ANL A, Rr (Logical AND register to accumulator) Instruction code Byte 1 Operation (A) (A) AND (Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical AND between the accumulator contents and the register r contents is determined.
  • Page 266 DESCRIPTION OF INSTRUCTIONS 14. ANL A, data address (Logical AND memory to accumulator) Instruction code Byte 1 Data address Byte 2 Operation (A) (A) AND (data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical AND between the accumulator contents and the specified data address contents is determined.
  • Page 267 MSM80C154S/83C154S/85C154HVS 15. ANL C, bit address (Logical AND bit to carry flag) Instruction code Byte 1 Bit address Byte 2 Operation (C) (C) AND (bit address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical AND between the carry flag and the specified bit address contents is determined.
  • Page 268 DESCRIPTION OF INSTRUCTIONS 16. ANL C,/bit address (Logical AND complement bit to carry flag) Instruction code Byte 1 Bit address Byte 2 (C) (C) AND (bit address) Operation Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) •...
  • Page 269 MSM80C154S/83C154S/85C154HVS 17. ANL data address, #data (Logical AND immediate data to memory) Instruction code Byte 1 Data address Byte 2 #data Byte 3 Operation (data address) (data address) AND #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The logical AND between an 8-bit immediate data value and the...
  • Page 270 DESCRIPTION OF INSTRUCTIONS 18. ANL data address, A (Logical AND accumulator to memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (data address) AND (A) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The logical AND between the accumulator and the specified data address contents is determined.
  • Page 271 MSM80C154S/83C154S/85C154HVS 19. CJNE @Rr, #data, code address (Compare indirect address to immediate data, jump if not equal) Instruction code Byte 1 #data Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF ((Rr)) #data r=0 or 1 THEN (PC) (PC)+relative offset IF ((Rr))<#data r=0 or 1 THEN (C) 1...
  • Page 272 DESCRIPTION OF INSTRUCTIONS Example CJNE @R1, #05H, TEST SOURCE 00B4 2155 TEST:AJMP TEST1 0118 B70599 COMP:CJNE @R1, #05H, TEST 011B 020500 OUT:LJMP OUT1 Instruction code 1 0 1 1 0 1 1 1 Byte 1 0 0 0 0 0 1 0 1 Byte 2 1 0 0 1 1 0 0 1 Byte 3...
  • Page 273 MSM80C154S/83C154S/85C154HVS 20. CJNE A, #data, code address (Compare immediate data to accumulator, jump if not equal) Instruction code Byte 1 #data Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF (A) #data THEN (PC) (PC)+relative offset IF (A)<#data THEN (C) 1 ELSE (C) 0...
  • Page 274 DESCRIPTION OF INSTRUCTIONS Example CJNE A, #0AH, SS1 SOURCE 0064 SS1:MOV R7, A 00C8 B40599 COMP:CJNE A, #0AH, SS1 00CB INCR:INC R5 Instruction code 1 0 1 1 0 1 0 0 Byte 1 0 0 0 0 1 0 1 0 Byte 2 1 0 0 1 1 0 0 1 Byte 3...
  • Page 275 MSM80C154S/83C154S/85C154HVS 21. CJNE A, data address, code address (Compare memory to accumulator, jump if not equal) Instruction code Byte 1 Data address Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF (A) (data address) THEN (PC) (PC)+relative offset IF (A)<(data address) THEN (C) 1 ELSE...
  • Page 276 DESCRIPTION OF INSTRUCTIONS Example CJNE A, 50H, NEXT SOURCE 10DC B55044 COMP:CJNE A, 50H, NEXT 10DF 120100 CAL:LCALL TEST 1123 NEXT:DEC A Instruction code 1 0 1 1 0 1 0 1 Byte 1 0 1 0 1 0 0 0 0 Byte 2 0 1 0 0 0 1 0 0 Byte 3...
  • Page 277 MSM80C154S/83C154S/85C154HVS 22. CJNE Rr, #data, code address (Compare immediate data to register, jump if not equal) Instruction code Byte 1 #data Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF ((Rr)) #data r=0 thru 7 THEN (PC) (PC)+relative offset IF ((Rr))<#data r=0 thru 7 THEN (C) 1...
  • Page 278 DESCRIPTION OF INSTRUCTIONS Example CJNE R4, #32H, COUNT SOURCE 0473 COUNT:INC R4 0482 BC32EE COMP:CJNE R4, #32H, COUNT Instruction code 1 0 1 1 1 1 0 0 Byte 1 0 0 1 1 0 0 1 0 Byte 2 1 1 1 0 1 1 1 0 Byte 3 Before execution...
  • Page 279 MSM80C154S/83C154S/85C154HVS 23. CLR A (Clear accumulator) Instruction code Byte 1 Operation (A) 0 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The accumulator is cleared to 0 and flag is updated. Example CLR A Instruction code 1 1 1 0 0 1 0 0 Byte 1...
  • Page 280 DESCRIPTION OF INSTRUCTIONS 24. CLR C (Clear carry flag) Instruction code Byte 1 Operation (C) 0 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The carry flag is cleared to 0. Example CLR C Instruction code 1 1 0 0 0 0 1 1 Byte 1...
  • Page 281 MSM80C154S/83C154S/85C154HVS 25. CLR bit address (Clear bit) Instruction code Byte 1 Bit address Byte 2 Operation (bit address) 0 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified bit address content is cleared to 0. Example CLR P1.5 Instruction code 1 0 0 0 0 0 1 0...
  • Page 282 DESCRIPTION OF INSTRUCTIONS 26. CPL A (Complement accumulator) Instruction code Byte 1 Operation (A) (A) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Accumulator data 0 is set to 1 and 1 is set to 0. Example CPL A Instruction code 1 1 1 1 0 1 0 0...
  • Page 283 MSM80C154S/83C154S/85C154HVS 27. CPL C (Complement carry flag) Instruction code Byte 1 Operation (C) (C) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The carry flag is set to 1 if 0, set to 0 if 1. Example CPL C Instruction code 1 0 1 1 0 0 1 1...
  • Page 284 DESCRIPTION OF INSTRUCTIONS 28. CPL bit address (Complement bit) Instruction code Byte 1 Bit address Byte 2 (bit address) (bit address) Operation Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified bit address content is set to 1 if 0, and set to 0 if 1. Example CLR B.7 Instruction code 1 0 1 1 0 0 1 0...
  • Page 285 MSM80C154S/83C154S/85C154HVS 29. DA A (Decimal adjust accumulator) Instruction code Byte 1 Operations +6 (AC)=1 or 10 >10 (C)=1 or 10 >10 (C) 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • Description The arithmetic operation result located in the accumulator following an addition between two 2-digit decimal number is converted to a normal decimal number.
  • Page 286 DESCRIPTION OF INSTRUCTIONS Example DA A Instruction code 1 1 0 1 0 1 0 0 Byte 1 Before execution After execution Accumulator Accumulator 1 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 Before execution After execution Accumulator...
  • Page 287 MSM80C154S/83C154S/85C154HVS 30. DEC @Rr (Decrement indirect address) Instruction code Byte 1 Operation ((Rr)) ((Rr))–1 r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The contents of the data memory location addressed by the register r contents are decremented by 1.
  • Page 288 DESCRIPTION OF INSTRUCTIONS 31. DEC A (Decrement accumulator) Instruction code Byte 1 Operation (A) (A)–1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The accumulator contents are decremented by 1, and the flag is updated.
  • Page 289 MSM80C154S/83C154S/85C154HVS 32. DEC Rr (Decrement register) Instruction code Byte 1 Operation (Rr) (Rr)–1 r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The register r contents are decremented by 1. Example DEC R7 Instruction code 0 0 0 1 1 1 1 1 Byte 1...
  • Page 290 DESCRIPTION OF INSTRUCTIONS 33. DEC data address (Decrement memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (data address)–1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified data address contents are decremented by 1. Example DEC 5AH Instruction code 0 0 0 1 0 1 0 1...
  • Page 291 MSM80C154S/83C154S/85C154HVS 34. DIV AB (Divide accumulator by B) Instruction code Byte 1 Operation (A) quotient (A)/(B) (B) remainder Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • Description The accumulator contents are devided by the contents of arithmetic operation register (B).
  • Page 292 DESCRIPTION OF INSTRUCTIONS 35. DJNZ Rr, code address (Decrement register, and jump if not zero) Instruction code Byte 1 Relative offset Byte 2 Operations (PC) (PC)+2 (Rr) (Rr)–1 r=0 thru 7 IF (Rr) 0 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV...
  • Page 293 MSM80C154S/83C154S/85C154HVS Example DJNZ R1, LOOP SOURCE 00FE LOOP:ADD A, R7 010B D9F1 COUNT:DJNZ R1, LOOP Instruction code 1 1 0 1 1 0 0 1 Byte 1 1 1 1 1 0 0 0 1 Byte 2 Before execution After execution Register 1 Register 1 0 0 0 0 1 0 0 0...
  • Page 294 DESCRIPTION OF INSTRUCTIONS 36. DJNZ data address, code address (Decrement memory, and jump if not zero) Instruction code Byte 1 Data address Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 (data address) (data address)–1 IF (data address) 0 THEN (PC) (PC)+relative offset Number of bytes Number of cycles...
  • Page 295 MSM80C154S/83C154S/85C154HVS Example DJNZ 57H, LOOP 1 SOURCE 1033 A957 LOOP 1:MOV R1, 57H 1095 D5579B COUNT:DJNZ 57H, LOOP 1 Instruction code 1 1 0 1 0 1 0 1 Byte 1 0 1 0 1 0 1 1 1 Byte 2 1 0 0 1 1 0 1 1 Byte 3 Before execution...
  • Page 296 DESCRIPTION OF INSTRUCTIONS 37. INC @Rr (Increment indirect address) Instruction code Byte 1 Operation ((Rr)) ((Rr))+1 r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The contents of the data memory location addressed by the register r contents are incremented by 1.
  • Page 297 MSM80C154S/83C154S/85C154HVS 38. INC A (Increment accumulator) Instruction code Byte 1 Operation (A) (A)+1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The accumulator contents are incremented by 1, and the flag is updated. Example INC A Instruction code 0 0 0 0 0 1 0 0 Byte 1...
  • Page 298 DESCRIPTION OF INSTRUCTIONS 39. INC DPTR (Increment data pointer) Instruction code Byte 1 Operation (DPTR) (DPTR)+1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description 16-bit contents od the data pointer (DPH·DPL) are incremented by 1. Example INC DPTR Instruction code 1 0 1 0 0 0 1 1...
  • Page 299 MSM80C154S/83C154S/85C154HVS 40. INC Rr (Increment register) Instruction code Byte 1 Operation (Rr) (Rr)+1 r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The register r contents are incremented by 1. Example INC R5 Instruction code 0 0 0 0 1 1 0 1 Byte 1...
  • Page 300 DESCRIPTION OF INSTRUCTIONS 41. INC data address (Increment memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (data address)+1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified data address contents are incremented by 1. Example INC P1 Instruction code 0 0 0 0 0 1 0 1...
  • Page 301 MSM80C154S/83C154S/85C154HVS 42. JB bit address, code address (Jump if bit is set) Instruction code Byte 1 Bit address Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF (bit address)=1 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW)
  • Page 302 DESCRIPTION OF INSTRUCTIONS Example JB 34.3, ENTER SOURCE 0903 20134A BITTS:JB 34.3, ENTER 0950 ACA0 ENTER:MOV R4, 0A0H Instruction code 0 0 1 0 0 0 0 0 Byte 1 0 0 0 1 0 0 1 1 Byte 2 0 1 0 0 1 0 1 0 Byte 3 Before execution...
  • Page 303 MSM80C154S/83C154S/85C154HVS 43. JBC bit address, code address (Jump and clear if bit is set) Instruction code Byte 1 Bit address Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF (bit address)=1 THEN (bit address) 0 (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV...
  • Page 304 DESCRIPTION OF INSTRUCTIONS Example JBC 46.1, COUNT 4 SOURCE 00DC C281 COUNT 4:CLR 128.1 0136 1071A3 BTEST:JBC46.1, COUNT 4 Instruction code 0 0 0 1 0 0 0 0 Byte 1 0 1 1 1 0 0 0 1 Byte 2 1 0 1 0 0 0 1 1 Byte 3 Before execution...
  • Page 305 MSM80C154S/83C154S/85C154HVS 44. JC code address (Jump if carry is set) Instruction code Byte 1 Relative offset Byte 2 Operations (PC) (PC)+2 IF (C)=1 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Control is shifted to a relative jump address if the carry flag is 1.
  • Page 306 DESCRIPTION OF INSTRUCTIONS Example JC CARRY SOURCE 16DC 7110 CHECK:ACALL ADDR 16DE 4015 JMPC:JC CARRY 16F5 CARRY:INC @R1 Instruction code 0 1 0 0 0 0 0 0 Byte 1 0 0 0 1 0 1 0 1 Byte 2 Before execution After execution Carry flag...
  • Page 307 MSM80C154S/83C154S/85C154HVS 45. JMP @A + DPTR (Jump to sum of accumulator and data pointer) Instruction code Byte 1 Operation (PC) (A)+(DPTR) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The accumulator contents are added to the data pointer con- tents, and the resulting sum is placed in the program counter.
  • Page 308 DESCRIPTION OF INSTRUCTIONS 46. JNB bit address, code address (Jump if bit is not set) Instruction code Byte 1 Bit address Byte 2 Relative offset Byte 3 Operations (PC) (PC)+3 IF (bit address)=0 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV...
  • Page 309 MSM80C154S/83C154S/85C154HVS Example JNB 37.3, EXIT SOURCE 0835 302B22 TEST:JNB 37.3, EXIT 085A EXIT:MOV A, @R0 Instruction code 0 0 1 1 0 0 0 0 Byte 1 0 0 1 0 1 0 1 1 Byte 2 0 0 1 0 0 0 1 0 Byte 3 Before execution After execution...
  • Page 310 DESCRIPTION OF INSTRUCTIONS 47. JNC code address (Jump if carry is not set) Instruction code Byte 1 Relative offset Byte 2 Operations (PC) (PC)+2 IF (C)=0 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Control is shifted to a relative jump address if the carry flag is 0.
  • Page 311 MSM80C154S/83C154S/85C154HVS Example JNC EXIT SOURCE 0835 5022 TEST:JNC EXIT 0859 85E0F0 EXIT:MOV B, ACC Instruction code 0 1 0 1 0 0 0 0 Byte 1 0 0 1 0 0 0 1 0 Byte 2 Before execution After execution Carry flag Carry flag Program counter...
  • Page 312 DESCRIPTION OF INSTRUCTIONS 48. JNZ code address (Jump if accumulator is not 0) Instruction code Byte 1 Relative offset Byte 2 Operations (PC) (PC)+2 IF (A) 0 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Control is shifted to a relative jump address if the accumulator...
  • Page 313 MSM80C154S/83C154S/85C154HVS Example JNZ TEST SOURCE 00FC 7030 CHECK:JNZ TEST 012E TEST:MOV R3, A Instruction code 0 1 1 1 0 0 0 0 Byte 1 0 0 1 1 0 0 0 0 Byte 2 Before execution After execution Accumulator Accumulator 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1...
  • Page 314 DESCRIPTION OF INSTRUCTIONS 49. JZ code address (Jump if accumulator is not 0) Instruction code Byte 1 Relative offset Byte 2 Operations (PC) (PC)+2 IF (A)=0 THEN (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Control is shifted to a relative jump address if the accumulator...
  • Page 315 MSM80C154S/83C154S/85C154HVS Example JZ EMPTY SOURCE 0099 EMPTY:INC A 00CA 60CD CHECK:JZ EMPTY Instruction code 0 1 1 0 0 0 0 0 Byte 1 1 1 0 0 1 1 0 1 Byte 2 Before execution After execution Accumulator Accumulator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Program counter...
  • Page 316 DESCRIPTION OF INSTRUCTIONS 50. LCALL code address (Long call) Instruction code Byte 1 Call address Byte 2 Call address Byte 3 Operations (PC) (PC)+3 (SP) (SP)+1 ((SP)) (PC (SP) (SP)+1 ((SP)) (PC 8~15 0~15 0~15 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW)
  • Page 317 MSM80C154S/83C154S/85C154HVS 51. LJMP code address (Long jump) Instruction code Byte 1 Jump address Byte 2 Jump address Byte 3 Operation 0~15 0~15 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Jump address A specified by operand are placed in the 0~15 program counter PC 0~15...
  • Page 318 DESCRIPTION OF INSTRUCTIONS 52. MOV @Rr, #data (Move immediate data to indirect address) Instruction code Byte 1 Data address Byte 2 Operation ((Rr)) #data r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description An 8-bit immediate data value is copied to the data memory location addressed by the register r contents.
  • Page 319 MSM80C154S/83C154S/85C154HVS 53. MOV @Rr, A (Move accumulator to indirect address) Instruction code Byte 1 Operation ((Rr)) (A) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The accumulator contents are copied to the data memory location addressed by the register r contents.
  • Page 320 DESCRIPTION OF INSTRUCTIONS 54. MOV @Rr, data address (Move memory to indirect address) Instruction code Byte 1 Data address Byte 2 Operation ((Rr)) (data address) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified data address contents are copied to the data memory location addressed by the register r contents.
  • Page 321 MSM80C154S/83C154S/85C154HVS 55. MOV A, #data (Move immediate data to accumulator) Instruction code Byte 1 #data Byte 2 Operation (A) #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description An 8-bit immediate data is copied to the accumulator, and the flag is updated.
  • Page 322 DESCRIPTION OF INSTRUCTIONS 56. MOV A, @Rr (Move indirect address to accumulator) Instruction code Byte 1 Operation (A) ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The data memory location contents addressed by the register r contents are copied to the accumulator, and the flag is updated.
  • Page 323 MSM80C154S/83C154S/85C154HVS 57. MOV A, Rr (Move register to accumulator) Instruction code Byte 1 Operation (A) (Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The register r contents are copied to the accumulator, and the flag is updated.
  • Page 324 DESCRIPTION OF INSTRUCTIONS 58. MOV A, data address (Move memory to accumulator) Instruction code Byte 1 Data address Byte 2 Operation (A) (data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The specified data address contents are copied to the accumu- lator, and the flag is updated.
  • Page 325 MSM80C154S/83C154S/85C154HVS 59. MOV C, bit address (Move bit to carry flag) Instruction code Byte 1 Bit address Byte 2 Operation (C) (bit address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The specified bit address content is copied to the carry flag. Example MOV C, P3.4 Instruction code 1 0 1 0 0 0 1 0...
  • Page 326 DESCRIPTION OF INSTRUCTIONS 60. MOV DPTR, #data (Move immediate data to data pointer) Instruction code Byte 1 #data Byte 2 #data Byte 3 Operation (DPTR) #data (DPH) I 8~15 (DPL) I Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description A 16-bit immediate data value is copied to the data pointer...
  • Page 327 MSM80C154S/83C154S/85C154HVS 61. MOV Rr, #data (Move immediate data to register) Instruction code Byte 1 #data Byte 2 Operation (Rr) #data r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description An 8-bit immediate data value is copied to the register r. Example MOV R5, #0AH Instruction code 0 1 1 1 1 1 0 1...
  • Page 328 DESCRIPTION OF INSTRUCTIONS 62. MOV Rr, A (Move accumulator to register) Instruction code Byte 1 Operation (Rr) (A) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The accumulator contents are copied to the register r. Example MOV R1, A Instruction code 1 1 1 1 1 0 0 1...
  • Page 329 MSM80C154S/83C154S/85C154HVS 63. MOV Rr, data address (Move memory to register) Instruction code Byte 1 Data address Byte 2 Operation (Rr) (data address) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified data address contents are copied to the register r. Example MOV R0, 5AH Instruction code 1 0 1 0 1 0 0 0...
  • Page 330 DESCRIPTION OF INSTRUCTIONS 64. MOV bit address, C (Move carry flag to bit) Instruction code Byte 1 Bit address Byte 2 Operation (bit address) (C) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The carry flag content is copied to the specified bit address. Example MOV P1.4, C Instruction code 1 0 0 1 0 0 1 0...
  • Page 331 MSM80C154S/83C154S/85C154HVS 65. MOV data address, #data (Move immediate data to memory) Instruction code Byte 1 Data address Byte 2 #data Byte 3 Operation (data address) #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description An 8-bit immediate data value is copied to the specified data address.
  • Page 332 DESCRIPTION OF INSTRUCTIONS 66. MOV data address, @Rr (Move indirect address to memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The data memory location contents addressed by the register r contents are copied to the specified data address.
  • Page 333 MSM80C154S/83C154S/85C154HVS 67. MOV data address, A (Move accumulator to memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (A) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The accumulator contents are copied to the specified data address.
  • Page 334 DESCRIPTION OF INSTRUCTIONS 68. MOV data address, Rr (Move register to memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The register r contents are copied to the specified data address.
  • Page 335 MSM80C154S/83C154S/85C154HVS 69. MOV data address 1, data address 2 (Move memory to memory) Instruction code Byte 1 Data address 2 Byte 2 Data address 1 Byte 3 Operation (data address 1) (data address 2) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW)
  • Page 336 DESCRIPTION OF INSTRUCTIONS 70. MOVC A, @A + DPTR (Move code memory offset from data pointer to accumulator) Instruction code Byte 1 Operation (A) ((A)+(DPTR)) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The data pointer contents are added to the accumulator con- tents, and after temporary storage of the sum in the program counter, the ROM data contents specified by the program counter are stored in the accumulator.
  • Page 337 MSM80C154S/83C154S/85C154HVS 71. MOVC A, @A + PC (Move code memory offset from program counter to accumulator) Instruction code Byte 1 Operations (PC) (PC)+1 (A) ((A)+(PC)) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The program counter contents following an increment are added to the accumulator contents, and after temporary storage of the sum in the program counter, the ROM data contents specified by the program counter are stored in the accumulator.
  • Page 338 DESCRIPTION OF INSTRUCTIONS 72. MOVX @DPTR, A (Move accumulator to external memory addressed by data pointer) Instruction code Byte 1 Operation ((DPTR)) (A) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The accumulator contents are stored in external data memory (RAM) addressed by the data pointer contents.
  • Page 339 MSM80C154S/83C154S/85C154HVS 73. MOVX @Rr, A (Move accumulator to external memory addressed by register) Instruction code Byte 1 Operation ((Rr)) (A) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The accumulator contents are stored in external data memory addressed by the register r contents.
  • Page 340 DESCRIPTION OF INSTRUCTIONS 74. MOVX A, @DPTR (Move external memory addressed by data pointer to accumulator) Instruction code Byte 1 Operation (A) ((DPTR)) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description External data memory (RAM) contents addressed by the data pointer are stored in the accumulator, and the flag is updated.
  • Page 341 MSM80C154S/83C154S/85C154HVS 75. MOVX A, @Rr (Move external memory addressed by register to accumulator) Instruction code Byte 1 Operation (A) ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description External data memory (RAM) contents addressed by the register r contents are stored in the accumulator, and the flag is updated.
  • Page 342 DESCRIPTION OF INSTRUCTIONS 76. MUL AB (Multiply accumulator by B) Instruction code Byte 1 Operations 8~15 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • Description The accumulator contents are multiplied by the arithmetic operation register (B) contents.
  • Page 343 MSM80C154S/83C154S/85C154HVS 77. NOP (No operation) Instruction code Byte 1 Operation (PC) (PC)+1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The program counter is incremented by 1 without any other change in the CPU. Control is shifted to the next instruction.
  • Page 344 DESCRIPTION OF INSTRUCTIONS 78. ORL A, #data (Logical OR immediate data to accumulator) Instruction code Byte 1 #data Byte 2 Operation (A) (A) OR #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical OR between an 8-bit immediate data value and the accumulator contents is determined.
  • Page 345 MSM80C154S/83C154S/85C154HVS 79. ORL A, @Rr (Logical OR indirect address to accumulator) Instruction code Byte 1 Operation (A) (A) OR ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical OR between the accumulator contents and the data memory location contents addressed by the register r contents is determined.
  • Page 346 DESCRIPTION OF INSTRUCTIONS 80. ORL A, Rr (Logical OR register to accumulator) Instruction code Byte 1 Operation (A) (A) OR (Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical OR between the accumulator contents and the register r contents is determined.
  • Page 347 MSM80C154S/83C154S/85C154HVS 81. ORL A, data address (Logical OR memory to accumulator) Instruction code Byte 1 Data address Byte 2 Operation (A) (A) OR (data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical OR between the accumulator contents and the specified data address contents is determined.
  • Page 348 DESCRIPTION OF INSTRUCTIONS 82. ORL C, bit address (Logical OR bit to carry flag) Instruction code Byte 1 Bit address Byte 2 Operation (C) (C) OR (bit address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) •...
  • Page 349 MSM80C154S/83C154S/85C154HVS 83. ORL C,/bit address (Logical OR complement of bit to carry flag) Instruction code Byte 1 Bit address Byte 2 (C) (C) OR (bit address) Operation Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The logical OR between the carry flag and the complement of specified bit address content is determined.
  • Page 350 DESCRIPTION OF INSTRUCTIONS 84. ORL data address, #data (Logical OR immediate data to memory) Instruction code Byte 1 Data address Byte 2 #data Byte 3 Operation (data address) (data address) OR #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The logical OR between an 8-bit immediate data value and the...
  • Page 351 MSM80C154S/83C154S/85C154HVS 85. ORL data address, A (Logical OR accumulator to memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (data address) OR (A) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The logical OR between the accumulator and the specified data address contents is determined.
  • Page 352 DESCRIPTION OF INSTRUCTIONS 86. POP data address (Pop stack to memory) Instruction code Byte 1 Data address Byte 2 Operations (data address) ((SP)) (SP) (SP)–1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Stack contents addressed by the stack pointer are popped in the specified data address, and the stack pointer is decremented by 1.
  • Page 353 MSM80C154S/83C154S/85C154HVS 87. PUSH data address (Push memory onto stack) Instruction code Byte 1 Data address Byte 2 Operations (SP) (SP)+1 ((SP)) (data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The stack pointer is incremented by 1, and the specified data address contents are pushed in the stack addressed by the stack pointer.
  • Page 354 DESCRIPTION OF INSTRUCTIONS 88. RET (Return from subroutine, non interrupt) Instruction code Byte 1 Operations ) ((SP)) 8~15 (SP) (SP)–1 ) ((SP)) (SP) (SP)–1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The stack contents addressed by the stack pointer are popped in the upper order 8 thru 15 of the program counter, and the stack pointer is decremented by 1.
  • Page 355 MSM80C154S/83C154S/85C154HVS 89. RETI (Return from interrupt routine) Instruction code Byte 1 Operations ) ((SP)) 8~15 (SP) (SP)–1 ) ((SP)) (SP) (SP)–1 *INTERRUPT ENABLE Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description This return instruction functions as an interrupt routine terminat- ing instruction.
  • Page 356 DESCRIPTION OF INSTRUCTIONS 90. RL A (Rotate accumulator left) Instruction code Byte 1 Operation Accumulator Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description All accumulator bits are shifted by one bit to the left. The MSB (bit 7) is shifted to the LSB bit position (bit 0).
  • Page 357 MSM80C154S/83C154S/85C154HVS 91. RLC A (Rotate accumulator and carry flag left) Instruction code Byte 1 Operation Carry Accumulator Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • Description The accumulator and the carry flag are connected, and all bits are shifted by one bit to the left.
  • Page 358 DESCRIPTION OF INSTRUCTIONS 92. RR A (Rotate accumulator right) Instruction code Byte 1 Operation Accumulator Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description All accumulator bits are shifted by one bit to the right. The LSB (bit 0) is shifted to the MSB bit position (bit 7).
  • Page 359 MSM80C154S/83C154S/85C154HVS 93. RRC A (Rotate accumulator and carry flag right) Instruction code Byte 1 Operation Carry Accumulator Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • Description The accumulator and the carry flag are connected, and all bits are shifted by one bit to the right.
  • Page 360 DESCRIPTION OF INSTRUCTIONS 94. SETB C (Set carry flag) Instruction code Byte 1 Operation (C) 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The carry flag is cleared to 1. Example SETB C Instruction code 1 1 0 1 0 0 1 1 Byte 1...
  • Page 361 MSM80C154S/83C154S/85C154HVS 95. SETB bit address (Set bit) Instruction code Byte 1 Bit address Byte 2 Operation (bit address) 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The specified bit address content is set to 1. Example SETB IE.7 Instruction code 1 1 0 1 0 0 1 0...
  • Page 362 DESCRIPTION OF INSTRUCTIONS 96. SJMP code address (Short jump) Instruction code Byte 1 Relative offset Byte 2 Operations (PC) (PC)+2 (PC) (PC)+relative offset Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description Relative offset jump data is added/subtracted to/from the program counter contents following an increment.
  • Page 363 MSM80C154S/83C154S/85C154HVS Example SJMP CHECK SOURCE 0111 8010 SJUMP:SJMP CHECK 0123 CHECK:RLC A Instruction code 1 0 0 0 0 0 0 0 Byte 1 0 0 0 1 0 0 0 0 Byte 2 Before execution After execution Program counter Program counter 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1...
  • Page 364 DESCRIPTION OF INSTRUCTIONS 97. SUBB A, #data (Substract immediate data from accumulator with borrow) Instruction code Byte 1 #data Byte 2 Operation (A) (A)–((C)+#data) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag content and an immediate data value are substracted from the accumulator contents.
  • Page 365 MSM80C154S/83C154S/85C154HVS 98. SUBB A, @Rr (Substract indirect address from accumulator with borrow) Instruction code Byte 1 Operation (A) (A)–((C)+((Rr))) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag content and the data memory location contents addressed by the register r contents are substracted from the accumulator contents.
  • Page 366 DESCRIPTION OF INSTRUCTIONS 99. SUBB A, Rr (Substract register from accumulator with borrow) Instruction code Byte 1 Operation (A) (A)–((C)+(Rr)) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag content and the register r contents are substracted from the accumulator contents.
  • Page 367 MSM80C154S/83C154S/85C154HVS 100. SUBB A, data address (Substract memory from accumulator with borrow) Instruction code Byte 1 Data address Byte 2 Operation (A) (A)–((C)+(data address)) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • • • • Description The carry flag contents and the specified data address contents are substracted from the accumulator contents.
  • Page 368 DESCRIPTION OF INSTRUCTIONS 101. SWAP A (Exchange nibble in accumulator) Instruction code Byte 1 Operation ) (A Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The contents of the four higher order bits (4 thru 7) of the accumulator are exchanged with the contents of the four lower order bits (0 thru 3) Example SWAP A...
  • Page 369 MSM80C154S/83C154S/85C154HVS 102. XCH A, @Rr (Exchange indirect address with accumulator) Instruction code Byte 1 Operation (A) ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The accumulator contents are exchanged with the data memory location contents addressed by the register r, and the flag is updated.
  • Page 370 DESCRIPTION OF INSTRUCTIONS 103. XCH A, Rr (Exchange register with accumulator) Instruction code Byte 1 Operation (A) (Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The accumulator contents are exchanged with the register r contents, and the flag is updated.
  • Page 371 MSM80C154S/83C154S/85C154HVS 104. XCH A, data address (Exchange memory with accumulator) Instruction code Byte 1 Data address Byte 2 Operation (A) (data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The accumulator contents are exchanged with the specified data address contents, and the flag is updated.
  • Page 372 DESCRIPTION OF INSTRUCTIONS 105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator) Instruction code Byte 1 Operation ) ((Rr )) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The lower order bits (0 thru 3) of the accumulator contents are exchanged with contents of the lower order bits (0 thru 3) of the data memory location addressed by the register r contents.
  • Page 373 MSM80C154S/83C154S/85C154HVS 106. XRL A, #data (Logical exclusive OR immediate data to accumulator) Instruction code Byte 1 #data Byte 2 Operation (A) (A) XOR #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The exclusive OR operation is executed between an immediate data value and the accumulator contents.
  • Page 374 DESCRIPTION OF INSTRUCTIONS 107. XRL A, @Rr (Logical exclusive OR indirect address to accumulator) Instruction code Byte 1 Operation (A) (A) XOR ((Rr)) r=0 or 1 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The exclusive OR operation is executed between the accumulator contents and the data memory location contents addressed by the register r contents.
  • Page 375 MSM80C154S/83C154S/85C154HVS 108. XRL A, Rr (Logical exclusive OR register to accumulator) Instruction code Byte 1 Operation (A) (A) XOR (Rr) r=0 thru 7 Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) • Description The exclusive OR between the accumulator contents and the register r contents is determined.
  • Page 376 DESCRIPTION OF INSTRUCTIONS 109. XRL A, data address (Logical exclusive OR memory to accumulator) Instruction code Byte 1 Data address Byte 2 Operation (A) (A) XOR (data address) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) •...
  • Page 377 MSM80C154S/83C154S/85C154HVS 110. XRL data address, #data (Logical exclusive OR immediate data to memory) Instruction code Byte 1 Data address Byte 2 #data Byte 3 Operation (data address) (data address) XOR #data Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) Description The exclusive OR between an immediate data value and the...
  • Page 378 DESCRIPTION OF INSTRUCTIONS 111. XRL data address, A (Logical exclusive OR accumulator to memory) Instruction code Byte 1 Data address Byte 2 Operation (data address) (data address) XOR (A) Number of bytes Number of cycles Flags F0 RS1 RS0 OV (PSW) •...

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