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Endura KP915GV Product Manual

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Endura KP915GV
Product Manual
w w w . r a d i s y s . c o m
007-01542-0001 December 2005

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  • Page 1 Endura KP915GV Product Manual w w w . r a d i s y s . c o m 007-01542-0001 December 2005...
  • Page 2 KP915GV Product Manual Copyright © 2005 by RadiSys Technology (Ireland) Ltd. All rights reserved. EPC and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ, MultiPro, SAIB, Spirit, and ValuePro are trademarks of RadiSys Corporation. DAVID, MAUI, OS-9, OS-9000, and SoftStax are registered trademarks of RadiSys Microware Communications Software Division, Inc.
  • Page 3 KP915GV Product Manual Preface Revision History Revision history Date Description September 2005 • First Release December 2005 • Updates to clarify jumper default positioning, non-support for S/PDIF In and Out on board, BIOS update to P28 version, and editorial changes to some tables. Added details to OEM Features section.
  • Page 4 KP915GV Product Manual Safety and Approval Notices Safety and approval notices Item Description This product contains a lithium cell. Battery • When removing or replacing the lithium cell, do not use a conductive instrument as a short-circuit may cause the cell to explode.

  • Page 5: Table Of Contents

    KP915GV Product Manual Contents OVERVIEW ........................ 10 Accessories ………………………………………………………………………………………….. 11 Motherboard Layout ........................12 Block Diagram.........................14 Configuration ………………………………………………………………………………………….15 1.4.1 Operation Mode Selection Jumper (JP3) ................15 1.4.2 BIOS Boot Block Write Protection Jumper (JP2)..............16 1.4.3 Clear CMOS Jumper (JP1) .....................16 1.4.4 Front Panel Connections......................16 1.4.5 Alternate Power LED.......................17...
  • Page 6 KP915GV Product Manual MOTHERBOARD BIOS ..................... 51 BIOS Features ........................51 Post and Boot ………………………………………………………………………………………..51 4.2.1 Hotkeys ...........................52 Setup Utility ………………………………………………………………………………………….. 52 4.3.1 Enter Setup ..........................52 4.3.2 Configuration Reset ........................52 4.3.3 Keyboard Command .......................52 4.3.4 Setup Configuration ........................53 Power Management ........................93 4.4.1 ACPI Wake-up Support......................93...
  • Page 7 KP915GV Product Manual CONTROL REGISTERS ..................111 Index Register ........................111 Watchdog Control ......................... 111 Watchdog Kick ........................112 Watchdog Status........................112 Watchdog Timeout Period.....................113 General Purpose I/O Port 1....................113 General Purpose I/O Port 2 and Control ................113 PWM Control ………………………………………………………………………………………..114 Processor Identification......................
  • Page 8 KP915GV Product Manual Figures Figure 1. KP915GV Board Layout.....................12 Figure 2. KP915GV Block diagram ...................14 Figure 3. Jumpers ........................15 Figure 4. Clocking Block Diagram .....................25 Figure 5. KP915GV Board Slot Layout..................28 Figure 6. Audio Jack Socket and ATAPI Connectors ..............29 Figure 7.
  • Page 9 KP915GV Product Manual Table 34. Complex Programmable Logic Device (CPLD) JTAG Header ........124 Table 35. Serial Port 2 Header ....................124 Table 36. 4 X Internal USB Headers ...................124 Table 37. Remote Thermal Sensor....................125 Table 38. 3 X Fan Connector.......................125 Table 39. SMBus Connector......................125 Table 40.

  • Page 10: Overview

    This motherboard is part of the RadiSys Endura product line, which is specifically targeted at embedded applications with a lifetime of 5 years. Products are fully revision controlled and any change to form, fit or function will be notified to...

  • Page 11: Accessories

    KP915GV Product Manual Product Specification Overview Item Description Intel 82573V (or ‘L) PCI-E Gbit Ethernet controller, co-lay with Intel 82562GZ Network 10/100 PHY (using the integrated MAC) Available with second Intel 82573V (or ‘L) Gbit Ethernet controller Four SATA ports with locking headers...

  • Page 12: Motherboard Layout

    KP915GV Product Manual Motherboard Layout Figure 1 shows the layout of the KP915GV motherboard with the major components identified. Figure 1. KP915GV Board Layout (Optional) 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 30...
  • Page 13 KP915GV Product Manual Component Identification Description Description Description Ethernet port 1 Super IO USB port 2 header (option) Memory sockets I/O panel USB port 7 USB port 3 header Serial port 2 header I/O panel USB port 8 USB port 4 header...

  • Page 14: Block Diagram

    KP915GV Product Manual Block Diagram Figure 2 shows the block diagram of the KP915GV motherboard. Figure 2. KP915GV Block diagram Prescott, Tejas VRD 10.1 Pentium 4 EE 4 Phase PWM LGA775 processor Socket T CK-410 Clock 800/533 FSB Channel A DDR-2...

  • Page 15: Configuration

    KP915GV Product Manual Configuration The majority of the configuration of the motherboard is done through the Setup utility built into the BIOS – discussed later in this document. There are, however, a number of jumpers that control the operation of the motherboard as described below. Some jumpers are not fitted to certain products.

  • Page 16: Bios Boot Block Write Protection Jumper (Jp2)

    KP915GV Product Manual Recover Mode (No jumper) With no jumper installed on pins 1, 3, and 5 recovery mode is entered. The motherboard does not boot and waits until a valid recovery diskette is detected and then copies new BIOS into the ROM. The motherboard must be powered down and then re-powered with the jumper in the normal position before normal operation can resume.

  • Page 17: Alternate Power Led

    KP915GV Product Manual Tamper Switch To make use of the tamper detection logic of the motherboard, connect a momentary switch between pins 18 and 20. The switch should be open when the chassis is closed. 1.4.5 Alternate Power LED The power LED function on the front panel connector is duplicated on the Alternate Power LED connector for use with LEDs cabled to a 3-pin connector.
  • Page 18 KP915GV Product Manual 3. Use thumb & forefinger to hold the hook of the load lever and pull the lever sideways to unlock it. Correct Wrong Warning: DO NOT use finger to lift the locking lever, as injury could occur to the finger and the SKT could be damaged.
  • Page 19 KP915GV Product Manual Alignment key Pin 1 indicator...
  • Page 20 KP915GV Product Manual Close the load plate, and slightly push down the tongue side. Slightly push down the tongue side 7. Lower the lever and lock it to the load plate, then the CPU is locked in place CAUTION Excessive temperatures will severely damage the CPU and system. Therefore, you should install CPU cooling fan and make sure that the cooling fan works normally at all times in order to prevent overheating and damaging to the CPU.
  • Page 21 KP915GV Product Manual DDR2 Memory bank 128 Pins 112 Pins 3. The plastic clips at both sides of the DIMM slot will lock automatically. CAUTION Be sure to unplug the AC power supply before adding or removing expansion cards or other system peripherals, especially the memory devices, otherwise the motherboard or the system memory might be seriously damaged.
  • Page 22 KP915GV Product Manual 1.5.3 Power Supply In order to avoid damaging any devices, make sure that they have been installed properly prior to connecting the power supply. It is recommended that the board be used with a power supply that supports a minimum current load of 0.3A or less on the 5V supply rail and 2A or less on the 3.3V supply rail.
  • Page 23 KP915GV Product Manual KP915GV 20-pin ATX power connector: Below is the ATX power supply connector. Make sure that the power supply cable and pins are properly aligned with the connector on the motherboard. Firmly plug the power supply cable into...

  • Page 24: Motherboard Description

    KP915GV Product Manual Motherboard Description Processor Support • Single processor support • Intel® Pentium® 4 Processor 550/551 (3.4GHz 800MHz FSB 1MB L2) • Intel® Celeron™ D Processor 340/341 (2.93GHz 533MHz FSB 256Kb L2) • Follow the Design Guide in the Intel(R) Pentium(R) 4 Processor in the 775-land Package on 90 nm Process EMTS REV.

  • Page 25: On Board Clocking Block Diagram

    KP915GV Product Manual On board Clocking Block Diagram 14.318MHz CPU 133/200 MHz Diff Pair MCH 133/200 MHz Diff Pair DDR 4 Slots 12 Diff Pair CLKs PCI Express 100 MHz Diff Pair PCI Express x16 SDVO Channel A DDR2 DOT 96 MHz Diff Pair...

  • Page 26: 915Gv Chipset Feature

    KP915GV Product Manual Table 1. KP915GV Motherboard Form PCI-E x16 PCI-E PCI Riser Chipset Factor or ADD2 Extension 915GV • See Figure 5 for slot configurations • ADD2 will be a green connector 915GV Chipset Feature The 915GV is a Memory Controller Hub (MCH) designed for use with the Prescott processors in desktop platforms.

  • Page 27: Video

    KP915GV Product Manual • Support for non-ECC memory, unbuffered DIMMs only, in 256MB, 512MB, 1GB, and 2GB sizes, which may be installed as single DIMMs if desired. If a total of 4GB of DIMMs is installed, the maximum available memory will be approximately 3.24GB, with the balance of the address space being consumed by other resources in the system.

  • Page 28: Disks

    KP915GV Product Manual Processor ADD2 PCI-E PCI-E Figure 5. KP915GV Board Slot Layout Disks • Four 150MB/s SATA ports with locking headers • One Ultra ATA/100 interface via on-board 40-way boxed header • 40/80-pin cable host-side detection or forced in BIOS •...

  • Page 29: Network

    KP915GV Product Manual External Internal Optional* ATAPI 1 Line in Line out ATAPI 3 Line out MIC in MIC in ATAPI 2 Figure 6. Audio Jack Socket and ATAPI Connectors Table 2: Audio Channel Allocation I/O panel jack Internal header...

  • Page 30: Power Management

    KP915GV Product Manual 2.11 • Four USB 2.0 ports on I/O panel via two dual stacked USB over RJ45 connectors • Four USB 2.0 ports on internal locking headers • Available with IEEE 1394b controller with support for 1394a •...

  • Page 31: Programmable Controller (Pld)

    KP915GV Product Manual 2.15 Programmable Controller (PLD) • Programmable logic device to support configurable system functions • Supports software-based updates (including field updates) • Supports customizable logic (by RadiSys, not user customizable) • Option of 128 or 256 macrocell device (256 for enhanced controller) •...

  • Page 32: Operating Systems Support

    KP915GV Product Manual • All configuration is automatic - no stopping on configuration change • Resources freed when unused 2.19 Operating Systems Support • Windows XP Professional SP2 • Embedded Windows XP Server SP2 • Red Hat Enterprise Linux 4.0 AS •...

  • Page 33: Reliability And Environmental

    KP915GV Product Manual 2.21 Reliability and Environmental Table 5. Environmental Specifications Characteristic State Value Temperature Operating C to +55 (ambient) Operation above +30° C reduces the maximum operational relative humidity. Operating ±5°C per minute gradient Storage C to +85 C, 5°C per minute maximum excursion gradient.

  • Page 34: Regulatory Compliance

    KP915GV Product Manual 2.22 Regulatory Compliance Table 6. Regulatory Testing* Characteristic State Value Operating Designed and tested to pass (not certified): To IEC 1000-4-2 / EN61000-4-2: 1995 4kV direct contact, performance criteria B 6kV direct contact, performance criteria C 4kV air discharge, performance criteria B...

  • Page 35: Specifications

    KP915GV Product Manual Specifications Product Basis This product based on the Intel® 915GV Express chipset, designed for the Intel® Pentium® 4 processor with Hyper-Threading (HT) Technology in the LGA775 package, and is flexible for specific customer needs. Non-Core Integrated Sub-systems 3.2.1...
  • Page 36 KP915GV Product Manual • PCI Express endpoint • Independent Bus Master logic for eight general purpose streams: Four input and four output • Support three external Codecs • Supports variable length stream slots • Supports multimedia channel, 32-bit sample depth, 192kHz sample rate output •...
  • Page 37 KP915GV Product Manual • Support for APM-based legacy power management for non-ACPID Desktop implementation • External Glue Integration • Integrated Pull-op, Pull down and Series Termination resistors on IDE, processor I/F • Integrated Pull-down and Series resistors on USB •...

  • Page 38: Flash Bios

    KP915GV Product Manual • 5V tolerant buffers on IDE, PCI, and Legacy signals • Integrated 1.5V Voltage Regulator (INTVR) for the Suspend and LAN wells • Firmware Hub I/F supports BIOS Memory size up to 8 MBytes • Low Pin Count (LPC) I/F •...

  • Page 39: Major Sub-Systems

    KP915GV Product Manual • Greater than 100 years Data Retention • Low Power Consumption • Active Read Current: 6 mA (typical) • Standby Current: 10 µA (typical) • Fast Sector-Erase/Byte-Program Operation • Sector-Erase Time: 18 ms (typical) • Block-Erase Time: 18 ms (typical) •...

  • Page 40: Figure 8. Sigmatel Stac9200 High Definition Block Diagram

    KP915GV Product Manual STAC9200 Block Diagram SPDIF SPDIF IN Pin47 PCM to Receiver SPDIF Pin48 SPDIF Stream/ Stream/ Channel Channel Select Select -6dB MONO_OUT Digital +0dB Pin 37 PC Beep mute Pin5 Stream/ BIT_CLK Stream/ Channel Pin6 Channel Port A...

  • Page 41: Hardware Management Interface

    KP915GV Product Manual • Package 48-pin Lead Free LQFP 3.3.2 Hardware Management Interface The LM96000, hardware monitor, has a two wire digital interface compatible with SMBus 2.0. Using an 8-bit Σ∆ ADC, the LM96000 measures: • The temperature of two remote diode connected transistors as well as its own die •...

  • Page 42: Ethernet Interface

    KP915GV Product Manual • XOR-tree test mode • Package 24-pin Lead TSSOP 3.3.3 Ethernet Interface Either one or two IEEE 802.3 compatible Ethernet ports are available as build options that are based around Intel controllers (82562GZ and 82573V or ‘L) to provide 10/100Mbps and/or 10/100/1000Mbps configuration.

  • Page 43: Super I/O Interface

    KP915GV Product Manual • Support ASF1.0 and 2.0 alerting • Support Wake On LAN (WOL) and ACPI • Programmable LED functionality • On-chip power control circuitry • Loop-back capabilities • IEEE 802.3ab Auto-Negotiation support and PHY compliance with compatibility •...
  • Page 44 KP915GV Product Manual • Heceta6-compatible register set accessible via the LPC interface and SMBus • Supports the following combinations of LMxx devices: • LM41 and optional LM30 • LM32 • LM40 • Simultaneous read support via LPC interface and SMBus •...
  • Page 45 KP915GV Product Manual • Lock option for the configuration and data of each output pin • 15 GPIO ports generate IRQ/SMI/SIOPME# for wake-up events; each GPIO has separate: • Enable control of event status routing to IRQ • Enable control of event status routing to SMI •...
  • Page 46 KP915GV Product Manual • Supports programmable 8-byte sequence “Password” or “Special Keys” for Power Management • Simultaneous recognition of three programmable keys (sequences): “Power”, “Sleep” and “Resume” • Wake-up on mouse movement and/or button click 3.3.4.5 Bus Interface • LPC Bus Interface •...
  • Page 47 KP915GV Product Manual • Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS • IEEE 1284-compliant Parallel Port • ECP, with Level 2 (14 mA sink and source output buffers) • Software or hardware control • Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9 •...

  • Page 48: Motherboard Power Consumption

    KP915GV Product Manual • On-chip Clock Generator: • Generates 48 MHz clock • Generates 32.768 KHz internal clock • VSB3 powered • Based on the 14.31818 MHz clock input • Protection • All pins are 5V tolerant and back-drive protected (except LPC bus pins) •...
  • Page 49 KP915GV Product Manual KP915GV Item Description Power Supply FSP350-60PLN/350W Current Meter PROVA CM-01 AC/DC Clamp Meter Drives Powered independently Hard Drive Disk WD Caviar SE 1200/120GB Serial ATA Disk Network On-board (single LAN, not operating) Configuration 1 : Heavy Load...
  • Page 50 KP915GV Product Manual Configuration 2 : Light Load Item Description Memory Micron MT8HF3264AY-40EB3 256MB DDR2-400 CL3 X1 Video On-board (8MB shared Memory) Network On-board (single LAN, not operating) Intel Celeron 4 at 2.93GHz with 533MHz Processor Bus Motherboard Current (A)

  • Page 51: Motherboard Bios

    KP915GV Product Manual Motherboard BIOS BIOS Features • Phoenix Award BIOS • Intel® Pentium® 4 "Prescott" processor in an LGA775 socket with an 800MHz or 533MHz FSB and microcode patch • Intel 915GV chipset initialization modules and Intel memory sizing reference code •...

  • Page 52: Hotkeys

    KP915GV Product Manual and test progress messages are visible. Pressing the 'TAB' key on the keyboard during a Quietboot switches the display to text mode - providing the progress messages. The BIOS will then search for boot devices in the order configured by the BIOS Setup and load an operating system from the first boot device found.

  • Page 53: Setup Configuration

    KP915GV Product Manual 4.3.4 Setup Configuration 4.3.4.1 Standard CMOS Features...
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  • Page 57 KP915GV Product Manual Note: The Main BIOS level in the figure above is an example only and doesn’t necessarily reflect the latest BIOS on delivered products or available for downloading. 4.3.4.2 Advanced BIOS Features...
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  • Page 88 KP915GV Product Manual 4.3.4.8 Load Default Settings...
  • Page 89 KP915GV Product Manual 4.3.4.9 Set Supervisor Password...
  • Page 90 KP915GV Product Manual 4.3.4.10 Set User Password...
  • Page 91 KP915GV Product Manual 4.3.4.11 Save & Exit Setup...
  • Page 92 KP915GV Product Manual 4.3.4.12 Exit Without Saving...

  • Page 93: Power Management

    KP915GV Product Manual Power Management Supports APM and ACPI 2.0 with power states S0, S3, S4 (not S4BIOS), S5 and C0, C1, C2, C3. 4.4.1 ACPI Wake-up Support The next table indicates which events can cause an ACPI wake-up and from which sleep states.

  • Page 94: Cpld

    KP915GV Product Manual State Indicates Blinking The motherboard is in sleep state S1 with a message yellow waiting (as determined by ACPI TAPI). CPLD 4.7.1 POST Code Display Support for character-based LCD panel to display BIOS POST messages and other information.

  • Page 95: Normal Mode

    KP915GV Product Manual 4.9.1 Normal Mode This is the factory default position the jumper should be in for normal operation of the motherboard. 4.9.2 Configure Mode The Configure mode forces the BIOS into Setup with the manufacturer defaults loaded. The mode should be returned to normal before re-starting.

  • Page 96: Cmos Default Change

    KP915GV Product Manual NOTE The full-screen logo file must be 640X464 pixels with 16 colors BMP format. 4.12.2 CMOS Default Change The MODBIN6.EXE is the utility that runs at a DOS prompt for binary code manipulation. It allows selection of customized default CMOS (BIOS setup) settings.The process is described below: Execute the MODBIN6.exe...

  • Page 97: Bios Flash Usage Map

    KP915GV Product Manual 4.14 BIOS Flash Usage Map 4.15 Processor Microcode Support IA32 processors have the capability of correcting specific errata through the loading of an Intel- supplied data block (i.e. microcode update). Below table list the microcode that BIOS store in flash, and will load it into each processor during POST.
  • Page 98 KP915GV Product Manual Item SMBIOS Data Expected Result BIOS Vendor Phoenix Technologies, LTD BIOS Version 4C7R2BXX Type 00: BIOS Starting Addr Seg E000h Information BIOS Release Date MM/DD/YYYY BIOS ROM Size 512K Manufacturer ‘RadiSys‘ Product Name ‘Endura KP915GV‘ Version ‘ ‘...
  • Page 99 KP915GV Product Manual Item SMBIOS Data Expected Result System Cache Type Data Associativity Depend on CPU Socket Designation L2-Cache Cache Configuration Depend on CPU Maximum Cache Size Depend on CPU Installed Size Depend on CPU Supported SRAM Type Depend on CPU...
  • Page 100 KP915GV Product Manual Item SMBIOS Data Expected Result Slot Length: Other Slot ID: 0004 Slot Characteristics: Provides 3.3V Slot Characteristics 2: PME enable Location 03h(System board or motherboard) 03h(System Memory) Memory Error Correction 03h(None) Type 16 Physical Memory Capacity Depend on MEM...
  • Page 101 KP915GV Product Manual Item SMBIOS Data Expected Result Bank Locator Bank 4/5 Memory Type 0Fh(SDRAM) Type Detail 0080h(Synchronous) Memory Error Information Handle Unknown Total Width Depend on MEM Data Width Depend on MEM Size Depend on MEM Form Factor 09h(DIMM)

  • Page 102: Post Code Technical Description

    KP915GV Product Manual Item SMBIOS Data Expected Result Type 127: End-of- Table 4.17 Post Code Technical Description POST Code Description Test CMOS R/W functionality. Early chipset initialization: -Disable shadow RAM -Disable L2 cache (socket 7 or below) -Program basic chipset registers Detect memory -Auto-detection of DRAM size, type and ECC.
  • Page 103 KP915GV Product Manual POST Code Description Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead. Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of the ESCD’s legacy information.

  • Page 104: Post Beep

    KP915GV Product Manual POST Code Description Detect & install all IDE devices: HDD, LS120, ZIP, CDROM… Detect serial ports & parallel ports. Detect & install co-processor Switch back to text mode if full screen logo is supported. Call chipset power management hook. If password is set, ask for password.

  • Page 105: Customer Support

    KP915GV Product Manual Customer Support RadiSys Online Support can be found at www.radisys.com and includes device drivers, BIOS updates, support software and documentation. See the Manuals, Drivers & BIOS section. The next table displays online specifications and reference material: Table 7. References...

  • Page 106: Atechnical Reference

    KP915GV Product Manual Technical Reference I/O Map Table 8. I/O Map Address (hex)* Description 0000 – 000F DMA controller 1 0020 – 0021 Interrupt controller 1 002E – 002F SIO control registers 0040 – 0043 Timer counter 0060 – 0064...

  • Page 107: Pci Interrupt Allocation

    KP915GV Product Manual Table 8. I/O Map Address (hex)* Description 1300 – 133F AC97 audio master 1800 – 182F SIO GPIO and control logic FFA0 – FFA7 Primary IDE bus master registers FFA8 – FFAF Secondary IDE bus master registers...

  • Page 108: Pci Device Assignments

    KP915GV Product Manual PCI Device Assignments Table 10. PCI Device Assignments Device Device Function IDSEL Number Number Number Chipset host bridge and memory – controller AGP bridge – Graphics controller – PCI bridge – LPC bridge – (Includes DMA, timers, PIC, APIC, RTC, power &...

  • Page 109: Isa Interrupt Allocation

    KP915GV Product Manual ISA Interrupt Allocation While the motherboard does not include an ISA bus, it includes an ISA-compatible interrupt controller (PIC) in order to be compatible with AT standard architecture. The interrupts are allocated as described in the next table.

  • Page 110: Bios Organization

    KP915GV Product Manual BIOS Organization The BIOS ROM is a 4or 8Mbit device containing eight or sixteen symmetrical 64KB blocks. The next figure shows how the ROM stores code and control information. The addresses shown refer to the ROM image at the top of the 4GB-address space. Note that the system BIOS segment is compressed in this image.

  • Page 111: Bcontrol Registers

    KP915GV Product Manual Control Registers Notes • The following abbreviations are used in register descriptions: R=Read RO=Read only R/W=Read/Write W=Write only • The MSB (Most Significant Bit) is listed first. Index Register Version Index I/O location: 062h Default: vvvv 1010b Version A read-only field containing the software version number for the logic.

  • Page 112: Watchdog Kick

    KP915GV Product Manual Prescale 4-bit value to set the watchdog counter period 0..15 16..1s period (a value of 1010b gives a period of 6 seconds) Description Reset after second timeout: No reset Force system reset after second watchdog timeout Generate SMI after first timeout:...

  • Page 113: Watchdog Timeout Period

    KP915GV Product Manual Timer is enabled and counting Watchdog Timeout Period Watchdog timeout period I/O location: 066h Index Default: 11111111b Timeout period Do not use (causes immediate timeout) 1–255 Timeout period in units of 1 x prescale value seconds General Purpose I/O Port 1...

  • Page 114: Pwm Control

    KP915GV Product Manual These bits are input only. Writes to these bits have no effect; reads reflect the state of the GPIO port 2 bits 4 and 3 respectively. D104, GPIO Port 1 bits 0 – 4 direction control: GPIO bits 10 – 14 are inputs GPIO bits 10 –...

  • Page 115: Controller Part Number

    KP915GV Product Manual B.10 Controller Part Number The controller part number format is 97-xxyy-0v where v is version number (top 4 bits of index register), xx is the byte 2 value and yy is the byte 1 value. BCD encoding is used for all digits.

  • Page 116: Cconnector Descriptions

    KP915GV Product Manual Connector Descriptions Note 1 : Connector views in the following sections are shown from the motherboard side . Note 2 : In all tables below the # sign indicates “active low.” Connector Part Numbers The various motherboard connectors are listed in the next table along with the part number of one of the approved vendors.

  • Page 117: Pci-E Expansion Slot (Add2 Card Mode)

    KP915GV Product Manual Table 14. Connector part numbers Connector Part Number Type Front Panel Header Foxconn HC11101-L6 2 by 10-way header RS232 Serial Port2 Header Foxconn HL20051-D1 2 by 5-way shrouded header SATA Port 1 and Port 2 Foxconn LD1807V-S51B...

  • Page 118: Pci Expansion Slot

    KP915GV Product Manual Table 15. ADD2 Expansion Slot Signal Signal Signal Signal DVOCD11 DVOCD10 DVOBD5 DVOBD4 +3.3V +3.3V DVOCD9 DVOCD8 DVOBD3 DVOBD2 DVOCD7 DVOCD6 DVOBD1 DVOBD0 VDDQ1.5 VDDQ1.5 DVOCCLK# DVOCCLK DVOBHSYNC DVOBVSYNC DVOCD5 DVOCD4 VREFGC VREFGC PCI Expansion Slot Table 16. PCI Expansion Slot...

  • Page 119: Pci Express X1 Slot

    KP915GV Product Manual Not used but pulled low Not used but pulled high to +5V Not connected PCI Express x1 Slot Table 17. PCI Express x1 Slot (PCI-E x1) Signal Signal Signal Signal PRSNT1# 3.3V 3.3VAUX PWRGD WAKE# RSVD RSVD...

  • Page 120: Table 20. Serial Port

    KP915GV Product Manual Table 20. Serial Port SIGNAL SIGNAL SOUT Table 21. VGA Port SIGNAL SIGNAL GREEN BLUE Horizontal Sync Vertical Sync Table 22. 2 x Dual Stack USB Ports SIGNAL SIGNAL DATA0- DATA1- DATA0+ DATA1+ Table 23. LAN Jack...

  • Page 121: Table 24. 3 X Audio Jack

    KP915GV Product Manual Table 24. 3 x Audio Jack SIGNAL Left Audio Ring Right Audio Sleeve Remark L- Line (Line In, Line Out) Table 25. 1394 Header SIGNAL SIGNAL TA1+ TB1- TA1- Power Power TB1+ Table 26. Front Panel Header...

  • Page 122: Table 27. General Purpose I/O Headers

    KP915GV Product Manual Table 27. General Purpose I/O Headers SIGNAL SIGNAL +5V (fused) GPIO20 GPIO21 GPIO22 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 Reserved KEY (no pin fitted) GPI23 GPI24 Table 28. Power Supply Connector SIGNAL SIGNAL +3.3V +3.3V -12V +3.3V...

  • Page 123: Table 30. Ata/100 Hard Drive Disk Connector

    KP915GV Product Manual Table 30. ATA / 100 Hard Drive Disk Connector SIGNAL SIGNAL HDRST# Device data 7 Device data 8 Device data 6 Device data 9 Device data 5 Device data 10 Device data 4 Device data 11 Device data 3...

  • Page 124: Table 33. Tpm Header

    KP915GV Product Manual Table 33. TPM Header SIGNAL SIGNAL LCLK LFRAME# KEY PIN LRESET# LAD3 LAD2 LAD1 LAD0 SERIRQ CLKRUNin LPCPDn Table 34. Complex Programmable Logic Device (CPLD) JTAG Header SIGNAL VCC_STBY CPLD_TDO CPLD_TDI KEY PIN CPLD_TMS CPLD_TCK Table 35.

  • Page 125: Table 37. Remote Thermal Sensor

    KP915GV Product Manual Table 37. Remote Thermal Sensor SIGNAL DIODE+ DIODE- Table 38. 3 X Fan Connector SIGNAL +12V TACHO Table 39. SMBus Connector SIGNAL +3.3V DATA CLOCK Table 40. PS/2 Keyboard Header SIGNAL +5V (fused) DATA CLOCK Table 41. PS/2 Mouse Header...

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