Chipset - Asus P5LD2-X GBL User Manual

4.4.4

Chipset

The menu allows you to change the advanced chipset settings. Select an item then
press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD
Hyper Path 3
DRAM Throttling Threshold
Boot Graphic Adapter Priority
PEG Buffer Length
Link Latency
PEG Root Control
Slot Power
High Priority Port Select
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according to the
DRAM SPD (Serial Presence Detect). When disabled, you can manually set the
DRAM timing parameters through the DRAM sub-items. The following sub-items
appear when this item is Disabled.
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time the
data actually becomes available.
Configuration options: [6 Clock] [5 Clocks] [4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks] [6 Clocks]
DRAM RAS# to # Delay [4 Clocks]
Controls the latency between the DDR active command and the read/write
command. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks]
[6 Clocks]
DRAM # Activate to Precharge [15 Clocks]
Configuration options: [4 Clocks] [5 Clocks] ~ [18 Clocks]
DRAM Write Recovery Time [4 Clocks]
Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]
ASUS P5LD2-X/GBL
[Enabled]
[Auto]
[Auto]
[PCI Express/PCI]
[Auto]
[Auto]
[Auto]
[Auto]
[Disabled]
Configuration options: [Disabled] [Enabled]
Enable or Disable
Configure DRAM Timing
by SPD
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
4-23