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ARM AMBA NIC-301 Technical Reference Manual

Amba network interconnect
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AMBA
Network Interconnect (NIC-301)
®
Revision: r2p1
Technical Reference Manual
Copyright © 2006-2010 ARM. All rights reserved.
ARM DDI 0397G (ID031010)

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Summary of Contents for ARM AMBA NIC-301

  • Page 1 AMBA Network Interconnect (NIC-301) ® Revision: r2p1 Technical Reference Manual Copyright © 2006-2010 ARM. All rights reserved. ARM DDI 0397G (ID031010)
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    About the functions ....................... 2-2 Interfaces ........................2-3 Operation ........................2-12 Chapter 3 Programmers Model About this programmers model ..................3-2 Configuration programmers model ................3-3 Appendix A Revisions Glossary ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 4 Table 3-5 Peripheral ID registers ........................ 3-8 Table A-1 Differences between issue E and issue F ................... A-1 Table A-2 Differences between issue F and issue G .................. A-2 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 5 Remap set to 010 ........................2-22 Figure 2-4 Remap set to 011 ........................2-23 Figure 2-5 Remap set to 101 ........................2-23 Figure 3-1 Address map of the programmers model ..................3-3 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 6: Preface

    Preface This preface introduces the AMBA Network Interconnect (NIC-301). It contains the following sections: • About this book on page vii • Feedback on page ix. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 7: About This Book

    Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as commands, file monospace and program names, and source code. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 8 Lower-case n At the start or end of a signal name denotes an active-LOW signal. Additional reading This section lists publications by ARM and by third parties. See Infocenter, http://infocenter.arm.com, for access to ARM documentation. ARM publications This book contains information that is specific to this product. See the following documents for other relevant information: •...

  • Page 9: Feedback

    Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version.
  • Page 10 About the AMBA Network Interconnect on page 1-2 • Key features on page 1-3 • Relationship between AMBA Network Interconnect and AMBA Designer on page 1-4 • Product revisions on page 1-5. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 11: Chapter 1 Introduction

    Routing omitted for clarity Default AMBA slave signals AMIB master AMBA Distributed Global interface slave ASIB Programmers interface View (GPV) Figure 1-1 AMBA Network Interconnect top-level block diagram ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 12: Key Features

    Global Programmers View (GPV) for the entire infrastructure that you can configure so that any master, or a discrete configuration slave interface, can access it. See Chapter 3 Programmers Model. • Highly flexible timing closure options. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 13: Relationship Between Amba Network Interconnect And Amba Designer

    • Install AMBA Designer. • Generate and verify RTL sub-systems of ARM IP. • Stitch ARM components together. ARM components conform to the IP-XACT standard ™ from the SPIRIT Consortium ™ The AMBA Network Interconnect (NIC-301) Supplement to AMBA Designer (ADR-301) User Guide describes how to produce a customized infrastructure.

  • Page 14: Product Revisions

    The choice of CDAS is independent for reads and writes. • Additional configuration option for the single-slave-per-ID CDAS that permits only a single data-active write transaction to be in progress. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 15 Multi-region slave support replaces a single region per slave • Write FIFO, transaction release control instead of fixed write transaction release point. See Appendix A Revisions. r2p0-r2p1 Contains no differences in functionality. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 16: Chapter 2 Functional Description

    This chapter describes the functionality of the AMBA Network Interconnect. It contains the following sections: • About the functions on page 2-2 • Interfaces on page 2-3 • Operation on page 2-12. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 17: About The Functions

    AMBA Designer to create highly complex topologies using these modules. For more information, see the AMBA Designer (ADR-301) User Guide and AMBA Network Interconnect (NIC-301) Supplement to AMBA Designer (ADR-301) User Guide. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 18: Interfaces

    SYNC n:m. • Security of the following types: Secure All transactions originating from this slave interface are flagged as secure transactions and can access both secure and non-secure components. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 19: Table 2-1 Combination Of Configuration Parameters

    Combination 1 on page 2-5 Not configured Configured Combination 2 on page 2-5 Configured Configured Combination 3 on page 2-5 Not configured Not configured Combination 4 on page 2-6 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 20: Figure

    • Read fixed length bursts with HPROT[3] asserted to AXI fixed length bursts. • Read fixed length bursts with HPROT[3] negated to AXI singles. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 21 AXI domain. This is only possible with read transfers because AXI writes receive a response at the end of the burst only. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 22 Support for the full AHB-Lite protocol with only SWAP-like locks. Note You can reduce the gate count and increase the performance if the attached master does not create any AHB lock transactions. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 23 Read issuing capability of 1-32 transactions. • Buffering that FIFO and clocking function on page 2-15 describes. • Timing isolation: — from the external slave — from the network. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 24: Table 2-2 Axi Burst Type To Ahb Burst Type Mapping

    AHB responses are merged into a single AXI buffered response. The merged response is an AXI SLAVE ERROR if any of the AHB-Lite data beats have an AHB ERROR. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 25 APB interface ensure that only WORD writes access the APB sub-system. The address and data widths are fixed as follows: • address width of 32-bit • data width of 32-bit. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-10 ID031010 Non-Confidential...
  • Page 26 APB ports. • security of the following types: — secure for each APB port — non-secure for each APB port — boot secure for all APB ports. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-11 ID031010 Non-Confidential...

  • Page 27: Operation

    INCR bursts on page 2-13 • WRAP bursts on page 2-13 • Fixed bursts on page 2-13 • Bypass merge on page 2-13 • Acceptance capability on page 2-14. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-12 ID031010 Non-Confidential...

  • Page 28: Table 2-3 Conversion Of Incr Bursts By The Upsize Function

    You can configure the upsizer function to have a programmable bit named . If bypass_merge is asserted, the network does not alter any transactions that could pass through bypass_merge legally without alteration. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-13 ID031010 Non-Confidential...

  • Page 29: Table 2-5 Conversion Of Incr Bursts By The Downsize Function

    WRAP16, in which case, it treats the WRAP burst as two INCR bursts that can each map onto one or more INCR bursts. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-14 ID031010...

  • Page 30: Table 2-6 Conversion Of Fixed Bursts By The Downsize Function

    If you configure the network as a clock frequency crossing bridge, then a FIFO function is also configured. Note You can configure the buffering for multiple outstanding transactions even if you are using a 1:1 clocking ratio. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-15 ID031010 Non-Confidential...

  • Page 31: Table 2-7 How To Change Modes

    For some changes, it is necessary to use a different setting, that is, you can only change safely from 1:n to 1:m by first programming the register to m:n, before the clock update. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-16 ID031010...
  • Page 32 Single slave per ID This ensures that at a slave interface of a switch: • all outstanding read transactions with the same ID go the same destination ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-17 ID031010 Non-Confidential...
  • Page 33 When the network receives a locking transaction, if there is a co-incident lock transaction on the other address channel, then the read always takes priority, and the write address transaction is stalled. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-18 ID031010 Non-Confidential...
  • Page 34 The security checks that TrustZone technology implements cover the scope of a configured network. Note TrustZone is a brand name that represents aspects of implementing ARM security extensions. For example, security checks that are not within the scope of the network are: Physical attack Physical attack on the device.
  • Page 35 DECERR, and the transaction is not transferred to the slave. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-20 ID031010 Non-Confidential...
  • Page 36 Consider a configuration that uses three remap bits. Figure 2-1 on page 2-22 shows the memory map when remap is set to 000, representing no remap. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-21 ID031010...

  • Page 37: Figure 2-1 No Remap, Remap Set To 000

    Slave 0 region 0 Slave 1 Figure 2-3 Remap set to 010 Note Remap bit 0 still takes precedence if you set it as Figure 2-4 on page 2-23 shows. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-22 ID031010 Non-Confidential...

  • Page 38: Figure 2-4 Remap Set To 011

    101, Slave 1 is removed. Slave 2 Slave 0 region 1 Slave 0 region 0 Slave 3 region 1 Slave 3 region 0 Figure 2-5 Remap set to 101 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. 2-23 ID031010 Non-Confidential...

  • Page 39: Chapter 3 Programmers Model

    Programmers Model This chapter describes the programmers model. It contains the following sections: • About this programmers model on page 3-2 • Configuration programmers model on page 3-3. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 40: About This Programmers Model

    Programmers Model About this programmers model This chapter describes the architecture of the AMBA Network Interconnect AMBA infrastructure component. It describes the programmers interface and system characteristics. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 41: Configuration Programmers Model

    Maximum n = 63 Master interface 1 registers Master interface 0 registers ID registers Address control registers Configurable base address Figure 3-1 Address map of the programmers model ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 42: Table 3-1 Registers For Each Asib

    Valid only with a FIFO for the WFIFO channel, and if not an AHB slave 0x040 wr_tidemark interface. See FIFO and clocking function on page 2-15 for information wr_tidemark ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 43: Table 3-2 Registers For Each Ib

    See Upsizing data width function on page 2-12, Downsizing data width function on page 2-14, and Bypass merge on page 2-13. Reserved. 0x028 0x03C Value, only with a FIFO for the WFIFO channel. 0x040 wr_tidemark ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 44: Table 3-3 Registers For Each Amib

    Bypass merge. This register is only present if upsizing or downsizing. See 0x024 fn_mod2 Upsizing data width function on page 2-12 and Downsizing data width function on page 2-14. Reserved. 0x028 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 45: Address Region Control Registers

    For example, the security1[5] bit is the security setting for the address region for master interface node number 1, region 5. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 46: Table

    Revision, JEP106 code flag, JEP106[6:4] 0xFE8 0x4B Peripheral ID3 You can set this using the AMBA Designer Graphical User Interface 0xFEC 0x00 (GUI) Component ID0 Preamble 0xFF0 0x0D ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 47 It is possible for AMIB registers to exist in regions that are not contiguous, for example, you could have a register named AMIB_0 in the region , and have a register named AMIB_1 0x4000 in the region 0xA000 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 48: Table A-1 Differences Between Issue E And Issue F

    Multi-region slave support replaces a single region per slave Throughout the document r2p0 Write FIFO, transaction release control instead of fixed write transaction release point Throughout the document r2p0 ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...

  • Page 49: Table A-2 Differences Between Issue F And Issue G

    Revisions Table A-2 Differences between issue F and issue G Change Location Affects No technical changes ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. ID031010 Non-Confidential...
  • Page 50 AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave IP developments and ARM recommends only a subset of the protocol is usually used. This subset is defined as the AMBA AHB-Lite protocol.
  • Page 51 The letter x in the signal name denotes an AXI channel as follows: Write address channel. Write data channel. Write response channel. Read address channel. Read data channel. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. Glossary-2 ID031010 Non-Confidential...
  • Page 52 The number of active write transactions for which the MI is capable of transmitting data. This is counted from the earliest transaction. Write issuing capability The maximum number of active write transactions that an MI can generate. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. Glossary-3 ID031010 Non-Confidential...
  • Page 53 A data item stored at an address that is not divisible by the number of bytes that defines the data Unaligned size is said to be unaligned. For example, a word stored at an address that is not divisible by four. ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. Glossary-4 ID031010 Non-Confidential...
  • Page 54 Glossary A 32-bit data item. Word ARM DDI 0397G Copyright © 2006-2010 ARM. All rights reserved. Glossary-5 ID031010 Non-Confidential...

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