Intel DH61WW Technical Product Specification page 69

Table 38. Port 80h POST Codes (continued)
Port 80 Code
0x31
0x33
0x34
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x58
0x59
0x5A
0x5B
Progress Code Enumeration
PEIMs/Recovery
Crisis Recovery has initiated
Loading recovery capsule
Start recovery capsule / valid capsule is found
CPU Initialization
CPU PEI Phase
Begin CPU PEI Init
XMM instruction enabling
End CPU PEI Init
CPU PEI SMM Phase
Begin CPU SMM Init smm relocate bases
Smm relocate bases for APs
End CPU SMM Init
CPU DXE Phase
CPU DXE Phase begin
Refresh memory space attributes according to MTRRs
Load the microcode if needed
Initialize strings to HII database
Initialize MP support
CPU DXE Phase End
CPU DXE SMM Phase
CPU DXE SMM Phase begin
Relocate SM bases for all APs
CPU DXE SMM Phase end
Enumerating PCI buses
Allocating resources to PCI bus
Hot Plug PCI controller initialization
Resetting USB bus
Reserved for USB
ATA/ATAPI/SATA
Resetting PATA/SATA bus and all devices
Reserved for ATA
Error Messages and Beep Codes
I/O Buses
USB
continued
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