CHAPTER 3 THEORY OF OPERATION
HL-1450
Fig. 3-5 shows the block diagram of the main PCB of the HL-1450 printer.
A S I C
CPU Core
(MB86832)
Oscillator (33.33MHz)
Reset Circuit
BUS
INT
Address Decoder
DRAM Control
Program + Font ROM
8.0 Mbytes
Timer
RAM
(4.0 Mbytes)
FIFO
Option RAM (SIMM)
CDCC Parallel I/O
To PC
(max. 32Mbytes)
To PC
USB I/O
Soft Support
EEPROM (512 x 8 bits)
EEPROM I/O
Engine Control I/O
To Engine PCB
Fig. 3-5
3-5