1. Manuals
  2. Brands
  3. General Standards Corporation Manuals
  4. Controller
  5. PCI66-SIO4B
  6. User manual

General Standards Corporation PCI66-SIO4B User Manual

Quad channel multi-protocol serial controller with deep transmit and receive fifos and rs-422/rs-485 transceivers
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
PCI66-SIO4B
User's Manual
Quad Channel Multi-Protocol Serial Controller
With Deep Transmit and Receive FIFOs
and RS-422/RS-485 Transceivers
RS-422/RS-485
General Standards Corporation
8302A Whitesburg Drive
Huntsville, AL 35802
Phone: (256) 880-8787
Fax: (256) 880-8788
URL:
www.generalstandards.com
E-mail:
techsupport@generalstandards.com
Rev 0

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PCI66-SIO4B and is the answer not in the manual?

Questions and answers

Related Manuals for General Standards Corporation PCI66-SIO4B

Summary of Contents for General Standards Corporation PCI66-SIO4B

  • Page 1 PCI66-SIO4B User’s Manual Quad Channel Multi-Protocol Serial Controller With Deep Transmit and Receive FIFOs and RS-422/RS-485 Transceivers RS-422/RS-485 General Standards Corporation 8302A Whitesburg Drive Huntsville, AL 35802 Phone: (256) 880-8787 Fax: (256) 880-8788 URL: www.generalstandards.com E-mail: techsupport@generalstandards.com Rev 0...
  • Page 2 General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein, nor is any license conveyed under any patent right of any rights of others.

  • Page 3: Related Publications

    RELATED PUBLICATIONS ZILOG Z16C30 USC® User’s Manual ZILOG Z16C30 USC® Product Specifications Databook ZILOG, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 (408) 370-8000 http://www.zilog.com/ PLX PCI 9056 Data Book PLX Technology Inc. 390 Potrero Avenue Sunnyvale, CA 4085 (408) 774-3735 http://www.plxtech.com/ EIA-422-A –...

  • Page 4: Table Of Contents

    TABLE OF CONTENTS PREFACE ..................................I RELATED PUBLICATIONS ............................ II TABLE OF CONTENTS ............................III CHAPTER 1: INTRODUCTION ..........................1 ..........................1 ENERAL ESCRIPTION Z16C30 U ....................2 NIVERSAL ERIAL ONTROLLER FIFO ........................2 RANSMIT ECEIVE RS422/RS485 T ........................2 RANSCEIVERS PCI I ..............................
  • Page 5 CHAPTER 3: PROGRAMMING ........................... 20 ............................. 20 NTRODUCTION ................................. 20 ESETS FIFO ................................20 3.2.1 FIFO F ..............................20 LAGS 3.2.2 FIFO C ............................21 OUNTERS 3.2.3 FIFO S ..............................21 ......................... 21 OARD VS HANNEL EGISTERS ................. 22 ROGRAMMABLE SCILLATOR ROGRAMMABLE LOCKS...

  • Page 6: Chapter 1: Introduction

    Transmitter FIFO 66MHz 32 bit Interface Control Logic Prog Figure 1-1 Block Diagram of PCI66-SIO4B  Four Independent Multi-Protocol Serial Channels  Synchronous Serial Data Rates up to 10 Mbits/sec  Asynchronous Serial Data Rates up to 1 Mbit/sec ...

  • Page 7: Z16C30 Universal Serial Controller

    Z16C30 Universal Serial Controller The PCI66-SI04B is designed around the Z16C30 Universal Serial Controller (USC). The Z16C30 is a dual channel multi-protocol serial controller which may be software configured to satisfy a wide variety of serial communications applications. The USC supports most common asynchronous and synchronous serial protocols. The USC provides many advanced features, including: ...

  • Page 8: General Purpose Io

    General Purpose IO Since some signals may not be used in all applications, the SIO4B provides the flexibility to remap unused signals to be used as general purpose IO. For example, this would allow support for an application requiring DTR/DSR signals to be implemented on an unused DCD or TxAuxC signals.

  • Page 9: Chapter 2: Local Space Registers

    CHAPTER 2: LOCAL SPACE REGISTERS Register Map The SIO4B is accessed through three sets of registers – PCI Registers, USC Registers, and GSC Firmware Registers. The GSC Firmware Registers and USC Registers are referred to as Local Space Registers and are described below. The PCI registers are discussed in Chapter 3.

  • Page 10: Firmware Revision : Local Offset X 0000

    0x0044 Read/Write Ch 4 Rx Almost Full/Empty 00070007 0x0048 Read/Write Ch 4 Data FIFO 000000XX 0x004C Read/Write Ch 4 Control/Status 0000CC00 0x0050 Read/Write Ch 1 Sync Byte 00000000 0x0054 Read/Write Ch 2 Sync Byte 00000000 0x0058 Read/Write Ch 3 Sync Byte 00000000 0x005C Read/Write...

  • Page 11: Board Control : Local Offset X 0004

    2.1.2 Board Control: Local Offset 0x0004 The Board Control Register defines the general control functions for the board. Board Reset 1 = Reset all Local Registers and FIFOs to their default values Notes: This bit will automatically clear to 0 following the board reset. Board Reset will NOT reset programmable oscillator.

  • Page 12: Channel Tx Almost Flags Local Offset 0040

    2.1.3 Board Status: Local Offset 0x0008 The Board Status Register gives general overall status for a board. The Board Jumpers (D1:D0) are physical jumpers which can be used to distinguish between boards if multiple SIO4 boards are present in a system. D31:D9 RESERVED 0 = Standard...

  • Page 13: Hannel Rx Almost Lags Ocal Ffset 0044

    2.1.6 Channel RX Almost Flags: Local Offset 0x0014 / 0x0024 / 0x0034 / 0x0044 The Rx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs. The Almost Full/Empty Flags may be read as status bits in the Channel Control/Status Register, and are also edge- triggered interrupt sources to the Interrupt Register.

  • Page 14: Hannel Ync Etect Yte Ocal Ffset 005C

    D7:0 Channel Control Bits Reset USC (Pulsed) ‘1’ = Reset USC chip Notes:  This value will automatically clear to ‘0’.  Following a USC Reset, the next access to the USC must be a write of 0x00 to Local Offset 0x100 (Ch1/2) or Local Offset 0x300 (Ch3/4).

  • Page 15: Interrupt Registers

    2.1.10 Interrupt Registers There are 32 on-board interrupt sources (in addition to USC interrupts and PLX interrupts) which may be individually enabled. Four interrupt registers control the on-board interrupts – Interrupt Control, Interrupt Status, Interrupt Edge/Level, and Interrupt Hi/Lo. The 32 Interrupt sources are: IRQ # Source Default Level...

  • Page 16: Interrupt Control : Local Offset X 0060

    2.1.10.1 Interrupt Control: Local Offset 0x0060 The Interrupt Control register individually enables each interrupt source. A ‘1’ enables each interrupt source; a ‘0’ disables. An interrupt source must be enabled for an interrupt to be generated. 2.1.10.2 Interrupt Status/Clear: Local Offset 0x0064 The Interrupt Status Register shows the status of each respective interrupt source.

  • Page 17: Hannel In Ource Ocal Ffset 008C

    2.1.11 Channel Pin Source: Local Offset 0x0080 / 0x0084 / 0x0088 / 0x008C The Channel Pin Source Register configures the Output source for the Clocks, Data, RTS, and DCD outputs. Transceiver Termination Loopback DCE/DTE Transceiver Protocol Mode Enable Disable Enable Mode TxAuxC Unused...
  • Page 18 D21:19 Cable TxD Output Control Allows TxD output to be used as a general purpose output. TxD Source USC_TxD Output ‘0’ Output ‘1’ Differential Biphase Mark Differential Biphase Space Level Differential Biphase Level D18:17 Cable TxAuxC Output Control Defines the Clock Source for the TxAuxC signal to the IO connector. TxAuxC Source Tristate On-board Programmable Clock...
  • Page 19 D10:9 USC_CTS Direction Setup Defines the CTS direction for the USC CTS pin. Notes:  If CTS is used as GPIO, set this field to ‘00’ and set Pin Source Register D14:D13 for output / Pin Status Register D2 for input. ...

  • Page 20: Hannel In Tatus Ocal Ffset 009C

    D2:0 USC_TxC Source Defines the Clock Source for the USC_TxC pin. Since this signal is bidirectional (it may be used as either an input or output to the USC), the clock source must agree with the USC Clock setup (USC IO Control Reg D2:0) to ensure the signal is not being driven by both the USC and the FPGA.

  • Page 21: Fifo Size Egister Ocal Ffset 00Ec

    2.1.15 FIFO Size Register: Local Offset 0x00E0 / 0x00E4 / 0x00E8 / 0x00EC The FIFO Size Registers display the sizes of the installed data FIFOs. This value is calculated at power-up This value, along with the FIFO Count Registers, may be used to determine the amount of data which can be safely transferred without over-running (or under-running) the FIFOs.

  • Page 22: Universal Serial Controller Registers

    Universal Serial Controller Registers The internal registers of the Zilog Z16C30 Universal Serial Controller (USC) are memory mapped into Local Address space. It is beyond the scope of this manual to provide comprehensive USC programming information. For detailed programming information, please refer to the Zilog High Speed Communication Controller Product Specifications Databook for the Z16C30 and the Zilog Z16C30USC User’s Manual.

  • Page 23: Usc Data Transfer

    2.2.3 USC Data Transfer Although the Z16C30 USC contains 32 byte internal FIFOs for data transfer, these are typically not used on the SIO4B. Since the SIO4B has much deeper external FIFOs (or internal FPGA FIFOs), the internal USC FIFOs are setup to immediately transfer data to/from the external FIFOs.

  • Page 24: Usc Register Memory Map

    2.2.4 USC Register Memory Map To access the USC in 8-bit mode, the driver is required to access the upper and lower bytes of each register independently. The odd address byte will access the upper byte of each register (D15-D8), and the even address byte will access the lower byte (D7-D0).

  • Page 25: Chapter 3: Programming

    CHAPTER 3: PROGRAMMING Introduction This section addresses common programming questions when developing an application for the SIO4. General Standards has developed software libraries to simplify application development. These libraries handle many of the low-level issues described below, including Resets, FIFO programming, and DMA. These libraries may default the board to a “standard”...

  • Page 26: Fifo Counters

    The Almost Flag value represents the number of bytes from each respective “end” of the FIFO. The Almost Empty value represents the number of bytes from empty, and the Almost Full value represents the number of bytes from full (NOT the number of bytes from empty). For example, the default value of “0x0007 0007” in the FIFO Almost Register means that the Almost Empty Flag will indicate when the FIFO holds 7 bytes or fewer.

  • Page 27: Programmable Oscillator / Programmable Clocks

    Programmable Oscillator / Programmable Clocks Two On-Board Programmable Oscillators provide each channel with a unique programmable clock source using Cypress Semiconductor CY22393 Programmable Clock generators. In order to program the oscillator, it is necessary to calculate and program values for different clock frequencies. General Standards has developed routines to calculate the necessary values for a given setup and program the clock generator.
  • Page 28 FPGA CLOCK CONTROL ProgClk TxAuxC Source TxAuxC Pin Source Reg D18:D17 RxAuxC / RxAuxC TxAuxC Connector RxAuxC TxC Source On-Board Programmable ProgClk Oscillator Pin Source Reg D8:D6 USC TxC Source Pin Source Reg D2:D0 USC TxC USC TxC USC RxC Source USC RxC USC RxC...

  • Page 29: Dce/Dte Mode

    The preceding suggestions should work for most applications. The default Pin Source Register value should set the clocks to work with both scenarios – USC TxC pin = Programmable Clock, USC RxC Pin = Cable RxC, Cable TxC = Programmable Clock. (For async, use USC TxC is input clock). DCE/DTE Mode As all signals are bidirectional, the DCE or DTE mode will set the direction for each signal.

  • Page 30: General Purpose Io

    General Purpose IO Unused signals at the cable may be used for general purpose IO. The Pin Source and Pin Status Registers provide for simple IO control of all the cable interface signals. For outputs, the output value is set using the appropriate field in the Pin Source Register.

  • Page 31: Chapter 4: Pci Interface

    CHAPTER 4: PCI INTERFACE PCI Interface Registers The PCI interface is handled by a PCI9056 I/O Accelerator from PLX Technology. The PCI interface is compliant with the 5V, 66MHz 32-bit PCI Specification 2.2. The PCI9056 provides dual DMA controllers for fast data transfers to and from the on-board FIFOs.

  • Page 32: Local Configuration Registers

    4.1.2 Local Configuration Registers The Local Configuration registers give information on the Local side implementation. These include the required memory size. The SI04B memory size is initialized to 4k Bytes. All other Local Registers initialize to the default values described in the PCI9056 Manual. 4.1.3 Runtime Registers The Runtime registers consist of mailbox registers, doorbell registers, and a general-purpose control register.

  • Page 33: Chapter 5: Hardware Configuration

    CHAPTER 5: HARDWARE CONFIGURATION Board Layout The following figure is a drawing of the physical components of the PCI66-SI04B: 7.45" 6.9" FPGA PCI Bridge Figure 5-1: Board Layout Board ID Jumper J4 Jumper J4 allows the user to set the Board ID in the GSC Board Status Register (See Section 2.1.3). This is useful to uniquely identify a board if more than one SI04B card is in a system.

  • Page 34: Termination Resistors

    Termination Resistors The PCI66-SIO4B board is designed with socketed external parallel termination. The external termination resistors are 8 pin SIPs. There are 8 termination SIPs – RP5, RP6, RP10, RP11, RP16, RP17, RP20, and RP21. The external parallel resistors are for RS422/RS485 termination. This board is shipped with 120 Ohm external termination resistors.

  • Page 35: Interface Connectors

    Interface Connectors User I/O Connector: 68-pin SCSI connector (female) - P2 Part Number: AMP/TYCO 787170-7 Mating Connector: AMP/TYCO 749111-6 (or equivalent) Pin 34 Pin 1 Pin 68 Pin 35 RS422/RS485 RS422/RS485 AUXC1+ AUXC3+ AUXC1- AUXC3- DCD1+ DCD3+ DCD1- DCD3- CTS1+ RTS1+ CTS3+ RTS3+...

  • Page 36: Chapter 6: Ordering Options

    (quotes@generalstandards.com). Interface Cable General Standards Corporation can provide an interface cable for the SI04B board. This standard cable is a twisted pair cable for increased noise immunity. Several standard cable lengths are offered, or the cable length can be custom ordered to the user’s needs. Versions of the cable are available with connectors on both ends, or the cable may be ordered with a single connector to allow the user to adapt the other end for a specific application.

  • Page 37: Appendix A: Programmable Oscillator Programming

    APPENDIX A: PROGRAMMABLE OSCILLATOR PROGRAMMING The 4 on-baord clock frequencies are supplies via two Cypress Semiconductor CY22393 Programmable Clock Generatosr. In order to change the clock frequencies, this chip must be reprogrammed. This document supplies the information necessary to reprogram the on-board clock frequencies. GSC has developed routines to calculate and program the on-board oscillator for a given set of frequencies, so it should not be necessary for the user need the following information –...
  • Page 38 Measure Channel 3 Clock Measure Channel 4 Clock Reserved (Unused) Status Word Readback Control 0 => Status Word D31-D8 == Measured Channel Value 1 => Status Word D31-D8 == Control Word D23-D0 Post-divider set 0 = Ignore D23-D8 during Command Word Write 1 = Set Channel Post-Dividers from D23-D8 during Command Word Write D11-D8 Channel 1 Post-Divider...
  • Page 39 The Internal RAM is defined as follows: RAM Address 0x08–0x57 correspond directly to the CY22393 registers. Address Description Default Value 0x00 – 0x05 Reserved (Unused) 0x00 0x06 Reserved 0xD2 0x07 Reserved 0x08 0x08 ClkA Divisor (Setup0) 0x01 0x09 ClkA Divisor (Setup1) 0x01 0x0A ClkB Divisor (Setup0)

  • Page 40: Appendix B: Firmware Revisions / Features Register

    Firmware Register - Local Offset 0x00 (0xE1100100) D31:16 HW Board Rev 0xE110 PCI66-SIO4B Rev NR/A 1 = Features Register Present 1 = Complies with this standard 1 = 66MHz PCI bus interface...
  • Page 41 Feature Register - Local Offset 0xFC (0x00F97AF4) D31:24 RESERVED 1 = Sync Timestamp + RxWord Bit Size 1 = Rx Stop on Full in Ch_Ctrl 1 = SRAM Debug 1 = Rx Status byte (std only) D19:D18 Std Timestamp 01 = single external clock 10 = single internal clock D17:D16 FPGA Reprogram field...

Table of Contents