Efinix Titanium Ti375 User Manual

Pcie early access board

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Ti375 PCIe

Early Access Board

User Guide

Ti375-PCIeEA-BRD-UG-v1.1

August 2024

www.efinixinc.com

trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.

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Summary of Contents for Efinix Titanium Ti375

Page 1 Copyright 2024. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other © trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.
Page 2: Table Of Contents
Contents Introduction............................. 3 What's in the Box?................................3 Register Your Kit................................3 ® Download the Efinity Software............................. 3 Installing the Windows USB Drivers..........................4 Installing the Linux USB Driver............................4 Board Functional Description......................5 Features....................................5 Overview.................................... 6 Power On................................... 7 Reset....................................7 Configuration..................................
Page 3: Introduction
Ti375 PCIe Early Access Board User Guide Introduction Thank you for choosing the Ti375 PCIe Early Access Board (part number: Ti375-PCIE-EA). This early access board lets you see the Ti375 PCIe transceivers in action and get a sneak peak at the capabilities of the Ti375 FPGA. You can connect the Ti375 PCIe Early Access Board's PCIe edge card connector and edge card socket with a PCIe extender cable to do a loopback test.
Page 4: Installing The Windows Usb Drivers
The Ti375 PCIe Early Access Board development board has an FTDI FT2232H chip to communicate with the USB port. Note: If you have another Efinix board and are using the Ti375 PCIe Early Access Board, you must AN 050: Managing Windows Drivers manage drivers accordingly.
Page 5: Board Functional Description
The main purpose of this board is to demonstrate the PCIe Gen4x4 capability. However, the board also has a direct connection between the non-PCIe transceiver banks, which can be used for an Ethernet 10GBase-KR loopback. However, Efinix will not be providing an example design to demonstrate that functionality.
Page 6: Overview
Ti375 PCIe Early Access Board User Guide Overview The board features the Eﬁnix Ti375 FPGA in a N1156-ball FBGA package, which is fabricated using Eﬁnix Quantum technology. The Quantum -accelerated programmable ® ® logic and routing fabric is wrapped with an I/O interface in a small footprint package. Ti375 FPGAs also include embedded memory blocks and DSP blocks.
Page 7: Power On
Ti375 PCIe Early Access Board User Guide Power On You turn on the board by attaching the power cable to the board and a power source. The power good LEDs illuminate, giving you a visual conﬁrmation of the status. Do not connect multiple active power sources to the board at the same time.
Page 8: Clock Sources
Ti375 PCIe Early Access Board User Guide Clock Sources Nine on-board oscillators (25 and 100 MHz) are available to drive the Ti375 PLL input pins and transceiver clock inputs. Table 1: Oscillator and Clock Generator Sources Clock Source Label Ti375 Pin Name Resource 25 MHz oscillator OSC13...
Page 9: Header J34 And J35 (Jtag)
Ti375 PCIe Early Access Board User Guide Header J34 and J35 (JTAG) J34 and J35 are headers for the JTAG interface. You can access the Ti375 JTAG pins through this interface. Table 3: JTAG Pin Assignments Header Pin Number Signal Name Header USB1 (USB FTDI FT2232H) USB1, a micro-USB receptacle, is the interface between the board and your computer for communication through the FTDI FT2232H chip.
Page 10: Ti375 Pcie Early Access Board Example Design
Ti375 PCIe Early Access Board User Guide Ti375 PCIe Early Access Board Example Design Eﬁnix preloads the Ti375 PCIe Early Access Board with an example design that demonstrates the following functions: • Two-way transaction layer packet traﬃc generator with AXI master and slave logic as well as a pattern generator and checker.
Page 11: Set Up The Hardware
Ti375 PCIe Early Access Board User Guide Set Up the Hardware The following ﬁgure shows the hardware setup steps: Figure 4: Hardware Setup Ti375 J124 USB1 J29 J28 Power Supply Important: Always remove the power supply before attaching or detaching cables. 1.
Page 12: Run The Demonstration Design
Ti375 PCIe Early Access Board User Guide Run the Demonstration Design Before you run the demonstration design, download the example design ﬁles from the Eﬁnix Support Center. You need to use the debug proﬁle included with the design ﬁles. 1. Go to Support Center > Examples > Design Example: Ti375 PCIe Early Access Board (direct link).
Page 13: Reset The Design And Pcie Link
Ti375 PCIe Early Access Board User Guide Name Type Width Description q0_ltssm_state Probe LTSSM state for transceiver quad 0. Refer to “Appendix C: LTSSM State Encoding” in the Titanium PCIe Controller User Guide ® for more information. q0_link_status Probe Status of the PCIe link for transceiver quad 0. 2’b00: No receivers detected.
Page 14: Write To Pcie Registers Through Apb Interface
Ti375 PCIe Early Access Board User Guide Write to PCIe Registers through APB Interface The Debugger's apbvio tab gives you access to the PCIe Controller's conﬁguration register set through the APB interface. This access is useful for debugging purposes. Note: Refer to “Configuring Registers with the APB interface” in the Titanium PCIe Controller User Guide ®...
Page 15: Launching The Transceiver Debugger
Ti375 PCIe Early Access Board User Guide The right side of the window has an Eye Diagram Plot. The Status tab shows the PHY and link status; the Conﬁguration tab has options to customize the plot. Figure 5: Efinity Transceiver Debugger Launching the Transceiver Debugger In the Eﬁnity software v2024.1 you launch the Transceiver Debugger using a batch ﬁle (Windows) or shell script (Linux).
Page 16: Interpreting The Results
Ti375 PCIe Early Access Board User Guide 6. Review the PHY Status table in the Status tab. This table show whether the lanes are locked and ready. 7. In the Conﬁguration tab, adjust the settings for the eye diagram plot. Setting Description Vertical Offset Value Indicates how many vertical positions there are to the right and left...
Page 17: Creating Your Own Design
SPI active via JTAG bridge mode. Set the Starting Flash Address to 0x000000. Note: You use SPI active mode because you need to reset the FPGA. Efinix also includes the ti375n1156_ea_oob.bit file to be used with JTAG mode. Using JTAG mode requires you to reprogram the bitstream into the board when you reset the board.

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