Microchip Technology PolarFire SoC MSS Technical Reference Manual

PolarFire

Introduction

(Ask a Question)
®
The PolarFire SoC family offers the industry's first RISC-V based SoC FPGAs. The PolarFire SoC family combines
a powerful 64-bit 5x core RISC-V Microprocessor Sub-System (MSS), based on SiFive's U54-MC family, with the
PolarFire FPGA fabric in a single device. Packed with this powerful combination, PolarFire SoC devices offer the
scalable features of FPGAs and high-performance of ASICs. Only the FPGA fabric resources vary and the MSS
remains the same across PolarFire SoC device variants, making these devices ideal for a variety of applications.
PolarFire SoC FPGAs are ideal for running full-fledged Operating Systems (like Linux
This manual covers the PolarFire SoC MSS architecture and its functional blocks—the CPU Core Complex, AXI
Switch, MSS peripherals, Fabric interfaces, and MSS DDR controller. For information about configuring MSS,
see Standalone MSS Configurator User Guide for PolarFire
development and tool flow, and MSS booting, see
Important: The AXI protocol standard uses the terminology "Master" and "Slave". The equivalent
Microchip terminology is "Initiator" and "Target", respectively.
The following figure shows the MSS block at a high-level. For more details, see
©
2023 Microchip Technology Inc.
and its subsidiaries
®
SoC MSS Technical Reference Manual
PolarFire SoC Software Development and Tool Flow User
Technical Reference Manual
®
) using MSS.
SoC. For information about PolarFire SoC software
Figure 2-1.
Guide.
DS60001702G-page 1