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Summary of Contents for Ezurio SU60-SIPT
- Page 1 User Guide SU60-SIPT Development Kit (DVK-SU60-SIPT) Version 2.0...
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Page 2: Revision History
DVK-SU60-SIPT User Guide Revision History Version Date Notes Contributor(s) Approver 29 July 2017 Initial Release Jay White 15 Apr 2025 Ezurio rebranding Sue White Dave Drogowski https://www.ezurio.com/ © Copyright 2025 Ezurio All Rights Reserved... -
Page 3: Table Of Contents
DVK-SU60-SIPT User Guide Contents Overview ................................................. 4 Package Contents ..........................................4 SU60-SIPT Development Kit – Main Development Board ............................... 4 Key Features ............................................4 Understanding the Development Board ..................................5 Functional Blocks ............................................6 Pin Definitions ............................................. 6 3.1.1 SDIO-Pin Header ..........................................6 3.1.2... -
Page 4: Overview
SU60-SIPT module. This allows you to test different operating scenarios. The development board allows the SU60-SIPT module to physically connect to a SDIO host via the supplied SDIO extension cable and USB host via USB cable for development purposes. The development board also provides USB-to-Virtual COM port conversion through a FTDI chip – part number FT232R. -
Page 5: Understanding The Development Board
User Guide – Pin header (Ammeter) IO break-out (2.54 mm pitch headers) connectors interface for plugging-in external modules and accessing all interfaces of the SU60-SIPT • module [UART, LTE coexistence, PCM, GPIO, JTAG]. Two buttons and LEDs for user interaction •... -
Page 6: Functional Blocks
Figure 1: Development board 3 Functional Blocks The development board is formed from the following major functional blocks: Pin Definitions 3.1.1 SDIO-Pin Header Figure 2: DVK-SU60-SIPT SDIO pin header Table 1: SDIO pin definitions Voltage Name Type Description If Not Used Ref. -
Page 7: Pcie Golden Finger
PCIe host indication to disable the WLAN function of the device (input) (active low) Ground PERST0# I, PD 3.3V PCIe host indication to reset the device (input) (active low) PETn0 1.8V PCIe Transmit Data-Negative PCIE_3V3 Power 3.3V module power supply https://www.ezurio.com/ © Copyright 2025 Ezurio All Rights Reserved... -
Page 8: Power Supply
USB1 / USB2 SDIO Interface Figure 3: DVK-SU60-SIPT power supply The development board can be powered from DC 12V supply (into DC jack connector CN1), USB (type micro-B) connector (USB1 and USB2), or the host interface (PCIe or SDIO interface). The power source fed into DC jack is regulated down to 5V with an on-board regulator and wire to SW1. -
Page 9: Host Configuration
The 5V from the USB or the DC jack is regulated down to 3.3V with an on-board regulator on the development board. Switch SW1 selects between the regulated 5V and USB. The voltage from host interface (PCIe or SDIO interface) is not regulated but is fed directly to SU60-SIPT module supply pin. -
Page 10: Tact Switch
3.5 4-wire UART Serial Interface The development board provides access to the SU60-SIPT module 4-wire UART interface (TX, RX, CTS, RTS) either through USB (via U7 FTDI USB- UART convertor chip) or through a breakout header connector J15, J16, J17, and J18. Refer to... -
Page 11: Uart Mapping
Figure 6: USB to UART Interface and Header to UART interface 3.6 32.768KHz Oscillator The development kit is fitted with a (U5) 32.768KHz oscillator which provides sleep clock to SU60-SIPT module. Fit a jumper on J14 to disable the sleep clock, if necessary. -
Page 12: Pcm
The pin descriptions of J6 are shown in below table. Table 6: LTE coexistence pins Description Pin 1 Pin 2 LTE_SOUT Pin 3 LTE_SIN Pin 4 JTAG_TMS Pin 5 JTAG_TCK Pin 6 https://www.ezurio.com/ © Copyright 2025 Ezurio All Rights Reserved... -
Page 13: Gpios
1.26V to 2.2V; V is from -0.4V to 0.54V 3.10 LED Indicator Table 8: LED pins LEDs Description LED1 WLAN status (Active Low) LED2 BT status (Active Low) LED3 3.3V Module Power https://www.ezurio.com/ © Copyright 2025 Ezurio All Rights Reserved... -
Page 14: U.fl Connector
DVK-SU60-SIPT User Guide 3.11 U.FL Connector The development kit provides U.FL connectors for RF measurement Table 9: U.FL connectors U.FL Description CON3 ANT0 (Wi-Fi) CON1 ANT1 (Wi-Fi + BT) https://www.ezurio.com/ © Copyright 2025 Ezurio All Rights Reserved... -
Page 15: Additional Information
Ezurio materials or products for any specific or general uses. Ezurio or any of its affiliates or agents shall not be liable for incidental or consequential damages of any kind. All Ezurio products are sold pursuant...
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