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SiTime SiT95210 Manual

Ultra low jitter, programmable frequency, 4 outputs quad pll clock generator
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SiT95210
Ultra Low Jitter, Programmable Frequency, 4 Outputs
Quad PLL Clock Generator

Description

SiT95210
offers programmable Quad Fractional Frequency
translation-based jitter cleaning clock generator parts with
flexible input to output frequency translation options. Ultra-
high performance PLL supports up to 4 Diff/8 Single Ended
input clocks that are common for all the 4 fractional
translations and provides 4 clock outputs. The clock outputs
can be derived from any of the 4 PLLs in a fully flexible
manner.
It is fully programmable with the I2C/SPI interface or an
on chip one-time programmable non-volatile memory for
factory pre-programmed devices.

Applications

Carrier Ethernet,
◼
OTN Equipment,
◼
Microwave Backhaul,
◼
Gigabit Ethernet,
◼
Wireless Infrastructure,
◼
Network Line Cards,
◼
Small Cells,
◼
Data Center/Storage,
◼
SONET/SDH,
◼
Test / Instrumentation,
◼
Broadcast Video
◼
Product
Inputs / Outputs
Family
SiT95210
4 Diff / 8 SE Inputs
Rev 0.51

Features

◼
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Input Freq
Output Frequency
200 KHz -2.1 GHz
0.5 Hz - 2.94912 GHz
21 March 2025
PRELIMINARY
Ultra-high Performance PLLs
Fully Integrated design with no external components
Sub 70fs Typical RMS integrated jitter (12k-20M)
122.88M Output with excellent close in noise
performance
Fully Flexible Output and Input Mux: High level of
flexibility in output allocation for PLLs
JESD204B/C Support for data converter clocks
External EEPROM Support
Frequency Control DCO: DCO Control on all outputs
(down to 0.001 ppt)
Phase Control DCO: Fine phase adjustment knob for
phase of all outputs from a PLL (adjustment accuracy
< 1ps) in both closed loop and open loop modes
Repeatable input to output delays with output relative
delay adjust
Internal ZDB Mode with < 0.5 ns Input to Output delay
variation. Independently available for each PLL
Outputs can be phase aligned on independent sync
pulse
44 QFN 7 mm x 7 mm Package
RMS Jitter
~ 70 fs typ (QFN)
Packages
44 QFN
www.sitime.com

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Summary of Contents for SiTime SiT95210

  • Page 1: Description

    SiT95210 PRELIMINARY Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Description Features SiT95210 offers programmable Quad Fractional Frequency Ultra-high Performance PLLs ◼ translation-based jitter cleaning clock generator parts with Fully Integrated design with no external components ◼...
  • Page 2 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Input (LVCMOS/ Buffer Differential) Figure 1. Functional Overview Contact SiTime for MEMS Reference Clocks for best jitter. Rev 0.51 Page 2 of 74 www.sitime.com...

  • Page 3: Table Of Contents

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Table of Contents Description ....................................1 Applications ....................................1 Features ....................................... 1 Ordering Information ................................4 Electrical Characteristics ................................5 Functional Description ................................16 Master and Slaves: Architecture Description and Programming Procedures ................20 Overview of the programming procedure ..........................

  • Page 4: Ordering Information

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Ordering Information [1,2] Notes: 1. X = “A” and “B” customer device, “C” to “Z” reserved. a. A:Denotes blank devices; b. B: Denotes Pre-configured devices, contact SiTime for the specifics 2.

  • Page 5: Electrical Characteristics

    Description Conditions Symbol Units –40 – °C Ambient temperature °C Junction temperature +125 SiT95210 : 44 QFN Package Still Air Thermal Resistance θ °C/W Air Flow :1m/s Junction to Ambient Air Flow: 2m/s Thermal Resistance θ °C/W Junction to Case Thermal Resistance θ...
  • Page 6 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Description Conditions Symbol Units Supply Current All Four DE Inputs assumed to VDDIN DDIN be enabled Four PLLs and All 4 Outputs enabled LVPECL, output pair terminated 50 Ω to V...
  • Page 7 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Parameter Conditions Symbol Unit Reference Clock (Applied to X1), Can be external XO Range for best jitter Reference Clock Frequency IN_REF Overall supported range Input Voltage Swing...
  • Page 8 4. The SiT95210 chips provide a GPIO latching function that allows for certain GPIOs to function as latched GPIOs that are latched along with the release of chip reset (using the RSTB pin) and can the same pin is released for other functions in steady state.
  • Page 9 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator 5. The 0.001 ppt specification is for the smallest frequency step resolution available. Larger frequency step resolutions up to 100 ppm can be used also. The frequency resolution for the DCO mode frequency step is independently programmable for each DCO step.
  • Page 10 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Description Conditions Symbol Units Low Frequency Fundamental Crystal (LFF) Can be supported with a fundamental crystal > 25 MHz Crystal Frequency XTAL range. For Best Performance use an LFF crystal > 48 MHz...
  • Page 11 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator SiT95210 156.25 MHz Output (LVDS) with 48 MHz Crystal Table 10. Power Supply Rejection Description Conditions Symbol Units = 156.25 MHz, F SPUR 100 kHz, VDD = 1.8 V...
  • Page 12 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Table 12. Output Clock Specifications Descriptions Conditions Symbol Units DC Electrical Specifications – LVCMOS output (Complementary Out of Phase Outputs or One CMOS Output per Output Driver) Output High Voltage 4 mA load, VDD = 3.3 V...
  • Page 13 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Descriptions Conditions Symbol Units Measured at 156.25M Output (Programmable Programmable Output Typical Levels mentioned) differential peak CML DC Coupled True CML [1],[2] Coupled Output termination assumed. See foot note Measured at 156.25M...
  • Page 14 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 2. SiT95210 Pin Configuration Table 13. Pin Description Default Name I/O Type Voltage Level Description Pull Up/ Down -0.5V – 3.6 V IN1P Input Clock + for differential clock input. Single ended Input clock.
  • Page 15 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Default Name I/O Type Voltage Level Description Pull Up/ Down VDDIN (Pin 8) or VDD Serial Data Output (SPI 4 wire Interface). In I2C mode this is the...

  • Page 16: Functional Description

    Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Functional Description The SiT95210 is a clock generator device that offers four slaves) has an associated unique Page number. Each Page independent PLLs. The fully integrated part offers low has an independent 8 bit addressable PIF memory.
  • Page 17 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Input (LVCMOS/ Buffer Differential) Figure 3. SiT95210 Functional Block Diagram Rev 0.51 Page 17 of 74 www.sitime.com...
  • Page 18 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 4. Output Clock Distribution Input (fref) based Oscillator Figure 5. PLL Internals Note: Similar for all PLLs Rev 0.51 Page 18 of 74 www.sitime.com...
  • Page 19 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Table 14. PIF Description Page Contents Summary of contents All Generic Information related to the chip Chip Configuration details Master Control for the master sequencer FSM Input Reference Clock Related Information...

  • Page 20: Master And Slaves: Architecture Description And Programming Procedures

    Master and Slaves: Architecture Description and Programming Procedures Overview of the programming procedure The SiT95210 part can be programmed using different programmed with the desired configuration from the serial methods. The chip has a serial SPI/I2C port to access the SPI/I2C interface.
  • Page 21 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator chip configuration once the final configuration is determined the default mode for the cases where an autonomous wake and wake up of the entire chip is desired in this up is not desired.
  • Page 22 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 7. Slave Memory Structure The Master Wake-Up Finite State Machine (FSM) is shown Latching is disabled by default in SiT95210. GPIO latching in more detail in Figure 8. At every power up of the device...
  • Page 23 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Table 16. Default GPIO Configuration Default Default GPIO Default Function Description Direction Pull Up / Pull Down GPIO0 Input Weak Pull Down IN_SEL0 Manual Input Clock Select Bit0...
  • Page 24 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Auto Release master from reset by POR Latch GPIOs Copy NVM to volatile NVMCopy Copy volatile NVMCopy to Chip Settings Is EEPROM Access Available Read EEPROM Is EEPROM...
  • Page 25 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Release slave from reset Copy NVM to volatile NVMCopy Copy volatile NVMCopy to slave settings Is EEPROM Access Available? Update slave settings from EEPROM Escape to PRG...

  • Page 26: Gpio Latching

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator GPIO Latching GPIO Latching is used to configure the chip during wakeup. modes. Latched value of GPIOs will be decoded later when GPIO latching is disabled as default factory settings and NVM contents are copied to Chip Settings.

  • Page 27: Status Vs Notify Available On The Chip

    Status vs Notify available on the Chip SiT95210. GPIO latching and its corresponding latching SiT95210 provides various Status and notify bits that can functions are factory programmed by SiTime with non 00 be accessed from the register map. Below are the details of code marking.

  • Page 28: Gpio Modes During Regular Operation

    Manual Clock Select: GPIO can be used as mode GPIO will act as EEPROM read done manual clock selection for PLLs. Indicator to indicate that EEPROM read is done and SiT95210 became the slave. Clock Disqualification: GPIO External micro controller can check the...

  • Page 29: Configuring The Device From External Eeprom

    CRC, then all defect flags will be de-asserted C mode, SiT95210 tries to read the configuration block and EEPROM read done indication will be sent out on the from EEPROM configured GPIO.
  • Page 30 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator word_address EEPROM data size Page Register Address Page Register Data Page Register Address Page Register Data CRC ID crc[3] crc[2] crc[1] crc[0] 0x01FFF 0x02000 Device ID 0x02001...
  • Page 31 14000 16000 18000 1A000 1C000 1E000 • Page Register Address & Page Register Data: Device ID: Device ID field indicates to which SiT95210 device this Page Register Address contains register configuration block belongs. This device id will be read address...

  • Page 32: Input Reference Clock Connectivity Options

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Input Reference Clock Connectivity Options The CMOS XO/TCXO output and the termination components should be placed as close as possible to the X1/X2 pins [OPTIONAL] Figure 10. Crystal Connections Rev 0.51...
  • Page 33 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 11. CMOS XO Connections CMOS XO Driver Supply R1 (Ohms) R2 (Ohms) 1.8 V 2.5 V 3.3 V Figure 12. Differential XO Connections Rev 0.51 Page 33 of 74...

  • Page 34: Input Slave Description

    SiT95210 are shown in this section. be routed to PLLs with complete flexibility. Apart from the above given interface examples, SiT95210 Both single ended and AC coupled differential clock inputs differential input buffer can accept 3.3 V/2.5 V domain are possible.
  • Page 35 SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 14. SiT95210 4 Diff/8 SE Input Drivers Figure 15. Input Buffer Structure Note: DE – Differential Buffer; SEP – Single Ended Buffer at CLKP; SEN – Single Ended Buffer at CLKN Rev 0.51...
  • Page 36 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Driver Supply R1 (ohm) R2 (ohm) 1.8 V 2.5 V 3.3 V Rs is resistance to match Ro_driver + Rs = 50 ohm Figure 16. Interface Type-I: Single Ended DC Coupled Rev 0.51...
  • Page 37 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 17. Interface Type II Single Ended Direct AC Coupled Rev 0.51 Page 37 of 74 www.sitime.com...
  • Page 38 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 18 Interface Type III SE AC Coupled with 50-ohm termination Figure 19 Interface Type IV Differential AC Coupled 4A Figure 20 Interface Type IV Differential AC Coupled 4B Rev 0.51...
  • Page 39 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 21 Interface Type IV Differential AC Coupled 4C Figure 22 Interface Type V Differential DC Coupled 5A Figure 23 Interface Type V Differential DC Coupled 5B Rev 0.51...

  • Page 40: Clock Monitor Slave Description

    (or recovery from a fault monitoring indicators. There are 4 categories of clock clock loss) is programmable in the SiT95210 GUI interface monitoring that are necessary for the chip namely: Clock allowing for flexibility in choosing these thresholds. In addition there is a programmable “Wait Time”...

  • Page 41: Frequency Drift Monitors

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Coarse Frequency Drift has an implicit hysteresis with Frequency Drift Monitors resolution of ±100 ppm since the same range is available Frequency Drift monitors frequency drift of a particular clock for the FD assertion and de-assertion.

  • Page 42: Pll Slave Description

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator PLL Slave Description is determined by the relation fVCOx = DIVNx*fref. This is All settings with respect to each PLLx slave (x ϵ {A, B, C, the mode of operation before the loop is locked to the D}) are accessible on the respective Page {A, B, C, D}.

  • Page 43: Mode Of Operations

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 25. Basic DLPF Block Diagram Mode of Operations Basic Mode of Operation In this mode, the digitized phase information is conditioned done. The conditioned signal is applied as a correction to by the low-pass filters, decimated and passed through the the programmed division control word (DIVN).

  • Page 44: Dco Increment/Decrement Mode

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator DCO Increment/Decrement Mode This mode is useful to steer the clock frequency up or down, in small increments or decrements. The DCO increment/decrement path for the inner loop is highlighted in the figure below. A similar path also exists for the outer-loop and will be explained later.

  • Page 45: Outer-Loop Dco Increment/Decrement Path Architecture

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Zero Delay Mode Outer-Loop DCO increment/decrement path architecture There are two independent Zero Delay Mode/Buffer (ZDM/B) are supported on each PLL i.e. External and The outer-loop increment/decrement path has a similar Internal.

  • Page 46: Output Slave Description

    Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Output Slave Description Figure 29. SiT95210 Output Drivers Several Terminations are available for the SiT95210 parts Output Driver which serve several industry standards. ◼ SiT95210 parts offer programmable output swing for the various termination arrangements.

  • Page 47: Regular High Swing Modes

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 30. Waveform Convention Regular High Swing modes Differential Output Drivers: Regular High Swing Modes Figure 31. Output Driver used with traditional DC Coupled LVDS receiver Supported Swing: →...
  • Page 48 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 32. Output Driver used with traditional LVPECL DC Coupled receiver (DC Termination to VDDO - 2V) Figure 33. Output Driver used with AC Coupled terminations for various receivers Supported Swing: →...
  • Page 49 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 34. Output Driver used with traditional DC Coupled CML receiver Supported Swing: → 0.05V to 0.4V Differential Peak Swing Differential Peak Swing Step Size → 50mV Figure 35.

  • Page 50: Internal Termination Modes

    Differential Peak Swing Differential Peak Swing Step Size → 50mV Internal Termination modes SiT95210 support differential 100Ω internal termination in LVDS mode. ◼ If the receiver is correctly terminated, internal termination is not recommended The internal termination is recommended for cases where transmission line integrity or far end termination is not robust.
  • Page 51 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 38. Output Driver used with AC Coupled terminations for various receivers Supported Swing with far end termination: → 0.05V to 0.4V Differential Peak Swing Differential Peak Swing Step Size → 50mV Supported Swing without far end termination: →...

  • Page 52: Output Clock Modes

    Output Clock Modes SiT95210 can provide 4 differential clocks or 8 pair of single ended clocks. These output clocks can be programmed differently to serve different applications at system level. This document explains output clock behavior in different functional modes of operations.

  • Page 53: Sysref Mode With Pulser

    This is done to reduce cross-talk between SYSREF and programmed for 3 pulses. DEVICE clock. In SiT95210, sysref clocks can be programmed in pulser mode of operation too. There are 8- bits independent to each sysref clock to program number of output pulses from 1 to 255.

  • Page 54: Serial Programming Interface Description

    GPIO is latched as 1 and decoded as EEPROM EEPROM, and I2C(slave) and SPI(slave) serial interface access disable, and serial interface is configured to I2C protocols, for reconfiguring the device settings using mode, SiT95210 tries to read the configuration block from register read/write. EEPROM. Serial Interface Pins To read the configuration data from the external I2C Following pins of the device are used as a Serial Interface.

  • Page 55: Clock Synchronization

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Figure 42. EEPROM read In I2C master mode device supports following I2C features. I2C master is compliant with 100 KHz and 400 KHz I2C interface. ◼ Supports 7 bit I2C bus address. .

  • Page 56: Arbitration

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Arbitration Arbitration refers to a portion of the protocol required only if Two masters can actually complete an entire transaction more than two masters are used in the system. Two without error, as long as the transmission is identical.

  • Page 57: Start Byte

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Start Byte can be preceded by a start procedure which is much longer Microcontrollers can be connected to the I2C-bus in two than normal (please see Figure 45).
  • Page 58 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Read Operation - Single Byte Slave Addr [6:0] Reg Addr [7:0] Slave Addr [6:0] Data [7:0] Read Operation - Burst (Auto Address Increment) Slave Addr [6:0] Reg Addr [7:0]...

  • Page 59: Single Byte Write

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Single Byte Write The master initiates the transaction by issuing a start condition, writes 7-bit slave address and then the read/write bit is written as 0 (write)

  • Page 60: I2C Bus Timing Specifications

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator I2C Bus Timing Specifications Table 21. I2C bus Timing Specifications Standard Mode Fast Mode Description Symbol Units – – SCLK clock frequency – – µs Hold time START condition HD:STA –...

  • Page 61: Spi Protocol

    Select (CSB), Serial Input/Output (SDIO) and Serial Clock clock and the slave in the SiT95210 captures the (SCLK) pins. SDIO pin acts as an input when receiving data same on the rising edge of the SPI clock. For...

  • Page 62: Spi Timing Specifications

    SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator In SiT95210 the transmitter always sends data on In a 4-wire mode of operation, the output data bit the falling edge of the SPI clock to be captured in slave is controlled only when transmitting the read the receiver by the rising edge of the SPI clock.

  • Page 63: Spi Single Byte Write

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator SPI Single byte write The master initiates the transaction by issuing a start condition by pulling csb_i to active low ◼ The master assembles the serial data on the falling edge of the SPI clock so the SPI slave can capture the same ◼...

  • Page 64: Spi Burst Write

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator SPI Burst write The master initiates the transaction by issuing a start condition by pulling csb_i to active low ◼ The master assembles the serial data on the falling edge of the SPI clock so the SPI slave can capture the same ◼...

  • Page 65: Spi Incremental Byte Read

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator SPI Incremental byte Read The master initiates the transaction by issuing a start condition by pulling csb_i to active low ◼ The master assembles the serial data on the falling edge of the SPI clock so the SPI slave can capture the same on the ◼...

  • Page 66: Monitoring Through The Register Map Read Back: Status And Notify

    Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Monitoring through the register map read back: Status and Notify SiT95210 provides various Status and notify bits that can when status toggles. The default value for the mask register is 0xff so all the notify signals are enabled.
  • Page 67 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Status Register Notify Register Mask Register Sr No Name of Signal Description Register Register Register Address Address Address eeprom_ctrl_eeprom_read_done eeprom ctrl eeprom read done eeprom_ctrl_crc_deft eeprom ctrl crc defect...

  • Page 68: Examples For Live Status Read Back

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Status Register Notify Register Mask Register Sr No Name of Signal Description Register Register Register Address Address Address clk_in1n_loss clk in1n loss clk_in1n_loss_with_FD clk in1n loss with FD...
  • Page 69 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Holdover Status pll_ho_freeze_dyn_status = rd_cmd(0x0a) & 0xff (pll_ho_freeze_dyn_status >> 0) & 0x01 PLLA Status for HO, Read bit position [0] (pll_ho_freeze_dyn_status >> 1) & 0x01 PLLB Status for HO, Read bit position [1] (pll_ho_freeze_dyn_status >>...
  • Page 70 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator data rmw_cmd(addr,bit_loc,no_of_bits,data) def clr_intrb(): This is the main clear function which calls the 4 clear functions clr_intb_CMON_IN0P() clr_intb_PLL_OUTER_LOL() clr_intb_PLL_HO() clr_intb_XO_CL() Rev 0.51 Page 70 of 74 www.sitime.com...

  • Page 71: Package Information

    PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator Package Information Figure 54. Package Diagram (44 QFN) Rev 0.51 Page 71 of 74 www.sitime.com...
  • Page 72 PRELIMINARY SiT95210 Ultra Low Jitter, Programmable Frequency, 4 Outputs Quad PLL Clock Generator General Notes 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication Allowance of 0.05 mm.
  • Page 73 1st X indicates the device revision code such as rev B, C…etc, empty/blank indicate rev A​ • “-XXXXXX” indicates specific custom configuration code, empty for non-programmable devices.​ • Line 3: “LLLLL”, Lot code from SiTime Line 4: Pin 1 dot and “SiTime” logo Rev 0.51 Page 73 of 74 www.sitime.com...
  • Page 74 © SiTime Corporation 2024-2025. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.

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