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DATE
REVISION
CHANGE DESCRIPTION
11/04/2023
1.0.0
Release
27/07/2023
1.0.1
Updated pinout (Rev.A), updated chapter "How to connect the reset pin"
24/08/2023
1.0.2
Updated marking code on Ordering Information chapter
14/12/2023
1.0.3
Fixed typo errors on multiplexing chapter
11/01/2024
1.0.4
Improved module pinout, improved multiplexing chapter
19/04/2024
1.0.5
Updated ordering info
04/02/2025
1.0.6
Upgraded ordering info, corrected typos on Ethernet Chapter
15/04/2025
1.0.7
Updated module pinout
.Core MX93 HW Manual
i
Getting started manual
Revision History
1
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Table of Contents
Summary of Contents for ENGICAM i.Core MX93 FULL 2GB NPU
- Page 1 .Core MX93 HW Manual Getting started manual Revision History DATE REVISION CHANGE DESCRIPTION 11/04/2023 1.0.0 Release 27/07/2023 1.0.1 Updated pinout (Rev.A), updated chapter “How to connect the reset pin” 24/08/2023 1.0.2 Updated marking code on Ordering Information chapter 14/12/2023 1.0.3 Fixed typo errors on multiplexing chapter 11/01/2024 1.0.4...
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Page 2: Table Of Contents
Table of Contents INTRODUCTION ........................................... 4 ........................................5 ENERAL NFORMATION M ..........................................6 LOCK IAGRA ..........................................7 EATURES ....................................7 OCUMENT AND TANDARD EFERENCES 1.4.1 External Industry Standard Documents ........................................7 1.4.2 Other external documents ............................................. 7 1.4.3 On-line documentation ..............................................7 ............................................ - Page 3 ....................................47 ERIPHERAL MULTIPLEXING DESCRIPTION 6.1.1 Alternative SPI Configuration ............................................47 6.1.2 alternative IC Configuration ............................................48 6.1.3 Alternative UART pins tables ............................................49 6.1.4 alternative CAN bus interface ............................................50 6.1.5 alternative PWM pins table ............................................51 CARRIER BOARD RECOMMENDED SPECIFICATIONS ................................52 ......................................
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Page 4: Introduction
CHAPTER 1 Introduction This Chapter gives background information on this document. Section includes： General Overview ✔ Acronyms and Abbreviations Used ✔ Document and Standard References ✔... -
Page 5: General Information
All examples of this document are based on carrier board that is available from ENGICAM. This document also provides a collection of... -
Page 6: Block Diagram
1.2 Block Diagram... -
Page 7: Main Features
Engicam explicitly reserves the rights to change or add to the contents of this manual or parts of it without special notification. All operating parameters must be validated for each customer application by customer’s technical experts. -
Page 8: Support
We offer on-line support to allow the customer to stay updated on the development of software release and on the enhancement of the documentation. Following is shown the references for ENGICAM on-line support. www.engicam.com ENGICAM Product Experts are available to answer questions via email: support@engicam.com Engicam s.r.l. Via Ilio Barontini, 5/3 50018 Scandicci (Florence) Italy Tel. -
Page 9: Acronyms And Abbreviations Used
1.7 Acronyms and Abbreviations used ABBREVIATION EXPLANATION Analogue to Digital Converter Controller Area Network, a bus that is manly used in automotive and industrial environment Central Processor Unit Digital to Analogue Converter Electromagnetic Interference, high frequency disturbances eMMC Embedded Multi Media Card, flash memory combined with MMC interface controller in a BGA package, used as internal flash memory Electrostatic Discharge, high voltage spike or spark that can damage electrostatic- sensitive devices... -
Page 10: Mechanical Data
CHAPTER 2 2. Mechanical data This Chapter gives information about PCB and module's dimensions. Section includes： Assembly Top View ✔ ✔ Assembly Bottom View Mechanical data ✔... -
Page 11: Echanical Data
2.1 Mechanical data The i.MX 93 module has a standard SO DIMM footprint compliant with TYCO ELECTRONICS code 1473005-1 or compatible connector. The PCB dimensions is L 67.60 x W 32 x H 1 mm. The distances available on PCB under the module are from 1 to 1.4 mm. 2.2 Assembly Top View Figure 1 2.3 Assembly Bottom View... -
Page 12: Ordering Information And Features
CHAPTER 3 3. Ordering Information and Features This Chapter gives the ordering information and technical specifications of the modules. Section includes： i.CoreMX93 ordering codes ✔ CPU & Memory specification ✔ Operating temperature range ✔ i.CoreMX93 supported features ✔... -
Page 13: Ordering Information
CPU & Memory specifications Operating temperature Module available at least until range °C (excepted CPU) i.Core MX93 FULL 2GB NPU 002682035NI55B EDIMM 2.0, i.MX 93 Dual Cortex-A55@1700MHz industrial temperature dual Cortex-A55 MIMX9352 ARM Ethos U-65 and Cortex-M33@250MHz, 2GB LPDDR4, 8GB micro NPU, -40 to +105C , 8GB eMMC -25°C,... -
Page 14: Part Number Structure
3.2 Part Number Structure The module is available with eMMC option. The standard order codes shown in the tables above shall be modified as follow: 0026 Revision RAM size 512MB Option available Single Gb Ethernet Non volatile memory specification Dual Gb Ethernet 256MB SLC NAND 512MB SLC NAND 4GB eMMC... -
Page 15: Pinout And Electrical Specifications
CHAPTER 4 4. Pinout and Electrical Specifications This Chapter gives the pinout information. Section includes： Pinout overview ✔ Pad specifications ✔ Electrical specifications ✔... -
Page 16: Module Pinout
4.1 Module Pinout The module's interface is achieved by a SODIMM 200 position connector TYCO ELECTRONICS code 1473005-1 or compatible Name Pin Name on i.MX 93 Primary Function Description GPIO Voltage Capable +1V8 Output Power PIN +1V8 Output Power PIN Power PIN Power PIN Power PIN... - Page 17 Name Pin Name on i.MX 93 Primary Function Description GPIO Voltage Capable LVDS0_TX3_P LVDS0_D3_P LVDS Interface's Signals MIPI_DSI_D2_P MIPI_DSI1_D2_P MIPI_DSI LVDS0_TX3_N LVDS_D3_N LVDS Interface's Signals LVDS0_CLK_P LVDS_CLK_P LVDS Interface's Signals MIPI_DSI_D3_N MIPI_DSI1_D3_N MIPI_DSI LVDS0_CLK_N LVDS_CLK_N LVDS Interface's Signals MIPI_DSI_D3_P MIPI_DSI1_D3_P MIPI_DSI LVDS0_TX1_P LVDS_D1_P...
- Page 18 Name Pin Name on i.MX 93 Primary Function Description GPIO Voltage Capable UART2_TXD UART2_TXD UART TX DATA signal +3,3V UART2_RXD UART2_RXD UART RX DATA signal +3,3V Power PIN MIPI_CSI1_D0_P MIPI_CSI1_D0_P MIPI_CSI -(MIPI Camera Serial Interface) MIPI_CSI1_D0_N MIPI_CSI1_D0_N MIPI_CSI - (MIPI Camera Serial Interface) N MIPI_CSI1_CLK_P MIPI_CSI1_CLK_P MIPI_CSI - (MIPI Camera Serial Interface) N...
- Page 19 Name Pin Name on i.MX 93 Primary Function Description GPIO Voltage Capable ETH_TXRXM_B Ethernet signal GPIO_IO05 GPIO_IO05 Generic PWM +3,3V ETH_TXRXP_B Ethernet signal +3V3_OUT Output Power PIN +3V3_OUT Output Power PIN ETH2_TXRXP_A ENET2_TXC Ethernet signal ETH_nLINK Ethernet signal ETH2_TXRXM_A ENET2_TX_CTL Ethernet signal ETH_nACT Link/Activity LED...
- Page 20 Name Pin Name on i.MX 93 Primary Function Description GPIO Voltage Capable JTAG_TDO DAP_TDO_TRACESWO JTAG Interface +1,8V JTAG_TDI DAP_TDI JTAG Interface +1,8V JTAG_TMS DAP_TMS_SWDIO JTAG Interface +1,8V JTAG_TCK DAP_TCLK_SWCLK JTAG Interface +1,8V TAMPER1 TAMPER1 +3,3V TAMPER0 TAMPER0 +3,3V USB2_VBUS USB2_VBUS BOOT_MODE UART2_TXD Boot from USB/UART or Memory device...
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Page 21: Electrical Specifications
4.2 Electrical specifications 4.2.1 Operating Ranges V Min (Volts) V Typ (Volts) V Max (Volts) Vin 1) + 5,25 VBUS_USB (180, 195) + 5,25 GPIO V(oh) + 2,6 + 3,3 GPIO V(ol) + 0,6 GPIO V(ih) + 2,3 + 3,6 GPIO V(il) + 0,9 GPIO V(oh... -
Page 22: Module Interfaces
CHAPTER 5 5. Module Interfaces This Chapter gives the technical specifications for carrier board design. Section includes： Power signals and backup battery ✔ Serials ✔ CAN Bus ✔ Ethernet ✔ ✔ SDIO ✔ LVDS ✔ MIPI DSI ✔ MIPI CSI ✔... -
Page 23: How To Power The I .Core Module
5.1 How to power the i.CoreMX93 module Read carefully the related sections before starting the power stage design. This module needs to be supplied up to +5Vin power. Please refer to the table below for the power supply range specification. The power dissipated by the module in the operating mode is up to 600 mA, but the system must provide at least a power of 2A at 5V to allow the start of the module. - Page 24 The following table shows the nominal maximum rating of power output: Power output Max output current +1V8 +3V3_OUT Table 7 For further details on the power supply refer to "i.MX 93" data sheet and Reference Manual...
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Page 25: How To Connect Two 3-Wire Rs232 Serial Port
5.2 How to connect two 3-wire RS232 serial port This section shows how to use the i.MX 93 UARTs as 3-wire RS232 serial ports. The table shows involved UARTs and the associated pins: Number Name Primary Function GPIO Capable Voltage Description UART2_TXD UART TXD signal... -
Page 26: How To Connect Ars485 Serial Port
5.3 How to connect a RS485 serial port This chapter shows how an RS485 serial port can be connected to the module. The figure below shows how UART is connected to the RS485 transceiver. Figure 4 The pins involved in this RS485 communication in standard EDIMM specs are listed in the following table. Number Name Primary Function... -
Page 27: How To Connect Can Bus Interfaces
5.4 How to connect CAN BUS interfaces This chapter describes how CAN bus transceiver can be connected to the i.MX 93 module. Figure 5 The following table describes the pins' numbering in the main connector involved in the CAN interface Number Name Primary Function... -
Page 28: How To Design The Ethernet Interface
5.5 How to design the Ethernet interface The NXP i.MX 93 Mini Ethernet Media Access Controller (MAC) is designed to support 10/100/1000 Mbps Ethernet/IEEE ® standard 802.3™ networks. Figure 6 The table below lists all Ethernet signals of the module. Number Name Primary Function Description... -
Page 29: Double Ethernet Option (One Phy On Board And One Rgmii)
Number Name Primary Function Description GPIO Voltage Capable signal (TX-) for MDI-X configuration ETH2_TXRXM_B Negative receive signal (RX+) for MDI configuration and the negative +3,3V transmit signal (TX+) for MDI-X configuration ETH2_TXRXP_C BI_DC+ for MDI configuration and BI_DD+ for MDI-X configuration +3,3V ETH2_TXRXM_C BI_DC- for MDI configuration and BI_DD- for MDI-X configuration... -
Page 30: Component Placement Considerations
5.5.2 Component Placement considerations Components placement can affect signal quality, emissions and can decrease EMI problems. If the magnetics are a discrete component than the distance from the connector RJ45 should be kept to under 25mm of separation. To decrease EMI problems the distance between magnetics and Phy should be at least 25mm or greater to isolate the PHY from magnetics. -
Page 31: Cable Transient Event And Phy Protection
5.5.3 Cable Transient Event and PHY Protection Cable transient events are + and - DC surges that are induced across the transformer onto the PHY side of the TX+/- and RX+/- signals as shown in figure below. The PHY side of the transformer should not contain any DC component other than the typical 3.3V pull-up on the center tap of the transformer for analog signal biasing. -
Page 32: Usb Interface
5.6 USB interface Warning! The schematics in chapters below are generic, please refer to the signals in the table. 5.6.1 How to connect the USB OTG interface The NXP i.MX 93 USB module provides high performance USB On-The-Go (up to 480Mbps), compatible with the USB ®... - Page 33 Use of the USB OTG port as a Host with its own dedicated supply. The ID signal is forced to GND Figure 10 Use of the USB OTG port as Device. Figure 11...
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Page 34: How To Connect The Usb Host Interface
5.6.2 How to connect the USB host interface The module provides one port for USB host interface. The figure shows how to connect this port to the Module. Figure 12 It's possible to multiply the USB ports available by equipping the carrier board with a USB HUB. If only one port is needed it's possible to connect the USB_D (M/P) signals shown in the figure, directly to the module on pin 194-196 of the main connector. -
Page 35: How To Connect The Sd Card Interface
5.7 How to connect the SD CARD interface The NXP i.MX 93 Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host system ® and MMC/SD/SDIO/CE-ATA cards, including cards with reduced size or mini cards. The module includes these features and the figure shows how the Micro SD Card connector is connected to i.MX 93 Module in the evaluation board. -
Page 36: Lvds Interfaces
5.8 LVDS Interfaces The i.Core MX93 SOM is equipped with LVDS interfaces, available up to 24 bit data connection. The LVDS ports may be used as follows: • One single-channel output Following the LVDS interfaces maps and schemes Number Name Primary Function Description GPIO Capable Voltage... -
Page 37: Lvds Routing And Placement Considerations
5.8.1 LVDS Routing and Placement Considerations The LVDS lines are high-speed signals and as such during the designing must be complied with standards of protection against noise and crosstalk. In this chapter we give some advices about positioning, cabling and routing; for further details follow the guidelines and the manuals about LVDS bus. -
Page 38: Mipi Dsi Interface
5.9 MIPI DSI Interface MIPI DSI interface is a specification of the Mobile Industries Processor Interface (MIPI) Alliance (see http://mipi.org for details). The i.Core MX93 is equipped with one instance of 4-lane MIPI DSI interface. Number Name Primary Function Description GPIO Capable Voltage MIPI_DSI_D3_P... -
Page 39: Mipi Csi Interface
5.10 MIPI CSI Interface MIPI CSI interface is a specification of the Mobile Industries Processor Interface (MIPI) Alliance (see http://mipi.org for details). The i.CoreMX93 is equipped with an instance of 2-lane MIPI CSI interface. Number Name Primary Function Description GPIO Capable Voltage MIPI_CSI1_D0_P MIPI_CSI - (MIPI Camera Serial Interface) -
Page 40: Jtag Interface
5.11 JTAG Interface Joint Test Action Group (JTAG) is the common name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan. JTAG is often used as an IC debug or probing port. There are no official standards for JTAG adapter physical connectors. -
Page 41: Boot Mode Pin
5.12 Boot Mode Pin Boot mode pin determines how the module boot. The following table listed the possible options of the boot mode: BOOT_MODE Action Boot from memory devices Boot from Serial Table 22 The boot from Serial is usually used for the boot loader deploy, for further information referring to the i.MX RM. Note : Pin 86 and pin 116 must be floating or high impedance on booting. - Page 42 5.12.1 Boot Signals Management Following is shown the signals to be regarded during boot sequence. These signals must be floating or high impedance. Pin Number Signal Name Pin Name on i.MX93 UART2_TXD UART2_TXD UART1_TXD UART1_TXD...
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Page 43: How To Connect The Audio Interface
5.13 How to connect the Audio Interface i.Core MX93 is equipped with a SAI (Synchronous Audio Interface) that can be connected with a standard audio codec device. The figure below shows connection with a Low Power Stereo Codec using the module signals interface. Figure 18 The following table lists the I2S BUS pins numbering Number... -
Page 44: How To Connect The Reset Pin
5.14 How to connect the reset pin The reset pin is a reset input for the SOM and it is managed by the on board PMIC. By default an active state on reset signal causes a COLD reset with a complete new power sequence (power off fol- lowed by a new power on). -
Page 45: Adc Option
5.15 ADC Option The i.MX 93 module does not include ADC, but can be optional. Number Name Primary Function Description GPIO Capable Voltage OPT_ADC_IN0 ADC_IN0 +1.8V OPT_ADC_IN1 ADC_IN1 +1.8V OPT_ADC_IN2 ADC_IN2 +1.8V OPT_ADC_IN3 ADC_IN3 +1.8V Table 27 ADC 1.8V OPTION on REQUEST... -
Page 46: Peripheral Multiplexing
CHAPTER 6 6. Peripheral multiplexing This Chapter gives the alternative peripheral information Section includes： ✔ ✔ UART ✔ ✔... -
Page 47: Peripheral Multiplexing Description
6.1 Peripheral multiplexing description In the following we describe opportunity to use alternative interfaces using the properties of multiplexing pin. Refer to the NXP ® 's reference manual and documentation for further details. 6.1.1 Alternative SPI Configuration Using pin multiplexing 's features we may have the following SPI and IIS connections. The tables below show the output signals on the Connector's module. -
Page 48: Alternative Ic Configuration
SPI6 signals interfaces +3,3V Pin number Pin Name on i.MX 93 Signal reference Voltage reference GPIO_IO02 MOSI +3,3V GPIO_IO01 MISO +3,3V GPIO_IO03 +3,3V GPIO_IO00 +3,3V GPIO_IO24 +3,3V Table 32 SPI7 signals interfaces +3,3V Pin number Pin Name on i.MX 93 Signal reference Voltage reference GPIO_IO06... -
Page 49: Alternative Uart Pins Tables
IIC5 interfaces Pin number Pin Name on i.MX 93 Signal reference Voltage reference 12/ 109 GPIO_IO23/ GPIO_IO01 +3,3V 11/ 108 GPIO_IO22 / GPIO_IO00 +3,3V Table 36 IIC6 interfaces Pin number Pin Name on i.MX 93 Signal reference Voltage reference 105/ 132 GPIO_IO03/ GPIO_IO05 +3,3V 106/ 184... -
Page 50: Alternative Can Bus Interface
UART6 interfaces Pin number Pin Name on i.MX 93 Signal reference Voltage reference GPIO_IO04 UART6_TXD +3,3V GPIO_IO05 UART6_RXD +3,3V GPIO_IO06 UART6_CTS_B +3,3V GPIO_IO07 UART6_RTS_B +3,3V Table 43 UART7 interfaces Pin number Pin Name on i.MX 93 Signal reference Voltage reference GPIO_IO08 UART7_TXD +3,3V... -
Page 51: Alternative Pwm Pins Table
6.1.5 alternative PWM pins table It's possible to set the pins shown in the tables as PWM signals. Pin number Pin Name on i.MX 93 MicroGEA Signal reference Voltage reference 113/ 117 UART1_RXD / UART1_RXD TPM1_CH0 +3,3V 112/116 UART1_TXD / UART1_TXD TPM1_CH1 +3,3V UART2_RXD... -
Page 52: Carrier Board Recommended Specifications
CHAPTER 7 7. Carrier board recommended specifications Following are the specifications required for the carrier board to avoid problems in the assembly process. The module is interfaced with the carrier board through a SO-DIMM with 200 positions connector type TYCO ELECTRONICS code 1473005-1 or compatible. -
Page 53: Product Compliance
CHAPTER 8 Product Compliance In order to respect own internal policy regarding the environmental regulations and safety laws, Engicam in this chapter confirms the compliance, when applicable, of its own products to the normative ROHS and REACH and to the recognized hazards.
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