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Fairlight MFX3 Plus Service Manual

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Service Manual
Software Version 14 & 15
Part Number: MANMFXSERP
Document Number: #129
Copyright © June 1999
Ref: MFX3plusServiceManual12.p65

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Summary of Contents for Fairlight MFX3 Plus

  • Page 1 Service Manual Software Version 14 & 15 Part Number: MANMFXSERP Document Number: #129 Copyright © June 1999 Ref: MFX3plusServiceManual12.p65...
  • Page 2 © 1996 - 1999 Fairlight ESP Pty. Limited. MFX3 plus Service Manual...

  • Page 3: Table Of Contents

    ONTENTS 1. I ................ 13 NTRODUCTION 1.1 Important Notice ..............13 1.2 Document Registration ............13 1.3 Important Information............. 14 1.3.1 EMC Standards .............. 14 1.3.2 Fuse Ratings ..............14 1.3.3 Mains Cables..............14 1.3.4 Cleaning ................ 14 2.0 P &...
  • Page 4 8.0 O ..........37 BTAINING ECHNICAL UPPORT 8.1 Internet ................... 37 8.2 On-Line Technical Support ............ 38 8.3 Technical Support Leaflets ............. 38 8.4 ECN Updates ................. 38 8.5 FTP Site .................. 39 8.5.1 Introduction ..............39 8.5.2 Equipment and Software ..........39 8.5.3 File transfer using Windows FTP ........
  • Page 5 10.4.10 Edge Connectors to ESPPCI ........86 10.4.11 Digital Edge Connector ..........87 11.0 ESPCG4 C ........... 89 OLOR RAPHICS 11.1 ESPCG4 Block Diagram ............90 11.2 ESPCG4 Circuit Description ..........91 11.2.1 Document Revision ............. 91 11.2.2 Terminology..............91 11.2.3 Introduction ..............
  • Page 6 12.4 ESPPCI DSP Field Diagnostics ......... 125 12.4.1 Introduction ............... 125 12.4.2 System requirements ..........125 12.4.3 Running the diagnostics ..........125 12.4.4 Command Details ............. 126 12.5 ESPPCI Schematics ............127 12.5.1 ESPPCI Interconnecting Diagram ......127 12.5.2 Edge Connection to ESPWX ........128 12.5.3 CPU to PCI Interface ..........
  • Page 7 14.4 ESPDCC Field Diagnostics ..........165 14.4.1 Diagnostic test procedure ......... 166 14.4.2 ESPDCC Diagnostic Program ........166 14.4.3 DCC PLL Adjustment ..........167 14.4.4 DCC Led Indicators ........... 168 14.4.5 DCC Debug Masks ........... 168 14.5 ESPDCC Schematics............169 14.5.1 ESPDCC Interconnecting Diagram ......
  • Page 8 17.2.1 66MHz PLL .............. 231 17.2.2 256x Wordclock crystals .......... 232 17.2.3 LED Indicators ............232 17.2.4 Shared memory ............232 17.2.5 Sync card Test ............233 17.2.6 System tests ............... 234 17.3 ESPSYN Sync Card Schematics ......... 235 18.0 ESPMIDI MIDI I/O C ..........
  • Page 9 20.2.5 AES Sync Generation ..........289 20.2.6 AES Sync Reception ..........289 20.2.7 AES Sync Frequency ..........290 20.2.8 Diagnostic Description ..........290 20.3 ESPLTC Schematic ............. 291 21.0 ESP9PIN 9P ............293 21.1 Block Diagram ..............294 21.2 Diagnostics ................ 295 21.2.1 Running Diagnostics ..........
  • Page 10 25.1.6 LED Circuitry ............332 25.1.7 Clocks ............... 332 25.1.8 Watchdog ..............332 25.1.9 Displays ..............333 25.1.10 DUARTs ..............333 25.1.11 AC1A1 ..............334 25.1.12 ACIA2 ..............334 25.1.13 ACIA3 ..............334 25.1.14 ACIA4 ..............334 25.1.15 Speaker ..............335 25.1.16 Key scanning ............
  • Page 11 28.1.2 FLFS ................386 28.1.3 MDR-DOS ..............386 28.1.4 HFS ................387 28.1.5 FAT-16 ............... 388 29.0 M ............... 391 EDIA 29.1 Media Link Software – Description ........391 29.2 Media Link Software - Fairlight NT Applications ....392 Table of Contents...
  • Page 12 30.0 A ............... 393 PPENDICES 30.1 MFX3 Level Modification ..........393 30.1.1 Standard settings ............393 30.1.2 Settings for other standards ........394 30.2 Error Codes ................ 395 30.3 Blue Key Reference ............411 30.4 OS/9 Commands ..............412 30.5 ECNs .................. 424 MFX3 plus Service Manual...

  • Page 13: Introduction

    In no event will Fairlight ESP Pty Ltd be liable for direct or indirect damages arising from any defect in the software or its documentation. Further, Fairlight ESP Pty Ltd will not accept any liability for any programs, sounds, audio recording or sequences stored in or used with Fairlight products, including the cost of recovery of such data.

  • Page 14: Important Information

    1.3.1 EMC S TANDARDS plus plus The Fairlight MFX 3 Rack and MFX3 Console conform to EMC Directive 89/336/EEC standard, Class A EN55022 EN50082.1.1995, and may affect domestic electronic equipment. Installers should be aware of the requirements under the EMC Directive that complete installations must conform to the specification and not just the individual pieces of equipment.

  • Page 15: Pre -Installation & Cabling Considerations

    & C NSTALLATION ABLING ONSIDERATIONS The following information is presented to ensure a smooth and timely installation and plus commissioning of the Fairlight MFX3 system. 2.1 P NSTALLATION HECKLIST • Is all relevant building work completed ie. timber, concrete, plaster, brickwork? Building work is a source of dust and moisture, both which can seriously affect system operation and reliability.

  • Page 16: Cabling Considerations

    15-way shielded 50 Ohm cable with high density D-type connectors at each end. A maximum length of 20 metres is typical. The Fairlight Mainframe is supplied with a 10 metre cable which has been found to be suitable for the majority of monitors. An optional modified SVGA buffer unit may be used to extend the cable lenght if necessary.
  • Page 17 2.2.5 LTC C ABLE Cables used in connecting LTC to and from the MFX system should preferably be wired as pin 2 hot, pin 1 gnd and pin 3 cold. Where an unbalanced source is used, it is required that pin 3 be shorted to ground to prevent noise entering the system.
  • Page 18 MFX3 plus Service Manual...

  • Page 19: Space And Cooling

    3.0 S PACE AND OOLING It is recommended that the Mainframe be installed in an air conditioned machine room. The Mainframe system is designed to fit a standard 19 inch rack enclosure whereas the Mini is designed for free standing installation in a machine room or studio. For access requirements it is adviseable that at least 2U of space is left above and below the Mainframe to facilitate the easy placement of cards or external hard disk drives when updating software or firmware.
  • Page 20 MFX3 plus Service Manual...

  • Page 21: The Mfx3 Plus Mainframe And Mini

    4.1 T AINFRAME plus The Fairlight MFX3 19 inch Mainframe configuration offers a maximum of 24 input/ output tracks in both the digital and analogue domain, with all storage provided by SCSI hard drives. Systems can be configured from 4 input/4 output through to 24 input/24 output by the installation of the appropriate hardware and software.
  • Page 22 Front View with RF Screen Removed Mainframe Rear View Located to the left of the rear SCSI panel are six slots for ESPDIO/AIO cards. Depending on the plus configuration of the MFX3 system ordered, blanking plates are fitted if fewer than six ESPDIO/ AIO cards are present.

  • Page 23: The Mini

    19 inch Mainframe Digital Card Cage Slot Assignment 4.2 T plus The Fairlight MFX3 Mini configuration offers a maximum of 8 input/output tracks in both the digital and analogue domains operating from either a SCSI Magneto-Optical (MO) or hard drive. Systems can be configured as 4input/4 output or 8 input/8 output, or alternatively 4 input/8 output, depending on the hardware and software installed.
  • Page 24 Mini Front View with Cover Removed Mini Rear View The outer case of the Mini can be removed by first removing the two screws located at the bottom of each side of the case. Once the cover is removed access is gained to the power supply, digital card cage and internal drives.
  • Page 25 The rear of the Mini cabinet contains the Input/Output Sync Module and the ESPDIO/AIO digital/analog input/output cards. From right to left the cards should be as follows: Slot 1 ESPDIO/AIO Slot 2 ESPDIO/AIO (optional, 8-track) Slot 3 ESPSYNC I/O The SYNC module occupies the width of four ESPDIO/AIO cards and is held in position by four thumb screws.
  • Page 26 MFX3 plus Service Manual...

  • Page 27: Power Supply

    5.0 P OWER UPPLY plus The power supplies employed in the MFX3 product range are Computer Products™ units. Both the Mainframe and Mini utilise NFS350 350 Watt switch mode supplies. The Mainframe will also accept an optional Computer Products NFS110 110 Watt power supply, required if internal SCSI drives additional to the boot drive are to be fitted.
  • Page 28 MFX3 plus Service Manual...

  • Page 29: Installation

    6.0 I NSTALLATION 6.1 I NSTALLATION OWER IAGRAM plus MFX3 Video Monitor plus MFX3 Console Filtered & Regulated Common Mains Power Supply plus MFX3 Mainframe Monitor Cable Console Cable External SCSI Cable External SCSI Devices 6 – Installation...

  • Page 30: Mainframe

    The Fairlight MFX3 Mainframe 1. Install Mainframe into 19 inch Rack enclosure (requires removal of front panel). 2. Ensuring mains switch is in the off position, connect the input power cable.

  • Page 31: Mfx3Plus Console And Video Monitor

    Centronics connector located on the SYNC I/O module at the rear left of the Mainframe. 10. Connect any external SCSI drives and ensure that the last device is terminated. Ensure that the SCSI IDs are not in conflict with each other. 11.

  • Page 32: External And Internal Scsi Drives

    Fairlight dealer or Fairlight office. Typically Exabyte drives should be set to ID ‘5’ when connected to the Fairlight Mainframe. It is recommended that a rack tray be fitted either above or below the Mainframe to hold external SCSI devices.

  • Page 33: New Installation Testing

    The number of DIO’s detected will depend on the configuration of the system 6. The system will complete its power-on reset and the screen should turn to black. 7. The Fairlight ESP Waveform Executive Flashware configuration screen should be displayed - check for the following: [ Fairlight ESP Waveform Executive Flashware - v5.05 [15.1.04d] ]...
  • Page 34 plus Typical MFX3 System Boot Screen Digital Channel Cards: 0 1 2 3 4 5 DIO Cards Installed: 0 1 2 3 4 5 DIO Cards with Inputs: 0 1 2 3 4 5 DIO Cards with Analog Inputs:0 1 2 3 4 5 Note: Channel and DIO cards commence with card 0 to a maximum of 5 (if six cards are fitted for 24 tracks).

  • Page 35: Audio Input Test Procedure

    plus Typical MFX3 Project Page 7.2 A UDIO NPUT ROCEDURE plus Power up the MFX3 system and allow to boot to the Project page in the disk recorder. Create a new project called “ Test 44 Analog “. Route an audio source (preferably low level background type music) to the first four input channels &...

  • Page 36: Ltc In

    7.4.2 LTC I Press the M2 key. Press the BLUE key and the DIGI key at the same time and select MASTER M2 ON. Open a project and connect a source of LTC into the Mainframe. When PLAY is pressed the MFX will jump to the time code position of the incoming LTC source.

  • Page 37: Obtaining Technical Support

    Peripheral database are some of the new features to become available. A comprehensive Fairlight User Network including hints and tips to get the most out of our products, a FAQ section and links to other useful digital audio sites, will also form part of the structure.

  • Page 38: On-Line Technical Support

    8.2 O ECHNICAL UPPORT Online technical support is available via the Internet from our Web Site. Just point your browser to: http://www.fairlightesp.com.au click on products then click on tech support. Once there, you will find links to our FTP site for the latest software and firmware updates, up-to-date software bug information, an up-to- date ECN list, a listing of tech support leaflets and a place to ask specific technical questions.

  • Page 39: Ftp Site

    Fairlight products. The directories you will see depend on the access rights you have been given by Fairlight. The directories you will see in this manual may differ from those you will see once connected.

  • Page 40: Internet Connection

    TCP/IP settings. If you are unable to make an FTP connection to Fairlight’s site, check to see if you can connect to other sites before assuming the Fairlight site is not working (e.g. ftp.microsoft.com). You may not have access to other sites, but if it asks you for a name and password, that’s a good sign.

  • Page 41: File Transfer Using Windows Ftp

    25-pin to 9-pin Null Modem Cable 8.5.3 F ILE TRANSFER USING INDOWS 8.5.3.1 C ’ ONNECTING TO AIRLIGHT SITE 8.5.3.1.1 S TARTING AN SESSION Start an FTP session with one of the following methods: a) Select Programs from the Start Menu, select MS-DOS Prompt, type: ftp <return>...
  • Page 42 <return> ftp.fairlightesp.com.au 8.5.3.1.4 U SER NAME Enter your user name as supplied by Fairlight and hit <return>. 8.5.3.1.5 P ASSWORD Enter your password as supplied by Fairlight and hit <return>. Note: Your password will not appear on the screen as you type.

  • Page 43: Root Directory

    OOT DIRECTORY Once logged in, you will be able to access certain directories depending on your access rights as given by Fairlight. To see a list of directories and files, type the following: <return> Use this command at any time to display the contents of your current directory. To list the contents of a certain directory, use the ‘dir’...

  • Page 44: Listing Files

    8.5.3.2.3 C HANGING THE LOCAL DIRECTORY Change the local directory to where you would like the files placed. This will usually be a directory on your PC. <directory_name> <return> e.g: d:\data\download <return> Note: Substitute the directory path with your own. 8.5.3.2.4 B INARY TRANSFER MODE Set the system for binary file download with the following command:...

  • Page 45: Ending A Session

    8.5.3.2.6 D OWNLOADING Download a file with the following command: <filename> <return> e.g: machine <return> Note: Substitute the filename as required. 8.5.3.2.7 E NDING A SESSION When finished, close the connection with the following command: <return> quit 8.5.3.3 FTP C OMMANDS The following is a list of other commands you can use when accessing the site.
  • Page 46 hash This command is useful as it makes the software print a hash ‘#’ symbol every time a certain amount of data is downloaded to your PC. Usually when you decide to download a file you would type ‘get filename <return>’, at which stage no indication of activity is displayed until download has been completed.

  • Page 47: File Transfer Using An Ftp Client

    8.5.4 F FTP C ILE TRANSFER USING AN LIENT 8.5.4.1 FTP C LIENTS FTP client programs offer the familiar ‘drag and drop’ interface similar to Windows Explorer. It is possible to configure such programs to automatically log on to specific sites and directories within those sites at start-up.

  • Page 48: File Transfer Using A Web Browser

    To copy files to your PC simply ‘drag and drop’ as required ‘Right Click’ on the desired file and select ‘Download’. This will put the file into the local directory displayed in the lower window. Alternatively, select ‘Get’ for a choice of download locations.
  • Page 49 Once you have connected, the directories and files will be displayed according to the ‘View’ settings of your browser. If you have an old version of your browser, you may not be able to perform all these tasks. It is advisable to download the latest version from the Net. It is recommended that you use Internet Explorer 4 or later.

  • Page 50: Administering Your Account

    8.5.6 A DMINISTERING YOUR ACCOUNT To administer your FTP account, use an internet browser to display the following web site: http://ftp.fairlightesp.com.au/ Selecting “Change Password” will take you to a page where you can enter a new password. plus 8.5.7 T MFX3 RANSFERRING FILES TO AN plus...
  • Page 51 Step 3: To be safe, rename any files that are to be replaced as a backup, for example: rename machine machine.old <return> Substitute other filenames for ‘machine’ as required. Step 4: Run the Telix program: telix <return> 8.5.7.3 PC H YPER ERMINAL SETUP Use the following procedure to set up a HyperTerminal session on a PC for use with...
  • Page 52 Step 6: Select 38400 Baud Step 7: Select Flow Control - None Step 8: Select OK Note: The Advanced options should be set to default. Click in the HyperTerminal window and type some characters to check com- plus munications with MFX3 The characters should plus appear on the MFX3...
  • Page 53 8.5.7.4 H YPER ERMINAL RANSFER plus Once Telix is running on MFX3 and HyperTerminal is set-up and running on the PC, use the following procedure to transfer files: Step 1: Select Transfer->Send File. Step 2: Type in or browse for the required file(s). Step 3: Select Send.
  • Page 54 MFX3 plus Service Manual...

  • Page 55: Mfx3 Plus Block Diagram

    plus 9.0 MFX3 LOCK IAGRAM 10 WAY SERIAL CABLE SYNC I/O SYNC CARD 60 WAY WAVEFORM SYNC EXECUTIVE CABLE ESP-LTC ESP-SYNC COLOUR ESP-MIDI ESP-WX GRAPHICS ESP-9PIN CARD CPU BUS ESP-PLL ESP-CG4 GRAPHICS & HSSL SYNC CPU & BUS SYNCHRONISATION INPUT/OUTPUT INTERFACE HARDWARE INTERFACE...
  • Page 56 MFX3 plus Service Manual...

  • Page 57: Espwx Waveform Executive Card

    10.0 ESPWX W AVEFORM XECUTIVE 10 – ESPWXX Waveform Executive Card...

  • Page 58: Espwx Block Diagram

    10.1 ESPWX B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 59: Espwx Circuit Description

    10.2 ESPWX C IRCUIT ESCRIPTION 10.2.1 D OCUMENT EVISION 11.4.1996 v1.0 cea: created 15.4.1996 v1.1 cea: proof read 10.9.1996 v1.2 cea: 16M simms 16.10.1996 v1.3 cea: Rev 2.1 PCB release 10.2.2 T ERMINOLOGY DRAM Dynamic RAM SRAM Static RAM FROM Flash ROM CMI-41 Waveform Supervisor ESP-WX Waveform Executive...

  • Page 60: General Overview

    10.2.5 G ENERAL OVERVIEW All clocking on the WX card is synchronous to the CPU (68040-33 U29) and at 33.000MHz derived from the 66.000MHz crystal X3. To distribute the 33MHz system clock, a PLL/buffer chip (CY7B9920-7SC U18) provides individial outputs for each device requiring the clock. The operating system is contained in Flash ROMs (29F040 U27,U19,U24,U15).

  • Page 61: Detailed Description

    DIP switch enable ROM diagnostics spare spare disable PCI BIOS (disable synchronous SCSI, Rev 15 Software) disable copyback caching disable MMU disable CG4, use serial port enable ROM debugger To allow hardware debugging, the jumper at JP4 is connected to a logic analyser to provide a trigger pulse during diagnostics.
  • Page 62 It is possible for the CPU to generate a reset on *RESET by asserting *RSTO when the RESET instruction is executed. This is done by the operating system startup to reset all peripherals (approximatly 250mS after RESETIN is deasserted). During RESETIN assertion, WXGLU1 asserts *CPUMODE to select the internal CPU bus buffer type via diodes D2..D5 and JP11 jumpers (see cpu.sch).
  • Page 63 The following are the device selection signals controlled by WXCPUC: *FROMCE Flash ROM chip enable *FROMOE Flash ROM output enable for reads ($00400000-$007FFFFF) *CGDTS CG4 transfer start ($00800000-$0083FFFF) *WXMIXRTS Mixer interface transfer start [high speed serial link on ESP-CG4] ($00840000-$0087FFFF) *RTCCE RTC and SRAM enable ($00880000-$0088FFFF)
  • Page 64 When the FROM or RTC locations are read, the *OE signal is asserted to enable the data to the CPU data bus. When a write is made to these locations, SIZ[0..1] and A[0..1] are used to assert the appropriate *WE0..3 to enable writing to the correct bytes. If the bus cycle has TT[0..1] = 112 indicating an interrupt acknowledge cycle, WXCPUC asserts *AVEC with *TA.
  • Page 65 10.2.6.5 D EBUGGING NTERFACE (see 10.4.6 Debug Interface schematic) The WXDEBG Lattice (U11) provides facilities for debugging the WX. The address map is (all locations are bytes): $008F0003 read - interrupt source 100 clock interrupt quad serial chip interrupt 1 quad serial chip interrupt 2 quad serial chip interrupt 3 PCI interrupt A...
  • Page 66 There are 4 dongle codes, each byte read sequenctially with a different sequence number: pcb revision dongle byte 1 dongle byte 2 dongle byte 3 $008F000F read and $008F0007 bit 3 clear - read DIP switches The dip switches are read as a 1 repesenting the ON state of the switch.
  • Page 67 This XILINX operates as the master WFM bus controller providing the WFM bus refresh (*LWREF), slice clock (LSCLK) and slice taken by WX signal (*LTSOUT). The PCI WFM bus interface XILINX connects to the local bus signals (LWA0..25, LWD0..15, *LWUDS, *LWLDS, *LWWR) and arbitrates with the WX XILINX for the WFM bus.

  • Page 68: Espwx Field Diagnostics

    IAGNOSTICS The ROMs supplied with the ESP-WX include low level diagnostics to check hardware operation, debugger provided by Microware, a WX version of the KMON diagnostics by Fairlight, and the facilities for booting the operating system. There are 8 DIP switches which are used during diagnostics and selection of the operating system boot mode.

  • Page 69: Cache Push Test

    10.3.1 C ACHE USH TEST The diagnostic assumes failure then executes the CPUSH (cache push) instruction. If this fails then the failed condition will still be displayed on the LEDs and the card will hang until reset. Otherwise, the success code is displayed. 10.3.2 D ONGLE TEST The dongle is enabled within the WXCPUC lattice and the 4 dongle byte sequence is read twice.

  • Page 70: Wfm Bus Access Test

    10.3.8 WFM BUS ACCESS TEST The diagnostic does a walking address memory test on the SC shared memory and verifies each value after it is written, and strobes LASTROBE on error. 10.3.8.1 WFM BUS INTERRUPT TEST The diagnostic writes to the SC to assert the WBINT interrupt signal and checks that it is asserted.
  • Page 71 10.3.8.7 7- SEGMENT BOOT PROGRESS CODES As the ROM starts up the Microware debugger or the normal startup, the LED displays show the progress for tracing errors during booting. If the system fails, one of the codes below will remain on the right two digits showing the last successful operation: System reset (ROM faulty) initialisation entry...
  • Page 72 After performing the initial diagnostics with the dip switches the following will be seen on the monitor when system restarted: *** ATTENTION NVRAM was found corrupted - reconfiguration is forced. Do you want to use the recommended NVRAM configuration ? (Y/N) Answer “n”...
  • Page 73 04:> b2 05:> b3 06:> b4 07:> b5 08:> b6 09: > At this point press return and the following should be displayed on screen: Boot order will be set to ... 01: Display Devices on Turbo SCSI Target:0 02: Boot from Turbo SCSI Disk Drive Target:0 03: Boot from Turbo SCSI Disk Drive Target:1 04: Boot from Turbo SCSI Disk Drive Target:2 05: Boot from Turbo SCSI Disk Drive Target:3...
  • Page 74 DIO #2 Present:NO DIO #3 Present:NO DIO #4 Present:NO DIO #5 Present:NO Fairlight ESP Waveform Executive Flashware - v4.03 Waveform Bus Present: Yes Compile Date: Mar 9 1998 Turbo SCSI Present: Yes Compile Time: 15:58:06 CG4 Present: Yes ROM Debug Level: OFF...
  • Page 75 Message System ...... ESP Messages Version 1.10 Starting Console Daemon ...... Starting ........Checking Machine ......================================================== Machine ID:0997 [GAL] Fairlight ESP Pty Ltd - Production No. 3 Channels:24 EQ:YES TimeFX:YES Editing:YES NinePin:YES Printing:YES 10 – ESPWXX Waveform Executive Card...
  • Page 76 [5] Micron Technology, 1995 DRAM Data Book. [6] Lattice Semiconductor, Lattice Data Book 1994. [7] Xilinx, The Programmable Logic Data Book 1994. [8] Cirrus Logic, CL-CD2400/CD2401 Data Book August 1993. [9] Fairlight ESP , CDIAG v3.0. MFX3 plus Service Manual...

  • Page 77: Espwx Schematics

    10.4 ESPWX S CHEMATICS 10.4.1 ESPWX I NTERCONNECTING IAGRAM 10 – ESPWXX Waveform Executive Card...

  • Page 78: Cpu Control

    10.4.2 CPU C ONTROL MFX3 plus Service Manual...

  • Page 79: 10.4.3 Mc68040 Cpu

    10.4.3 MC68040 CPU 10 – ESPWXX Waveform Executive Card...

  • Page 80: Rtc, Ram And From

    10.4.4 RTC, RAM FROM MFX3 plus Service Manual...

  • Page 81: Dram Controller And Simm

    10.4.5 DRAM C SIMM ONTROLLER AND 10 – ESPWXX Waveform Executive Card...

  • Page 82: Debug Interface

    10.4.6 D EBUG NTERFACE MFX3 plus Service Manual...

  • Page 83: Serial Ports

    10.4.7 S ERIAL ORTS 10 – ESPWXX Waveform Executive Card...

  • Page 84: Wfm Bus Interface

    10.4.8 WFM B NTERFACE MFX3 plus Service Manual...

  • Page 85: Expansion Board Connector

    10.4.9 E XPANSION OARD ONNECTOR 10 – ESPWXX Waveform Executive Card...

  • Page 86: Edge Connectors To Esppci

    10.4.10 E ESPPCI ONNECTORS TO MFX3 plus Service Manual...

  • Page 87: Digital Edge Connector

    10.4.11 D IGITAL ONNECTOR 10 – ESPWXX Waveform Executive Card...
  • Page 88 MFX3 plus Service Manual...

  • Page 89: Espcg4 Color Graphics Card

    11.0 ESPCG4 C OLOR RAPHICS 11 – ESPCG4 Color Graphics Card...

  • Page 90: Espcg4 Block Diagram

    11.1 ESPCG4 B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 91: Espcg4 Circuit Description

    11.2 ESPCG4 C IRCUIT ESCRIPTION 11.2.1 D OCUMENT EVISION 11.12.1996 v1.0 ecl: created 11.2.2 T ERMINOLOGY SRAM Static RAM VRAM Static RAM used for video data PRAM Static RAM used for palette data ESP-WX Waveform Executive ESP-CG4 Graphics Card HSSL High Speed Serial Link for Amek console Operating System (OS9 for 68xxx) FPGA...
  • Page 92 11.2.6 T HEORY OF PERATION RAPHICS The CG4 is a highly specialised video graphics engine with a number of features to allow certain types of images to be displayed more efficiently than on a generic PC type graphics card. In particular CG4 has dedicated hardware to efficiently generate horizontal, vertical and 45 degree angle lines from software as well as allowing horizontal scrolling areas within static areas.

  • Page 93: Detailed Description

    11.2.7 D ETAILED ESCRIPTION 11.2.7.1 B IZING (see 11.4.2 Bus Sizing schematic) Bus sizing is performed totally within one Lattice ispLSI2064-80LT device located at U1 and transfers data between the 32 bit CPU data bus D[0..31] and the CG4’s local 8 bit data bus SD[0..7]. Any transfer between the WX and the graphics hardware starts with the WX generating a transfer start signal *CGDTS.
  • Page 94 Input addresses are supplied to ADDX with signals GMA[0..1] and A[2..17] making up an 18 bit address bus. These address signals are multiplexed inside ADDX with internally generated video access addresses to provide the VRAM address signals RA[0..16], so that during CPU accesses GMA[0..1]/A[2..16] are fed directly to RA[0..16] whilst during video generation accesses, internally generated addresses drive RA[0..16].

  • Page 95: Video Ram

    values for the eight consecutive pixels are then clocked output of DATAX via the palette address lines PA[0..8] over the following eight cycles of the 33mhz clock BCLKCGMX. PA[0..8] drive the low eight address lines of the PRAMs which convert which map the plane data values to colour values specified by the data contained within the PRAMs.

  • Page 96: Programming The Lattice Devices

    11.2.7.6 H (HSSL PEED ERIAL IXER NTERFACE (see 11.4.7 Mixer Interface schematic) The HSSL interface is a 1Mbit bidirectional full-duplex serial link with hardware handshaking designed specifically to interface with the Amek console used in FAME systems. All signals are transmitted over the HSSL cable in differential mode using an AM26LS31 differenial driver (U27) at the transmitter end and opto-couplers (U24, U25 and U26) at the receiver to electrically isolate the console from the MFX3 in order to prevent any possibility of ground loops.

  • Page 97: Testing And Diagnostics

    68040’s Memory Management Unit. 11.2.10 A DDITIONAL EFERENCES [1] Chris Alfred, Motorola MC68040 operation, Fairlight ESP . [2]Motorola, MC68040 32 bit Microprocessor User’s Manual. [3]Chris Alfred, ESP-WX Waveform Executive Functional Description, Fairlight ESP. [4]Lattice Semiconductor, Lattice Data Book 1994.

  • Page 98: Espcg4 Test Procedures

    11.3.3 ESPCG4 T ROCEDURES 11.3.3.1 G ENERAL IELD IAGNOSTIC Connect the 26-way IDC loopback cable (including the ESPRIO) to JP2 of the ESPCG4 and plus switch ON the MFX3 . When the bootup process has finished, type the following command in the Telix window on the PC: cg4diag <enter>...
  • Page 99 VRAM Plane 5 (U 9) : 0 errors. VRAM Plane 6 (U10) : 0 errors. VRAM Plane 7 (U12) : 0 errors. Dual palettes have been detected. Checking PRAM (U3, U14, U15, U18, U19, U20 and U21). OSK palette : 0 errors. CMI palette : 0 errors.
  • Page 100 Erase register (0x82FCCB): OK. Test palette RAM (y/n)? : y Testing PRAM write then read. OSK palette : 0 errors. CMI palette : 0 errors. MDR palette : 0 errors. Testing PRAM write then read. OSK palette : 0 errors. CMI palette : 0 errors.
  • Page 101 VRAM Plane : 6 : 0 errors. VRAM Plane : 7 : 0 errors. Test Video RAM across planes (y/n)? : y errors. Test auto increment hardware (y/n)? : y Byte write, move down, starting from 0x828000. Byte write, move up, starting from 0x82BFFF. Test auto increment hardware II (y/n)? : y Top line left to right.
  • Page 102 11.3.4.3 M IXER Connect the 26-way IDC loopback cable (including the ESPRIO) to JP2 of the ESPCG4 and switch ON the ESPWX. When the bootup process has finished, type: hssltest <enter> at the ‘#:’ prompt. This program should run and print the following : ————========++++++++++========————...

  • Page 103: Loopback Plug

    Characters received : 298959 Zero errors. Place HSSL in loopback mode (y/n)? : n Detailed HSSL test (y/n)? : n 11.3.4 L OOPBACK The loopback plug is made from a 25 pin male D connector. The following connections should be made on this D connector. pin 2 <—>...

  • Page 104: Espcg4 Schematics

    11.4 ESPCG4 S CHEMATICS 11.4.1 ESPCG4 I NTERCONNECTING IAGRAM MFX3 plus Service Manual...

  • Page 105: Auto Bus Sizing

    11.4.2 A IZING 11 – ESPCG4 Color Graphics Card...

  • Page 106: Address Xilinx

    11.4.3 A DDRESS ILINX MFX3 plus Service Manual...

  • Page 107: Data Multiplexer

    11.4.4 D ULTIPLEXER 11 – ESPCG4 Color Graphics Card...

  • Page 108: Video Ram

    11.4.5 V IDEO MFX3 plus Service Manual...

  • Page 109: Video Generation

    11.4.6 V IDEO ENERATION 11 – ESPCG4 Color Graphics Card...

  • Page 110: Mixer Interface

    11.4.7 M IXER NTERFACE MFX3 plus Service Manual...

  • Page 111: Connector, Clock Buffer

    11.4.8 C ONNECTOR LOCK UFFER 11 – ESPCG4 Color Graphics Card...
  • Page 112 MFX3 plus Service Manual...

  • Page 113: Esppci Pci Bus Interface Card

    12.0 ESPPCI PCI B NTERFACE 12 – ESPPCI PCI Bus Interface Card...

  • Page 114: Esppci Block Diagram

    12.1 ESPPCI B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 115: Esppci Circuit Description

    12.2.3 I NTRODUCTION To allow Fairlight to use the many PCI compliant cards available to the PC world, the ESP- PCI card provides a PCI interface to the ESP-WX. It is connected as a daughter card at connectors CN1 and CN2 of the ESP-WX.
  • Page 116 12.2.4.2 68040 PCI I INTERFACE The CA91C068 Spanner chip at U1 converts Motorola CPU transfers into PCI transfers. When power is applied and the PCI bus is un-reset (PCIRST# high), this chip is not accessable from the 68040 side and so U19 is programmed with a simple state machine to write the value 6 to configuration register 4 from the PCI side.
  • Page 117 12.2.4.4 PCI SLOTS CN6,CN5,CN4,CN3 are PCI slots 1 to 4 respectively. These are standard 5V PCI slots. 12.2.4.5 8M DRAM SHARED WITH The 8M DRAM at U22 is dual ported between the PCI bus and the DSP at U17. The DSP has the higher priority to the DRAM.

  • Page 118: Installation Of Esp-Pci

    12.2.5 I ESP-PCI NSTALLATION OF When first installing the ESP-PCI, the system must be booted from the ESP-TS card and install the new software. New Flash ROMS with the ESP-PCI drivers blown. Once this is done, the jumpers at JP13 on the ESP-WX can be added and the ESP-WX with ESP-PCI and PCI SCSI installed by replacing the ESP-WX card in the ESP-TS slot.

  • Page 119: Starting The Diagnostics

    User name?: Type: mfx<Return> You should see: Process #36 logged on 97/12/16 03:14:46 Welcome! Fairlight OS9 Ready mfx: Type: pcidiag -rspd 12.3.2.3 F URTHER IAGNOSTICS Once the above tests have all passed, the pcidsp program is used to futher test the ESP-PCI.

  • Page 120: Notes On Esp-Pci Basic Operation

    register tests PCI cards present mask control register test dsp control register test revision Spanner chip PCI interface tests Spanner vendor ID Spanner mapping PCI bus tests Slot IDs test pci data bits test dram data bits DSP IVR register bit test DRAM tests write all 0’s write all 1’s...

  • Page 121: Test Descriptions

    12.3.5 T ESCRIPTIONS 12.3.5.1 R EGISTER TESTS These tests check the data, address and control signals to U11 - the main control and status device. An access starts with a 30nS pulse on *PCITS (PCI transfer start) from the ESP-WX and completes with a 30nS pulse on *TA (transfer acknowledge) generated by U11 when the data is accepted on write or ready on read.
  • Page 122 12.3.5.2.2 S PANNER APPING A write to $008D0000 maps U1 to $0000F814. A write of $00000020 to U1’s configration register at $0000F814 remaps U1 configuration registers to $2000F800. $2000F800 is read and checked for a PCI ID of $57100048. 12.3.5.3 PCI B ESTS 12.3.5.3.1 S For each of the PCI slots, writing the slot number (1..4) plus 8 (the *PCIRST bit) to $60000007...
  • Page 123 12.3.5.4.3 D 0’ ALKING The DRAM is filled with $00000000 for its complete range. For each of the 32 bits, $38000000 is written with that bit low and all others high and checked. All other addresses are checked to be $00000000.

  • Page 124: References

    12.3.5.6.1 S TARTING The test program is loaded via the host port. Any value written to the host port HD registers (4 bytes, one each at $3C000010 (msb) $3C000014, $3C000018 and $3C00001C), is read back from these addesses. This is a simple way to prove that the DSP loaded correctly. 12.3.5.6.2 DRAM DSP W , CPU R RITE...

  • Page 125: Esppci Dsp Field Diagnostics

    3. Cypress Data Book - Memories, DataCom, FCT Logic, PC products, Cypress Semiconductor, May 1995. 4. PCI Local Bus Specification - Revision 2.1, PCI Special Interest Group, June 1 1995. 5. PAL Devices Data Book and Design Guide 1996, Advanced Micro Devices Inc, 1996. 6.

  • Page 126: Command Details

    12.4.4 C OMMAND ETAILS The pcidsp diagnistic is executed with command options. These options can be seen by using pcidsp -?. You will see: pcidsp v1.4 - ESP-PCI DSP diagnostics usage: pcidsp [options] options: dsp linked list processing test read from WFM memory test write to WFM memory test verbose output level (extra -z for more) -f=<file>...

  • Page 127: Esppci Schematics

    12.5 ESPPCI S CHEMATICS 12.5.1 ESPPCI I NTERCONNECTING IAGRAM 12 – ESPPCI PCI Bus Interface Card...

  • Page 128: Edge Connection To Espwx

    12.5.2 E ESPWX ONNECTION TO MFX3 plus Service Manual...

  • Page 129: Cpu To Pci Interface

    12.5.3 CPU PCI I NTERFACE 12 – ESPPCI PCI Bus Interface Card...

  • Page 130: Pci Control/Central Resources

    12.5.4 PCI C ONTROL ENTRAL ESOURCES MFX3 plus Service Manual...

  • Page 131: Pci Slots

    12.5.5 PCI S LOTS 12 – ESPPCI PCI Bus Interface Card...

  • Page 132: Pci Dram Interface

    12.5.6 PCI DRAM I NTERFACE MFX3 plus Service Manual...

  • Page 133: 12.5.7 Pci Dram

    12.5.7 PCI DRAM 12 – ESPPCI PCI Bus Interface Card...

  • Page 134: Wfm Interface

    12.5.8 WFM I NTERFACE MFX3 plus Service Manual...
  • Page 135 12 – ESPPCI PCI Bus Interface Card...

  • Page 136: Pci Scsi Card

    12.6 PCI SCSI C plus The SCSI Controller approved for use with the Fairlight MFX3 is the SYMBIOS SYM8100S (earlier product code was previously NCR8100S). This controller uses the SYMBIOS (NCR) PCI to SCSI chipset 53C810. Identification of the controller can be performed by visual inspection and the following routine should be followed: 1.

  • Page 137: Pci 100Baset Card Considerations

    MFX3 . Use of PCI network cards not approved by Fairlight ESP is not recommended. The original i82557 Intel chipset has been upgraded to i82558 and is 100% compatible with the earlier one. However, this might not be the case in the future.
  • Page 138 EtherExpress Model PRO/100B PCI 100BaseT Network Adaptor ID 678400-001 MFX3 plus Service Manual...

  • Page 139: Esptsr Turbo Scsi Card

    13.0 ESPTSR T SCSI C URBO 13 – ESPTS Turbo SCSI Card...

  • Page 140: Esptsr Block Diagram

    13.1 ESPTSR B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 141: Esptsr Circuit Description

    13.2 ESPTSR C IRCUIT ESCRIPTION 13.2.1 T ERMINOLOGY TSCSI ESPTSR Turbo SCSI Card Waveform Executive PCB WFMBUSS Waveform Bus WFMRAM Waveform RAM Signals which have been buffered are prefixed by ‘B’ (eg. RA once buffered becomes BRA). Signals which have been latched are prefixed by ‘L’ Active low signals are preceded by (*) 13.2.2 O VERVIEW...

  • Page 142: Status Leds

    5C00000 5C0001F NCR SCSI chip 5C00020 5C00023 TSCSI DMA address registers 5F00001 TSCSI control read/write register 5F00003 TSCSI status register For accesses in the range 5800000..5EFFFFF, TSEXT3 (U43 22V10) asserts the *TSCSI signal to indicate that the data is for on-card (internal) devices. The 8 bit control and read-back status registers are implemented as two TSCLAT PALS (U25,U26 22V10).
  • Page 143 13.2.3.4 W AVEFORM NTERFACE (see 13.4.4 ESPTSR Waveform Bus Interface schematic) All Waveform Buss transfers are controlled by the TSWFM15 (U40 22V10) and TSWFM25 (U39 22V10) PALS. TSWFM15 converts the WFMBUSS control signals to internal TSCSI control signals during non-DMA transfers by WFMBUSS buss masters. TSWFM25 handles the WFMBUSS arbitration and generates the WFMBUSS control signals for the TSCSI DMA transfer.
  • Page 144 Pins 1,2 shorted 441024 1M x4bit DRAMs Pins 2,3 shorted 44256 256k x 4bit DRAMs The Turbo SCSI card normally has 256k x 16 bits installed which will appear in the address range 5800000..587FFFF. 13.2.3.7 DMA A DDRESS EGISTERS (see 13.4.6 ESPTSR SCSI Interface schematic) 16 bit writes to 5C00020 (MSW) and 5C00022 (LSW) load the start address for TSCSI DMA transfers into the TSCNT DMA address counters (U16,U51,U17,U50 22V10).
  • Page 145 13.2.3.9 SCSI B NTERFACE (see 13.4.6 ESPTSR SCSI Bus Interface schematic) The NCR53C94 is accessed on even address boundaries in the range SC00000..SC0001F as decoded by TSSCSI14 (U48 22V10). Accesses assert *NCR and one of *SWR (write to NCR SCSI chip) or *SRD (read from NCR SCSI chip).

  • Page 146: Esptsr Schematics

    13.3 ESPTSR S CHEMATICS 13.3.1 ESPTSR I NTERCONNECTING IAGRAM MFX3 plus Service Manual...

  • Page 147: Esptsr Edge Connector

    13.3.2 ESPTSR E ONNECTOR 13 – ESPTS Turbo SCSI Card...

  • Page 148: Esptsr Support

    13.3.3 ESPTSR S UPPORT MFX3 plus Service Manual...

  • Page 149: Esptsr Wfm Bus Interface

    13.3.4 ESPTSR WFM B NTERFACE 13 – ESPTS Turbo SCSI Card...

  • Page 150: 13.3.5 Esptsr Dram

    13.3.5 ESPTSR DRAM MFX3 plus Service Manual...

  • Page 151: Esptsr Scsi Interface

    13.3.6 ESPTSR SCSI I NTERFACE 14 – ESPDCC Digital Channel Card...
  • Page 152 MFX3 plus Service Manual...

  • Page 153: Espdcc Digital Channel Card

    14.0 ESPDCC D IGITAL HANNEL 14 – ESPDCC Digital Channel Card...

  • Page 154: Espdcc Block Diagram

    14.1 ESPDCC B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 155: Espdcc Circuit Description

    14.2 ESPDCC C IRCUIT ESCRIPTION 14.2.1 D OCUMENT EVISION 03.08.1994 v0.x 14.2.2 T ERMINOLOGY Analog I/O Card (ESP-AIO) Digital Channel Card (ESP-DCC) Digital I/O Card (ESP-DIO) Digital Signal Processor IRAM Interface RAM QPRAM Quad-Port RAM Sync Card (ESP-SYN) SRAM Static RAM Sample Rate Conversion Synchronous Serial Interface Timesliced Sample Bus...
  • Page 156 14.2.3.3 WBUS I NTERFACE The DCC occupies several address segments on the waveform bus as follows: 02000000-027FFFFF WRAM mask C 04000000-047FFFFF WRAM mask B 05000000-057FFFFF WRAM mask A 05A00000-05A07FFF IRAM mask A 05A40000-05A47FFF IRAM mask B 05A80000-05A87FFF IRAM mask C 05AC0000-05AC7FFF control/status registers (mask A only) 05B00000...

  • Page 157: Dcc I/O Subsystem

    data written to WRAM in the next available WRAM cycle. A background read cycle latches the address and causes the data at that address to be read from WRAM and latched in the next available WRAM cycle. The data read by the DSP is the data which was latched by the previous background read cycle.
  • Page 158 cycle processing. During the data phase the TSB data lines are driven for the full 120nS and the data is latched by TSB receivers after nominally 90nS. A large margin is allowed for synchronisation errors. TSB cycles are grouped into sample “slots” of 3 cycles or 24 bits each (MS byte first). The slots are numbered sequentially starting from zero at the TSB trigger point.

  • Page 159: Xilinx Gate Array

    The DSP can determine the current page by reading the Xilinx status register. This must also be synchronised with the sample interrupt to ensure valid data. Each TSB image in the QPRAM is 64 samples long; however the last four slots of each page are used by the SSI output ports and should not be used for TSB transfers;...

  • Page 160: Xilinx Configuration Program X1

    14.2.6 X ILINX ONFIGURATION ROGRAM 14.2.6.1 G ENERAL The X1 program’s main function is to control the flow of data between the QPRAM and the I/O devices (SSI shift registers and TSB data buffer). The 33MHz system clock is used as the primary global clock signal.

  • Page 161: Transmitter Control

    control registers and output enables for the status registers. The DSP data bus is driven by the Xilinx in four modes: Status register A read assert D15..0 with RX port A status Status register B read assert D15..0 with RX port B status Waveform RAM read assert D15..0 with zero data QPRAM read...
  • Page 162 transfer data from the shift register to the holding register at the end of each byte. At this time a QPRAM request is also asserted to transfer the data into the receiver queue in QPRAM. The receiver queue contains 16 L/R pairs of samples, which allows the DSP to read input samples from QPRAM in a block for greater efficiency.
  • Page 163 sample rate well above 48kHz. There are four sources of QPRAM requests which are prioritised as follows (highest to lowest): SSI receiver port A SSI receiver port B SSI transmitter TSB requests are handled differently in that a pending TSB request prevents any other QPRAM request from being recognised in the 30nS preceding the TSB cycle.

  • Page 164: Additional References

    SSI TXA/B Direct: A9-A8 current page (0..2) A7-A4 all ones port A => 0, port B => 1 A2-A0 byte within sample period (0..7) assert TLDA/B, *QCE, *QRD SSI TXA/B Indirect Address Fetch: A9-A8 current page (0..2) A7-A4 all ones port A =>...

  • Page 165: Dcc Addressing Table

    14.3.1 DCC A DDRESSING ABLE Decimal Binary Rack Slot Address Address Switch 1 Switch 2 Switch 3 /Mini Slot 9 / 3 8 / 2 14.3.2 DCC T ERMINATION The DCC at address 0 (located furthest from the Sync Card) should have termination resistors installed as follows: RN1: 220 Ohm RN3: 330 Ohm...

  • Page 166: Diagnostic Test Procedure

    14.4.1 D IAGNOSTIC TEST PROCEDURE 1. Install the TSB cable and DIO cable to the card. 2. If the TSB cable is not connected to the SC, then JP7 must be installed. 3. Turn on system. 4. When at # prompt, run the DCC diagnostics by typing the following: dccdiag <return>.

  • Page 167: Dcc Pll Adjustment

    Sample of the screen view after running DCCDIAG V2.01 with no errors: WRAM test size = 6M or 8M Testing Card <num> (shows number of cards to be tested) Test bus integrity via JTAG Test DSP -> WX interrupt via JTAG Test WX ->...

  • Page 168: Dcc Led Indicators

    14.4.4 DCC L NDICATORS The DCC Leds diplay the following signals: RESET Reset LWIRQ IRQ to WFM MASKA Accessing DCC WRAM WACCL WFM to DCC DACC DCC to DRAM IRQ0 IRQ to DCC MSTR Card selected as AES input sync source FLAG0 Debug - shows ‘in play’...

  • Page 169: Espdcc Schematics

    14.5 ESPDCC S CHEMATICS 14.5.1 ESPDCC I NTERCONNECTING IAGRAM 14 – ESPDCC Digital Channel Card...

  • Page 170: Dsp And Sram

    14.5.2 DSP SRAM MFX3 plus Service Manual...

  • Page 171: Waveform Bus Interface, Pll Clock

    14.5.3 W , PLL C AVEFORM NTERFACE LOCK 14 – ESPDCC Digital Channel Card...

  • Page 172: Control Logic

    14.5.4 C ONTROL OGIC MFX3 plus Service Manual...

  • Page 173: Ws Interface Sram

    14.5.5 WS I SRAM NTERFACE 14 – ESPDCC Digital Channel Card...

  • Page 174: Waveform Ram Interface

    14.5.6 W RAM I AVEFORM NTERFACE MFX3 plus Service Manual...

  • Page 175: Waveform Ram 8Mb

    14.5.7 W RAM 8MB AVEFORM 14 – ESPDCC Digital Channel Card...

  • Page 176: Serial I/Oand Tsb Interface

    14.5.8 S TSB I ERIAL NTERFACE MFX3 plus Service Manual...

  • Page 177: Timesliced Bus And Serial Interfaces

    14.5.9 T IMESLICED US AND ERIAL NTERFACES 14 – ESPDCC Digital Channel Card...

  • Page 178: Pcb Extras

    14.5.10 PCB E XTRAS MFX3 plus Service Manual...

  • Page 179: 15 - Espdio Digital I/O Card

    15.0 ESPDIO D I/O C IGITAL 15 – ESPDIO Digital I/O Card...

  • Page 180: Espdio Block Diagram

    15.1 ESPDIO B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 181: Espdio Circuit Description

    15.2 ESPDIO C IRCUIT ESCRIPTION 15.2.1 CPU O PERATION *PDRST U10/17(68HC11) Power down reset, approx 350mS low pulse. Test by shorting JP5. 6M144 U10/7 (68HC11) 6.144 MHz CPU crystal clock input E U10/5 (68HC11) 1.536 MHz (6M144 / 4) CPU clock. Always present when 68HC11 operational. AS U20/11(74HC373) 163nS high, 488nS low.

  • Page 182: Dio Commands

    receive the same data. The receive lines are similarly bussed, however, only one DIO will transmit on this line at any one time. Pullups on the SC hold the line in the idle state (input to duart is high) when no card is transmitting.
  • Page 183 Once one of the error conditions occur (#,!,?), the DIO will stop processing commands until a STATUS or RESET command. The STATUS command will echo the error code and resume processing commands. If a second STATUS command is issued, the status command itself will be echoed indicating the last successful command.
  • Page 184 J <mask> <addr> Jump to address <addr> and start execution. ANALOG INPUT LEVEL L <mask> <input> <level> Set analog input attenuator on <input> to <level>. <input> should be 0..3, and <level> is 00..FF in 0.5dB steps where C0 is 0dB gain. INPUT SOURCE I <mask>...
  • Page 185 SYNC (clocking) SOURCE S <mask> <source> Set clocking sync source for card to <source>. Possible values for <source> are: from ESP-SYN card via ESP-DCC [S_EXT] from digital input port 0 [S_DIG0] from digital input port 1 [S_DIG1] Extra debugging modes: from DIO crystal [S_XTAL] digital out from xtal,input from...
  • Page 186 DISABLE DEBUG PORT - <mask> Disable any debug output. CALIBRATE ANALOG ~ <mask> Reset and calibrate the A/D and D/A converters - this takes about 200mS to complete. This command should be issued on initialisation and whenever the sample clocks are changed. The calibration resets the A/D and D/A processing and nulls any DC offsets on the A/D converter.

  • Page 187: Espdio Diagnostics

    15.3 ESPDIO D IAGNOSTICS DIO.EXE Digital IO/Analog IO Interface Software for PC. 15.3.1 I NTRODUCTION DIO.EXE is a program to communicate and control the ESP-DIO Digital IO Card and ESP-AIO Analog IO Card. This program communicates via COM1 serial port to a debugging serial port on the ESP-DIO.
  • Page 188 i <port> <source> select source of input data <source> input source _________________________ analog SPDIF AES, digital out is AES SPDIF, digital out is SPDIF o <source> select source of data for output (DAC) <source> output source _________________________ ESP-DCC digital channel card A/D converter (loops ADC to DAC) Yamaha +ve Yamaha -ve...

  • Page 189: Espdio Schematics

    15.4 ESPDIO S CHEMATICS 15 – ESPDIO Digital I/O Card...
  • Page 190 MFX3 plus Service Manual...
  • Page 191 15 – ESPDIO Digital I/O Card...
  • Page 192 MFX3 plus Service Manual...
  • Page 193 15 – ESPDIO Digital I/O Card...
  • Page 194 MFX3 plus Service Manual...
  • Page 195 15 – ESPDIO Digital I/O Card...
  • Page 196 MFX3 plus Service Manual...
  • Page 197 15 – ESPDIO Digital I/O Card...

  • Page 198: Espdo Schematics

    15.5 ESPDO S CHEMATICS MFX3 plus Service Manual...
  • Page 199 15 – ESPDIO Digital I/O Card...
  • Page 200 MFX3 plus Service Manual...
  • Page 201 15 – ESPDIO Digital I/O Card...
  • Page 202 Sheet 5 Removed MFX3 plus Service Manual...
  • Page 203 15 – ESPDIO Digital I/O Card...
  • Page 204 MFX3 plus Service Manual...
  • Page 205 15 – ESPDIO Digital I/O Card...
  • Page 206 MFX3 plus Service Manual...

  • Page 207: 16 - Espaio Analog I/O Card

    16.0 ESPAIO A I/O C NALOG 16 – ESPAIO Analog I/O Card...

  • Page 208: Espaio Block Diagram

    16.1 ESPAIO B LOCK IAGRAM ADDATA Unbalanced ADDATA ADC0~3 Attenuated SACLK,SBCLK SWCLK DABCLK,DAWCLK DA256FS, DAC0~3 DADATA AOUT Electronicly Balanced +22dBu DAC0~3 IDC50 MFX3 plus Service Manual...

  • Page 209: Espaio Circuit Description

    16.2 ESPAIO C IRCUIT ESCRIPTION 16.2.1. I NTRODUCTION The AIO card provides 4 channels of analog input and 4 channels of analog output. Each input channel has digitally controlled attenuators allowing gain to +30dB and attenuation to - 96dB and mute. The peak levels allowed on the card are +22dBu based on +4dBu nominal level and 18dB headroom.

  • Page 210: D/A Conversion

    16.2.5. D/A C ONVERSION CS4328 18bit stereo 16 times oversampling delta-sigma converters are used for output conversion. The input to these converters is in three wire format where DAWCLK0..1 is the sample rate word clock, DABCLK0..1 is the 64 Fs bit clock, and DADATA0..1 is the serial output data.

  • Page 211: Espaio Schematics

    16.3 ESPAIO S CHEMATICS 16 – ESPAIO Analog I/O Card...
  • Page 212 MFX3 plus Service Manual...
  • Page 213 16 – ESPAIO Analog I/O Card...
  • Page 214 MFX3 plus Service Manual...
  • Page 215 16 – ESPAIO Analog I/O Card...
  • Page 216 MFX3 plus Service Manual...
  • Page 217 16 – ESPAIO Analog I/O Card...
  • Page 218 MFX3 plus Service Manual...
  • Page 219 16 – ESPAIO Analog I/O Card...

  • Page 220: Espao Schematics

    16.4 ESPAO S CHEMATICS MFX3 plus Service Manual...
  • Page 221 Sheet 2 Removed 16 – ESPAIO Analog I/O Card...
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  • Page 223 16 – ESPAIO Analog I/O Card...
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  • Page 225 16 – ESPAIO Analog I/O Card...
  • Page 226 Sheet 7 Removed MFX3 plus Service Manual...
  • Page 227 Sheet 8 Removed 16 – ESPAIO Analog I/O Card...
  • Page 228 MFX3 plus Service Manual...

  • Page 229: Espsyn Sync Card

    17.0 ESPSYN S 17 – ESPSYN Sync Card...

  • Page 230: Espsyn Block Diagram

    17.1 ESPSYN B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 231: Espsyn Diagnostics

    17.2 ESPSYN D IAGNOSTICS 17.2.1 66MH U44 (4044) provides the phase detection and voltage control. D2 (BB809 varactor) and components around Q1 (2N2369) form a voltage controlled Hartley oscillator. U45 (CLKGEN) divides 66M to produce SREF to feed back into U44 for phase comparison. When the PLL is locked, U45/12 should be high (*UNLOCKED = 1) and UNLOCKED LED (bottom LED) should be off (NOTE: led will also be off if oscillator is not running).

  • Page 232: Wordclock Crystals

    17.2.2 256 ORDCLOCK CRYSTALS (see sheet 2) IGNAL STATES WHEN OPERATIONAL • U35/12 8.192MHz • U35/8 11.2783MHz • U36/12 12.2986MHz • U36/8 12.288MHz 17.2.3 LED I NDICATORS The diagnostic LEDs indicate the following: RESET Reset HALT Halt INT TO SC Interrupt to Sync Card INT TO WS Interrupt to Wave Exec...

  • Page 233: Sync Card Test

    (enter kmon30 on the sync card) The following should show on screen: Sync Card Monitor Vxx.xx 68040 is Ready ..68030 is Ready ..Fairlight E.S.P 68030 Monitor Vxx.xx 17 – ESPSYN Sync Card...

  • Page 234: System Tests

    8. At “ Q: ” prompt, type: (for sync card diagnostics) Following should show on screen: Sync Card Memory Tests Vx.xx Features Enabled ————————————— Report Passes Report Errors Memory Tests Enabled ————————————————— ADDRESS RANGE Start: 04900000 End: 04 f f f f f f <7 Meg> S C D I A G >...

  • Page 235: Espsyn Sync Card Schematics

    17.3 ESPSYN S CHEMATICS 17 – ESPSYN Sync Card...
  • Page 236 MFX3 plus Service Manual...
  • Page 237 Sheet 3 Removed 17 – ESPSYN Sync Card...
  • Page 238 MFX3 plus Service Manual...
  • Page 239 17 – ESPSYN Sync Card...
  • Page 240 MFX3 plus Service Manual...
  • Page 241 17 – ESPSYN Sync Card...
  • Page 242 MFX3 plus Service Manual...
  • Page 243 17 – ESPSYN Sync Card...
  • Page 244 MFX3 plus Service Manual...
  • Page 245 17 – ESPSYN Sync Card...
  • Page 246 MFX3 plus Service Manual...
  • Page 247 17 – ESPSYN Sync Card...
  • Page 248 MFX3 plus Service Manual...
  • Page 249 17 – ESPSYN Sync Card...
  • Page 250 MFX3 plus Service Manual...

  • Page 251: 18 - Espmidi Midi I/O Card

    18.0 ESPMIDI MIDI I/O C 18 – ESPMIDI MIDI I/O Card...

  • Page 252: Espmidi Block Diagram

    18.1 ESPMIDI B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 253: Espmidi Diagnostics

    18.2 ESPMIDI D IAGNOSTICS 18.2.1 R UNNING IAGNOSTICS System must have an ESP-SYN Sync Card and cable connecting it to the ESP-MIDI Card. Type: osk30 enters OSK30 operating system scdiag start Sync Card diagnostics (should get SC> prompt) 18.2.2 MIDI PORTS (1) Setup: Connect MIDI OUT A to MIDI IN A...

  • Page 254: Video Sync Input

    The possible status values displayed by the diagnostic are: pass Current test value was sent/received correctly. fail Current test value was not sent or a different value was received..No value has been received by the port. I:nn Extra interrupt received with byte nn. L:nn Lost interrupt, received byte was nn.

  • Page 255: Dip Switches

    18.2.4 DIP SWITCHES (1) Setup: None Type: (2) Change each dip switch (S1) and check display shows state. (3) Press q to exit. Diagnostic Description The diagnostic reads the status of the DIP switches via the 68681 duart at U24. Data read shows - (minus sign) when ON and _ (underscore) when OFF.
  • Page 256 Diagnostic Description The possible status values displayed by the diagnostic are: pass Current test value was sent/received correctly. fail Current test value was not sent or a different value was received..No value has been received by the port. I:nn Extra interrupt, received byte nn.

  • Page 257: Espmidi Schematics

    18.3 ESPMIDI S CHEMATICS 18 – ESPMIDI MIDI I/O Card...
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  • Page 259 18 – ESPMIDI MIDI I/O Card...
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  • Page 261 18 – ESPMIDI MIDI I/O Card...
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  • Page 263 18 – ESPMIDI MIDI I/O Card...
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  • Page 265 18 – ESPMIDI MIDI I/O Card...
  • Page 266 MFX3 plus Service Manual...

  • Page 267: Esppll Phase Lock Loop Card

    19.0 ESPPLL P HASE 19 – ESPPLL PLL Card...

  • Page 268: Esppll Block Diagram

    19.1 ESPPLL B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 269: Esppll Diagnostics

    19.2 ESPPLL D IAGNOSTICS 19.2.1 E QUIPMENT REQUIRED Example device 3.5 digit digital voltmeter FLUKE 100MHz or better frequency meter LEADER LDC823A Test connectors for SIO 19.2.2 S ETUP Shorting plug jumpers should be installed at: JP1 ,JP8 ,JP9 ,JP10,JP11,JP12,JP13,JP14 JP15,JP16,JP17,JP18,JP19,JP20,JP21,JP22 JP4/13-14 JP4/15-16 Connect ESP-PLL to ESP-MIDI card installed to system, turn-on system.

  • Page 270: Frame Pll Low Frequency Check

    19.2.5 FRAME PLL LOW FREQUENCY CHECK Connect frequency meter GND to TP16. Connect frequency meter probe to TP8. Check frequency is 60kHz +/- 5kHz. [55kHz to 65kHz] 19.2.6 32 LOW FREQUENCY CHECK Install shorting plugs JP6/5-6, JP6/11-12, JP6/15-16. Connect frequency meter GND to TP17. Connect frequency meter probe to TP3.

  • Page 271: Crystal Frequency Adjustment

    Check frequency is 41000Hz +/- 1900Hz. [39100Hz to 49200Hz] Remove shorting plugs from JP6. 19.2.9 C RYSTAL FREQUENCY ADJUSTMENT Connect frequency meter GND to TP5. Connect frequency meter probe to TP6. Adjust C62 for 16384.000 kHz +/- 100Hz. [16383.900kHz to 16384.100kHz] Connect frequency meter probe to TP13.

  • Page 272: General Purpose Outputs (Gpo)

    together and to RS232 connector pin 3 via 1k resistor. RS232 DB9 female 7-8-1 19.2.12 G (GPO) ENERAL URPOSE UTPUTS (1) Setup: Connect GPO and RS232 shorting plugs. Type: (2) Check that LEDs cycle ON. (3) Press q to exit test. Diagnostic Description The diagnostics assertes GP0..7 signals (outputs of U24 on ESP-MIDI) in sequence in 250mS intervals.

  • Page 273: Wclk Out And Wclk In

    19.2.14 WCLK OUT WCLK IN (1) Setup: Connect WCLK OUT to WCLK IN Type: ep xtal 48k [starts clocks at 48k] (2) Verify that received frequency is approximatly 48000Hz. (3) Press q to exit diagnostic. If successful, the display should show: / WCLK IN: 48000Hz Diagnostics Description The diagnostic enables the 12.288MHz crystal on the ESP-SYN card to generate 48kHz to...

  • Page 274: Esppll Scematics

    19.3 ESPPLL S CEMATICS MFX3 plus Service Manual...
  • Page 275 19 – ESPPLL PLL Card...
  • Page 276 MFX3 plus Service Manual...
  • Page 277 19 – ESPPLL PLL Card...
  • Page 278 MFX3 plus Service Manual...
  • Page 279 19 – ESPPLL PLL Card...
  • Page 280 MFX3 plus Service Manual...
  • Page 281 19 – ESPPLL PLL Card...
  • Page 282 MFX3 plus Service Manual...

  • Page 283: Espltc Ltc Card

    20.0 ESPLTC LTC C 20 – ESPLTC LTC Card...

  • Page 284: Block Diagram

    20.1 B LOCK IAGRAM LTCIN1 LTCIN 1 BALANCED FILTER LINE CONVERSION RECEIVER LTCIN2 LTCIN 2 BALANCED FILTER LINE CONVERSION RECEIVER LTCOUT LTCGEN U4D,C BALANCED TTL CONVERSION LINE TRANSMITTER AES SYNC AESTX+,AESTX- OUTPUT IMPEDANCE MATCH & ISOLATION TRANSFORMERS AES SYNC INPUT AESRX+,AESRX- IDC26 PCB MFX3...

  • Page 285: Diagnostics

    20.2 D IAGNOSTICS 20.2.1 R UNNING IAGNOSTICS Equipment Required Time code Generator/Reader XLR Male to XLR Female cable System must have an ESP-SYN Sync Card and cable connecting it to the ESP-MIDI Card and the ESP-LTC installed (other SIO modules need not be installed). Type: osk30 enters OSK30 operating system...
  • Page 286 (4) Press <space> to reverse direction of generated data. Verify that LTC IN B reports the correct direction of timecode. Also check that timecode passes backwards through midnight correctly. (5) Setup: Connect LTCOUT to MASTER CODE IN of ZETA-THREE timecode reader. Press DISPLAY button on ZETA-THREE until M_TC appears on the display.
  • Page 287 LTC Readers The LTC data at the LTC IN A/B sockets is filered by U1 (TL084) and Schmitt triggered by U2, 3 (LM311) to produce LTCINA and LTCINB to be sent to the TR1 decoder (U14 on ESP-MIDI). The TR1 decoder uses the 8MHz LTCCLK input to interpret the encoded input. Every frame received generates an interrupt on *TCINT to be sent to the ESP-SYN Card.

  • Page 288: Aes Sync In And Out

    20.2.4 AES SYNC IN AND OUT 1. Setup: Connect AES SYNC OUT to AES SYNC IN Type: ep xtal 32k The AES SYNC OUT will generate valid AES code at 32kHz. Once locked to the input, the display should show: AES SYNC OUTPUT AES SYNC INPUT Sample Rate...

  • Page 289: Aes Sync Generation

    The AES SYNC OUT will generate valid AES code at 48kHz. Once locked (may take several seconds) to the input, the display should show: AES SYNC OUTPUT AES SYNC INPUT Sample Rate Type Source Rate Detected Rate —————- —— —————- ——————- 48000Hz 48k 400ppm...

  • Page 290: Aes Sync Frequency

    Detected Rate: The incoming sample rate as detected by the decoder. 20.2.7 AES S REQUENCY 1. Setup: Connect AES SYNC IN to AES SYNC OUT Type: ep xtal 48k 2. Check that received frequency is approximately 48kHz. 3. Press q to exit diagnostic. 20.2.8 D IAGNOSTIC ESCRIPTION...

  • Page 291: Espltc Schematic

    20.3 ESPLTC S CHEMATIC 20 – ESPLTC LTC Card...
  • Page 292 MFX3 plus Service Manual...

  • Page 293: Esp9Pin 9P In Card

    21.0 ESP9PIN 9P 21 – ESP9PIN 9Pin Card...

  • Page 294: Block Diagram

    21.1 B LOCK IAGRAM SONY 9PIN 1 (MASTER) DB9M SONY 9PIN 2 SONYTX1,2 U3,4 (MASTER) SONYRX1,2 DB9M TRANSMIT & RECEIVE DRIVERS SONY 9PIN 2 (SLAVE) DB9F MFX MASTER OUT TO SLAVE VGAD15F IDC26 PCB U1,2 MFX SLAVE IN FROM MASTER TRANSMIT &...

  • Page 295: Diagnostics

    21.2 D IAGNOSTICS 21.2.1 R UNNING IAGNOSTICS System must have an ESP-SYN Sync Card and cable connecting it to the ESP-MIDI Card and the ESP-9PIN installed (other SIO modules need not be installed). Type: osk30 enters OSK30 operating system scdiag start Sync Card diagnostics (should get SC>...

  • Page 296: 21.2.2 9Pin Master Ports

    21.2.2 9PIN MASTER PORTS (1) Setup: Connect shorting plug to MACHINE A Connect shorting plug to MACHINE B Connect shorting plug to MACHINE SLAVE Type: (2) Press q to exit test. The diagnostic shows the status of transmission and reception of each byte sent (value shown in Send field).

  • Page 297: Fsync 1

    Note that port B is switched between driving MACHINE SLAVE and MACHINE B. Diagnostic Description The diagnostic sets SONYSEL low to select reception on SONYRX2 to be from MACHINE B port. Transmitter interrupts for U24 (68681 duart) are enabled for both serial ports which immediately generates an interrupt on *SERINT as the ports are ready to transmit.

  • Page 298: Multi Mfx Ports (Serial Interface)

    21.2.4 M MFX P ULTI ORTS SERIAL INTERFACE (1) Setup: Connect shorting plug to MFX IN Connect shorting plug to MFX OUT Type: (3) Press q to exit test. Upon success, the display will show: TEST 1 TEST 2 Send OUT IN OUT IN ——...

  • Page 299: Multi Mfx Control Signals

    21.2.5 M ULTI CONTROL SIGNALS (1) Setup: Connect shorting plug to MFX IN Connect shorting plug to MFX OUT Type: (2) Check that signals *ZTPS (U1/9), WCLKS (U1/15), *ZTPM (U2/5) and WCLKM (U2/11) are clocking and at the same rate. Press any key other than q to swap to fast clocking and recheck signals.

  • Page 300: Esp9Pin Schematic

    21.3 ESP9PIN S CHEMATIC MFX3 plus Service Manual...

  • Page 301: Espdmb Digital Mother Board

    22.0 ESPDMB D IGITAL OTHER OARD 22 – ESPDMB Digital Mother Board...

  • Page 302: Espdmb Description

    22.1ESPDMB D ESCRIPTION 22.1.1 I NTRODUCTION The ESP-DMB8 is a non-expandable mother board with 2 slots for ESP-DCC Digital Channel Cards to provide 8 tracks of disk-recording. The ESP-DMB24 has 8 slots for ESP- DCCs; 6 are required for 24 tracks of disk-recording, and the other 2 are future expansion slots.

  • Page 303: Espdmb8 Schematics

    22.2 ESPDMB8 S CHEMATICS 22 – ESPDMB Digital Mother Board...
  • Page 304 MFX3 plus Service Manual...
  • Page 305 22 – ESPDMB Digital Mother Board...
  • Page 306 MFX3 plus Service Manual...
  • Page 307 22 – ESPDMB Digital Mother Board...
  • Page 308 MFX3 plus Service Manual...

  • Page 309: Espdmb24 Schematics

    22.3 ESPDMB24 S CHEMATICS 22 – ESPDMB Digital Mother Board...
  • Page 310 MFX3 plus Service Manual...
  • Page 311 22 – ESPDMB Digital Mother Board...
  • Page 312 MFX3 plus Service Manual...
  • Page 313 22 – ESPDMB Digital Mother Board...
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  • Page 315 22 – ESPDMB Digital Mother Board...
  • Page 316 MFX3 plus Service Manual...
  • Page 317 22 – ESPDMB Digital Mother Board...
  • Page 318 MFX3 plus Service Manual...

  • Page 319: Espamb Analogue Mother Board

    23.0 ESPAMB A NALOGUE OTHER OARD 23 – ESPAMB Analogue Mother Board...

  • Page 320: Amb8 Schematics

    23.1 AMB8 S CHEMATICS MFX3 plus Service Manual...

  • Page 321: Amb24 Schematics

    23.2 AMB24 S CHEMATICS 23 – ESPAMB Analogue Mother Board...
  • Page 322 MFX3 plus Service Manual...

  • Page 323: Ear I/O C

    24.0 ESPRIO R I/O C 24 – ESPRIO Rear I/O Card...

  • Page 324: Esprio Block Diagram

    24.1 ESPRIO B LOCK IAGRAM MFX3 plus Service Manual...

  • Page 325: Esprio Description

    24.2 ESPRIO D ESCRIPTION The RIO rear I/O card provides a mounting system for the I/O ports of the WX and CG4. It also incorporates the circuitry and functionality of the ESP-RGB board (which is no longer required). The I/O devices on the RIO are; the WX reset switch, the WX modem port, the CG4 RGB output and the CG4 HSSL port.

  • Page 326: Hssl External Loopback Plug

    24.2.5 HSSL E XTERNAL OOPBACK PLUG An external loopback plug can be made using a male solder bucket 25 way D connector (ie Farnell 150-810). The following connections should then be made on this connector : Pin 2 <—> Pin 8 Pin 3 <—>...

  • Page 327: Esprio Schematics

    24.3 ESPRIO S CHEMATICS 24 – ESPRIO Rear I/O Card...
  • Page 328 MFX3 plus Service Manual...

  • Page 329: Mfx Console

    25.0 MFX C ONSOLE 25 – MFX Console...

  • Page 330: Mfx010 Conroller Card Description

    25.1 MFX010 C ONROLLER ESCRIPTION The MFX keyboard is a console designed to facilitate the use of post-production software on the MFX. The MFX keyboard contains two circuit boards. MFX010 is the controller board for the MFX console, containing the Microprocessor. The other board, MFK, is used to decode the switches and trigger keys.

  • Page 331: Non-Volatile Ram

    processor is reset. The MFX keyboard has been designed to allow downloading of software from the Series III CMI, eliminating the need for costly EPROM updates. The task of the boot code in the EPROM’s is to move the application code from the non-volatile memory to the RAM for execution. 25.1.4 N VOLATILE (refer schematic MFX010-MEMORY (page 3 of 8))

  • Page 332: Led Circuitry

    25.1.6 LED C IRCUITRY (refer schematic MFX010-DISPLAY (page 6 of 8)) The LED’s controlled by the MFX are arranged into rows and columns, and lit using a multiplexed scheme. Under this scheme each LED is pulsed on for 1ms with a high current, and then turned off for 7ms.

  • Page 333: Displays

    1. MIDI to MIDI D on the MFX 2. MIDI from MIDI D on the MFX 3. Midi from the Fairlight music keyboard 4. RS422 to and from a LYNX synchroniser or other synchroniser supporting the ES Bus 5. RS232 to and from an MFX expansion device 6.

  • Page 334: 25.1.11 Ac1A1

    clock is used as the MIDI 16 times clocks. The 68C681 DUART has two transmit channels, and two receive channels. All channels have independent baud rates. An internal, 16-bit counter can be programmed in a variety of ways to act as a timer, counter or frequency generator. An 8-bit output port is provided, with some of the bits being able to provide status information.

  • Page 335: Speaker

    recommended by the MIDI specifications. The MlDI transmitter is a BC549 transistor (Q7), which makes this circuit more rugged than the usual 7407 open-collector transmitter circuit. The tape synchroniser is interfaced using a DS8921 RS422 transmit receiver pair (U3), The driver has a source impedance of 110ohm and a low-pass filter.

  • Page 336: Jogger Wheel

    25.1.17 J OGGER WHEEL (refer schematic MFX010-DRIVERS (page 5 of 8)) The MFX supports the decoding of an optical shaft encoder. The quadrature output of the encoder is pulled up and low-pass filtered before being buffered by a 74HC132-schmitt-trigger (U18). The outputs of the Schmidt trigger are fed to ACIA2 (U10), input port bits IPO and lP1. The DUART can be configured to cause an interrupt on the edge of the quadrature signal.

  • Page 337: Mfx Console Diagnostics

    one diode network will have its cathode near GND, allowing its diodes to conduct if the attached switches are closed. 25.2 M ONSOLE IAGNOSTICS 1. To reset the non-volatile RAM in the MFX console switch OFF power and hold down numeric keypad keys 1:2:3.

  • Page 338: Mfx Cable Pinouts And Specifications

    Cabg8529 MFXP 1 of 2 Connect rev 1-3.dc with Metal Backshell of cable screens Ferrites to be FairRite P/N 2643626402 Fairlight P/N FERB0110) Cover ferrites with heatshrink Ferrite C O N S O L E C O N N E C T I O N...
  • Page 339 R E V . D A T E D E S C R I P T I O N Z O N E &$%*0);3OXV&DEOH&RQQHFWLRQ'LDJUDP 16/12/96 L.Stewart 16/1/96 L.Stewart Cable Spec & Connections 27/8/98 M.Paolino Signal names corrected (Midin / out) NOTES : Previous change reversed.

  • Page 340: Mfx010 Controller Card Schematics

    25.4 MFX010 C ONTROLLER CHEMATICS MFX3 plus Service Manual...
  • Page 341 25 – MFX Console...
  • Page 342 MFX3 plus Service Manual...
  • Page 343 25 – MFX Console...
  • Page 344 MFX3 plus Service Manual...
  • Page 345 25 – MFX Console...
  • Page 346 MFX3 plus Service Manual...
  • Page 347 25 – MFX Console...

  • Page 348: Mfk Schematics

    25.5 MFK S CHEMATICS MFX3 plus Service Manual...
  • Page 349 25 – MFX Console...
  • Page 350 MFX3 plus Service Manual...
  • Page 351 25 – MFX Console...
  • Page 352 MFX3 plus Service Manual...
  • Page 353 25 – MFX Console...
  • Page 354 MFX3 plus Service Manual...
  • Page 355 25 – MFX Console...
  • Page 356 MFX3 plus Service Manual...
  • Page 357 25 – MFX Console...
  • Page 358 MFX3 plus Service Manual...

  • Page 359: Mfx3 Specifications And

    26.0 MFX3 S PECIFICATIONS AND INOUTS 26.1 S PECIFICATIONS 26.1.1 A NALOG NPUTS AND UTPUTS Number: Input impedence: >10k Ohms Output impedence: < 55 Ohms Maximum input level: +22dBu Maximum output level: +22dBu Input Gain range: -96dB to +30dB (limited to +16dB by user interface) Swichable between -10dbV and +4dBu reference.

  • Page 360: Aes/Ebu Outputs

    26.1.4 AES/EBU O UTPUTS Number: 12 (pairs) Output level: Output impedence: 110 Ohms transformer isolated Output frequency: 32kHz -5% to 48kHz +5% (locked to sync source) 26.1.5 SPDIF O UTPUTS Number: 12 (pairs) Output level: 0.5V Output impedence: 75 Ohms Output frequency: 32kHz -5% to 48kHz +5% (locked to sync source)

  • Page 361: Ltc Inputs

    26.1.8 LTC I NPUTS Number: Input level: -20dBu to +10dBu Input impedence: >10k Ohms Input rate: 1/80 x playspeed to 30 x playspeed 26.1.9 LTC O UTPUT Output level: 0dBu Output impedence: 33 Ohms Output rate: locked to playback rate 26.1.10 AES S YNC INPUT Minimum differential:...

  • Page 362: Video Sync/ Vitc Input

    26.1.13 V / VITC IDEO INPUT Note: VITC Input is not currently supported Impedence: 75 Ohms terminated Level: 0.5V to 2V Field rate: 24Hz -5% to 60Hz +5% 26.1.14 S LAVE Standard 26.1.15 S ASTER Standard 26.1.16 GPO Output type: Open collector Maximum voltage: Maximum current:...

  • Page 363: Pinout Information

    26.2 P INOUT NFORMATION 26.2.1 A NALOGUE NPUTS Connectors 1x 15 pin D-mini Female Input Balanced Input level +22 dBu max Input sensitivity -10 dBu / +4 dBu switched Input attenuation range 14 dB to -99 dB Input impedance > 10K ohm Pin 1 Frame Ground Pin 2...

  • Page 364: Analogueoutputs

    26.2.2 A NALOGUE UTPUTS Connectors 1x 15 Pin D-mini Male Output Electronic Balanced Differential Output Level +22 dBu max at 0 dB digital full scale (nominal +4 dBu) Output impedance < 55 ohms Output load 600 ohms minimum Pin 1 Frame GND Pin 2 OUT 1 GND...

  • Page 365: 26.2.3 Aes / Ebu Input

    26.2.3 AES / EBU INPUT Connector 37 way D-mini Female Channels 2 x Stereo pairs per I/O Module Sample Rates 44.1 KHz , 48.0 KHz, 32 KHz, 44.056 KHz Input Type 200 mv Differential Minimum Input Level +22 dBu Peak Pin 17 AES IN 1 GND Pin 18...

  • Page 366: 26.2.5 Spdif Output

    26.2.5 SPDIF OUTPUT Connector 37 way D-mini Female Channels 2 Stereo pairs per I/O Module Sample Rates 44.1 KHz, 48 KHz, 32 KHz, 44.056 KHz Output Level 0.5v p-p Pin 10 SPDIF OUT 1 Pin 11 SPDIF OUT 2 Pin 28 SPDIF OUT 1 GND Pin 29 SPDIF OUT 2 GND...

  • Page 367: Ltc Output

    26.2.8 LTC OUTPUT XLR Male 0 dBm Pin 1 Pin 2 OUT+ Pin 3 OUT - 26.2.9 AES SYNC I NPUT XLR Female Pin 1 Pin 2 IN + Pin 3 26.2.10 AES SYNC OUT XLR Male Pin 1 Pin 2 OUT + Pin 3 OUT -...

  • Page 368: Video Sync Input

    26.2.12 V IDEO NPUT BNC 1v p-p 75 Ohms terminated 26.2.13 M N AND MFX IN and MFX OUT are not currently used. MFX OUT MFX IN DB15 VGA Female DB15 VGA Female Pin 1 Pin 1 Pin 2 TXS- Pin 2 RXM- Pin 3...

  • Page 369: 9-Pin

    26.2.14 9-P SONY A, SONY B SONY SLAVE DB9 Male DB9 Female Pin 1 Pin 1 Pin 2 Pin 2 Pin 3 Pin 3 Pin 4 Pin 4 Pin 5 Frame sync Pin 5 Frame sync Pin 6 Pin 6 Pin 7 Pin 7 Pin 8...

  • Page 370: General Purpose Outputs

    26.2.18 G ENERAL URPOSE UTPUTS DB9 Male Open Collector 30v max, 40 mA max Pin 1 Pin 2 GPO1 Pin 3 GPO2 Pin 4 GPO3 Pin 5 GPO4 Pin 6 GPO5 Pin 7 GPO6 Pin 8 GPO7 Pin 9 GPO8 26.2.19 S (RS232) ERIAL...

  • Page 371: Mfx Console Connection

    26.2.21 M ONSOLE ONNECTION Centronics 24 pin Female Pin 1 Pin 13 Pin 2 Pin 14 Pin 3 Pin 15 Pin 4 Pin 16 Pin 5 TX422+ Pin 17 TX422- Pin 6 RX422+ Pin 18 RX422- Pin 7 KEY+ Pin 19 KEY- Pin 8 MFX Sense...

  • Page 372: Printer

    Baud-Rate 38400 or 9600, 8 bits, 1 stop bit, No Parity. SERIAL INPUT printers ONLY. EPSON ESC/P - 9 pin protocol or ESC/P2 - 24 pin protocol (preferred). Serial cable when using DTR handshaking: Fairlight Printer Sync I/O RS232 D9 Male...

  • Page 373: Mfx Console Pinouts

    26.2.24 MFX C ONSOLE INOUTS Centronics 24 pin Female Pin 1 Pin 2 Pin 20 Pin 3 Pin 21 Pin 4 Pin 22 Pin 5 Pin 23 Pin 6 Data 1 Pin 24 Data 2 Pin 7 KBD232 Pin 25 Pin 8 MIDI OUT + Pin 26...
  • Page 374 MFX3 plus Service Manual...

  • Page 375: Software

    27.0 S OFTWARE 27.1 A PPLICATION OMPONENTS The MFX3plus is divided up into approximately 32 directories and about 572 files. The root level directory on of a MFX3plus boot drive contains 6 files that are required to run the application. The number of files and directories varies from release to release. In revision 14, the root level directory is also where projects (.MT files) are found.
  • Page 376 CMDS/umacs USR/CMDS/dfn_backup CMDS/unlink USR/CMDS/dfn_tbackup CMDS/xmode USR/CMDS/dfnserver CMDS/BOOTOBJS/nil USR/CMDS/dgt00x00_000 CMDS/BOOTOBJS/null USR/CMDS/differ CMDS/BOOTOBJS/pcf USR/CMDS/dinfo CMDS/BOOTOBJS/pipe USR/CMDS/diskinit CMDS/BOOTOBJS/pipe2 USR/CMDS/drt CMDS/BOOTOBJS/pipeman USR/CMDS/dtst CMDS/BOOTOBJS/ram USR/CMDS/dubchart CMDS/BOOTOBJS/rbsccs USR/CMDS/dvcs CMDS/BOOTOBJS/rbvccs USR/CMDS/e CMDS/BOOTOBJS/sbf USR/CMDS/ed SYS/errmsg USR/CMDS/errmesg SYS/loadisp USR/CMDS/erx SYS/moded.fields USR/CMDS/espfind SYS/motd USR/CMDS/esprz SYS/password.release USR/CMDS/espsz SYS/qsys.cfg USR/CMDS/fame SYS/startisp USR/CMDS/fame2 SYS/startnfs.client USR/CMDS/famesession SYS/startnfs.server...
  • Page 377 USR/CMDS/lzw USR/CMDS/tcopy USR/CMDS/march USR/CMDS/telix USR/CMDS/mdrcheck USR/CMDS/timer USR/CMDS/mdrmsg USR/CMDS/tod_pd USR/CMDS/mdrstart USR/CMDS/tofame USR/CMDS/mdump USR/CMDS/totvt USR/CMDS/mediad USR/CMDS/trace USR/CMDS/mfx3 USR/CMDS/traw USR/CMDS/mfxecho USR/CMDS/tree USR/CMDS/mfxload USR/CMDS/tvtsave USR/CMDS/mfxmouse USR/CMDS/tvtemu USR/CMDS/mfxsession USR/CMDS/tvterm USR/CMDS/mfxstart USR/CMDS/unwrap USR/CMDS/mfxstartf USR/CMDS/upgrade USR/CMDS/mfxstartf2 MFX Software upgrade utility USR/CMDS/mfxstartft USR/CMDS/uudecode USR/CMDS/mlist USR/CMDS/uuencode USR/CMDS/monitor USR/CMDS/ved USR/CMDS/move USR/CMDS/viddy USR/CMDS/mrestore USR/CMDS/wrap...
  • Page 378 USR/CMDS_WX/BOOTOBJS/ipconfig USR/CMDS/MFX/mdrfade_pb USR/CMDS_WX/BOOTOBJS/irqcount USR/CMDS/MFX/mdrfiles_pa USR/CMDS_WX/BOOTOBJS/macfm USR/CMDS/MFX/mdrfs USR/CMDS_WX/BOOTOBJS/mdrfm USR/CMDS/MFX/mdrint USR/CMDS_WX/BOOTOBJS/mfx232 USR/CMDS/MFX/mdrioq_pb USR/CMDS_WX/BOOTOBJS/mfxd USR/CMDS/MFX/mdrlevel_pb USR/CMDS_WX/BOOTOBJS/mouse USR/CMDS/MFX/mdrmarks_pb USR/CMDS_WX/BOOTOBJS/moused USR/CMDS/MFX/mdrmpatch_pa USR/CMDS_WX/BOOTOBJS/flfs USR/CMDS/MFX/mdrname_pa USR/CMDS_WX/BOOTOBJS/nvr USR/CMDS/MFX/mdrpassword_pb USR/CMDS_WX/BOOTOBJS/nvramd USR/CMDS/MFX/mdrpatch_pa USR/CMDS_WX/BOOTOBJS/osksyscalls USR/CMDS/MFX/mdrrtfx_pb USR/CMDS_WX/BOOTOBJS/p1 USR/CMDS/MFX/mdrscitask USR/CMDS_WX/BOOTOBJS/p2 USR/CMDS/MFX/mdrtake_pb USR/CMDS_WX/BOOTOBJS/qc USR/CMDS/MFX/mdrtracks_pa USR/CMDS_WX/BOOTOBJS/qssd USR/CMDS/MFX/mdruser_pa USR/CMDS_WX/BOOTOBJS/qterm USR/CMDS/MFX/mdrwaves_pb USR/CMDS_WX/BOOTOBJS/pc USR/CMDS/MFX/mdrwavex_pb USR/CMDS_WX/BOOTOBJS/r0 USR/CMDS/MFX/mdrwavi_pb USR/CMDS_WX/BOOTOBJS/r1 USR/CMDS/MFX/mdrwfld USR/CMDS_WX/BOOTOBJS/rbgen USR/CMDS/MFX/mdrwsmain USR/CMDS_WX/BOOTOBJS/rbuccs...
  • Page 379 USR/DCC/mix.bin USR/XILINX/x_pll.bin USR/MFX/.login USR/XILINX/x_pll16.bin USR/MFX/abase.form USR/XILINX/x_pll17.bin USR/MFX/abase.pform USR/XILINX/x_pll18.bin USR/MFX/mfx.raw USR/XILINX/x_syn.bin USR/MFX/mfk.raw USR/XILINX/ADDRESS.bin USR/MFX/mfk2.raw USR/XILINX/AXDATA.bin USR/MFX/mfx.dummy USR/XILINX/AXDATA2.bin USR/QSYS/diotask USR/XILINX/DXDATA.bin USR/QSYS/qctest USR/XILINX/DXTEST1.bin USR/QSYS/qmfx USR/XILINX/DXTEST2.bin USR/QSYS/qmfxcomms USR/XILINX/REGISTER.bin USR/QSYS/qmidia USR/XILINX/VIDADD.bin USR/QSYS/qprocs USR/XILINX/wb.bin USR/QSYS/qprinter USR/XILINX/wbgs.bin USR/QSYS/qshell USR/XILINX/wbgb.bin USR/QSYS/qsonic USR/XILINX/wbgsp.bin USR/QSYS/qsys USR/XILINX/wbgbp.bin USR/SC/.login CMDS/arpstat USR/SC/CMDS/scdiag CMDS/exportfs USR/SC/CMDS/BOOTOBJS/osk30kernel CMDS/ftp USR/QSYS/TCS/cman...
  • Page 380 CMDS/BOOTOBJS/ISP/netdb_resolv CMDS/BOOTOBJS/ISP/netdb_small CMDS/BOOTOBJS/ISP/nfs CMDS/BOOTOBJS/ISP/nfs_devices CMDS/BOOTOBJS/ISP/nfsnul CMDS/BOOTOBJS/ISP/pk CMDS/BOOTOBJS/ISP/pkdvr CMDS/BOOTOBJS/ISP/pkman CMDS/BOOTOBJS/ISP/pks CMDS/BOOTOBJS/ISP/sockdvr CMDS/BOOTOBJS/ISP/sockman CMDS/BOOTOBJS/ISP/tcp CMDS/BOOTOBJS/ISP/udp CMDS/BOOTOBJS/ISP/af_ether CMDS/BOOTOBJS/ISP/af_unix USR/CMDS/remotedc USR/CMDS/remoted USR/HTTP/FairlightLogo.gif USR/HTTP/UnderConstruction.gif USR/HTTP/bullet2.gif USR/HTTP/index.html USR/HTTP/line.gif USR/HTTP/riffmci.html USR/HTTP/rule18.gif USR/HTTP/sh.html USR/HTTP/slurrytile.gif USR/HTTP/AB/absrch.cgi USR/HTTP/AB/absrch.html ETC/Makefile ETC/host.conf ETC/hosts ETC/hosts.equiv ETC/inetdb ETC/inetd.conf ETC/networks ETC/nfs.map ETC/nfsd.map ETC/protocols ETC/readme.txt ETC/resolv.conf ETC/rpc ETC/rpcdb ETC/services...

  • Page 381: Upgrading 14.2 Software Revisions

    27.2 U 14.2 S PGRADING OFTWARE EVISIONS 27.2.1 F XABYTE 1. Connect Exabyte drive, set to ID 5. 2. Power up the Exabyte drive and insert software tape. plus 3. Power up (or restart) the MFX3 4. At Disk Recorder project page Type: quit <return>. You will be prompted “Close project and shutdown all applications”...

  • Page 382: From Hard Disk Drive

    27.2.2 F RIVE 1. Connect drive with software release file, set to ID to one of the following addresses that is not used by any other device on the SCSI chain 1,2,3,4 or 6. 2. Power up all drives. plus 3.

  • Page 383: Upgrading 15.1 Software Revisions

    27.3 U 15.1 S PGRADING OFTWARE EVISIONS Upgrading software in 15.1 is more complicated than our previous releases. These steps apply for both TurboSCSI and PCI Systems. This information should assist you: IMPORTANT TIPS: If you are upgrading from 14.2 to 15.1, a new file called /nvr/setup must be created. Please follow steps 1-22 For succeeding installations of Rev 15.1 please follow Steps 1-3 and 6-22.
  • Page 384 must be unique for each machine on the network. 7. Install release 15.1.X using file 15_1_XX.gz 8. Disconnect the machine from the 100 Base Hub (if used). 9. Restart MFX3 10. Login as mfx as in step 4. 11. Remove the modules inetdb and rpcdb from memory by repeatedly typing “unlink inetdb<RETURN>”...

  • Page 385: 28 - Disk Drives

    28.1.1 RBF RBF (Random Block File) is OS-9’s native disk file system. RBF supports drives up to approx. 4 GBytes capacity, with a maximum file size of 4 GBytes. This format is used in Fairlight systems from Rev 14 upwards.

  • Page 386: 28.1.2 Flfs

    FLFS supports drives of up to 200 GBytes, with a maximum individual file size of 4 GBytes. This format is used in Fairlight systems from Rev 14.2 upwards. (Note: Boot drives cannot be FLFS) To initialise a disk drive with the FLFS file format : 1) Connect the drive to the SCSI chain of an MFX3plus.

  • Page 387: 28.1.4 Hfs

    5) Type: boot <return> . 28.1.4 HFS HFS (Hierarchical File System) is the Macintosh file system. Fairlight MFX systems can read this file system, and it is used to transport OMF files from Macintosh based systems such as Avid Media Composer and Digidesign ProTools.

  • Page 388: 388

    FAT-16 (File Allocation Table) supports partitions of up to 2 GBytes, with a maximum file size of 2 GBytes. Fairlight MFX can read and write this disk file system, and it is used to transport WAVE files and other file types between MFX and products based on the PC.
  • Page 389 5. Format the disks to FAT16 using MS-DOS format utility by executing the following command: C:\> format X: <return> Where ‘X’ is the ‘drive letter‘ of the partition created earlier by fdisk. 6. Repeat the above command for any other newly created partitions. 7.
  • Page 390 MFX3 plus Service Manual...

  • Page 391: Media Link

    29.0 M EDIA 29.1 M – D EDIA OFTWARE ESCRIPTION Medialink Windows NT software provides the fast link between network interfaces and various applications that are necessary for operation of MediaLink network. Network protocols used for MediaLink connections are UDP/IP used for ANETD connections and TCP/IP used for DFNSERVER connections.

  • Page 392: Media Link Software - Fairlight Nt Applications

    Module DISKPERF.SYS currently doesn’t have a revision number and it cannot be verified It is essential that all the machines on a same network should run ANETD.EXE and DFNSERVER.EXE modules that were extracted from the same FAIRLIGHT MFX3+ distribution that runs on client MFX3+ machines.

  • Page 393: Appendices

    30.0 A PPENDICES 30.1 MFX3 L EVEL ODIFICATION MFX3 is shipped with a nominal level of +4dBu and +18dB headroom (i.e. +22dBu peak). This comforms to the Australian and American digital audio standards (although these standards are only a guideline). To modify the level settings, the nominal level in dBu and headroom in dB must be known.

  • Page 394: Settings For Other Standards

    30.1.2 S ETTINGS FOR OTHER STANDARDS Assumes the nominal level and headroom are known. 1. Determine the peak dB level PEAK (dBu) = nominal(dBu) + headroom (dB) + 0.5dB Usually the peak level is over estimated to ensure the requested headroom. 0.5dB has been added in the above to account for variations in ADC and DAC peak levels (±0.4dB).

  • Page 395: Error Codes

    30.2 E RROR ODES 255:255 Operation Failed 082:001 No Project File 082:002 Feature Not Available in this Release 082:003 File Already Exists - Delete Existing File First 082:004 Cant Get Free Space From Current Device 082:005 Space List Full 082:006 Bad File Descriptor 082:007 MFX File Already Exists 082:008 Bad Channel Number 082:009 Track Is Not Stereo...
  • Page 396 082:047 DCC Not Responding 082:048 Max Clip Duration Exceeded (2047 Megabytes) 082:049 No Selected Clip At Current Position 082:050 Bad File Type 082:051 Eq System Error 082:052 MFX Console has Wrong Software Revision 082:053 Can’t Attach The Current Project 082:054 Track-Lock Protocol Error 082:055 No Clip To Keep 082:056 Cannot Edit Library File 082:057 No Library File Open...
  • Page 397 082:093 Too Many GFX Modules 082:094 Invalid GFX Module 082:095 Waveform Not Available 082:096 File Layout Violation 082:097 Invalid Space List 082:098 Not Enough Disk Space 082:099 Range Edge Is At Head Of Clip 082:100 Range Edge Is At Tail Of Clip 082:101 No Clip At Range ‘From’...
  • Page 398 082:240 Incorrect Machine Type 000:001 Operation Terminated 000:002 Keyboard Quit 000:003 Keyboard Interrupt 000:032 Abort 000:033 Erroneous Math Operation 000:034 Illegal Function Image 000:035 Segment Violation (Bus Error) 000:036 Termination Request 000:037 Alarm Time Elapsed 000:038 Write To Pipe With No Readers 000:039 User Signal #1 000:040 User Signal #2 000:041 Address Error...
  • Page 399 000:124 Spurious Interrupt 000:133 An Uninitialized User Trap (1-15) Was Executed 000:148 Floating Point Unordered Condition 000:149 Floating Point Inexact Result 000:150 Floating Point Divide By Zero 000:151 Floating Point Underflow 000:152 Floating Point Operand Error 000:153 Floating Point Overflow 000:154 Floating Point Not A Number 000:155 Floating Point Unimplemented Data Type 000:156 Pmmu Configuration...
  • Page 400 000:214 File Not Accessible 000:215 Bad Pathlist 000:216 File Not Found 000:217 File Segment List Is Full 000:218 Creating An Existing File 000:219 Illegal Memory Block Address 000:220 Modem Data Carrier Lost 000:221 Module Not Found 000:222 System Clock Not Running 000:223 Deleting Stack Memory 000:224 Illegal Process Id 000:225 Bad Irq Parameter...
  • Page 401 006:003 Region Definition Full (Overflow) 006:004 Unallocated Identifer Number 006:005 Null Region 006:006 Bad Drawmap/Pattern Mode 006:007 No Active Font 006:008 No Drawmap 006:009 No Audio Play In Progress 006:010 Audio Record/Play Has Been Aborted 006:011 Audio Queue Is Full 006:012 Audio Processor Is Busy 006:100 No Free Slot Is Left In The Resource Table 006:101 The Specified Resource Module Id Is Not A Valid Slot...
  • Page 402 006:160 Line Table Overflow 006:161 Text Too Long (Maximum Is 65535) 006:162 Bad Type Or Type Not Implemented 006:163 Attempt To Draw A Line Too Long 006:164 Need A Line Table 006:165 Font Not Set In The Drawmap 006:166 Bad Rectangle 006:180 Global Variable Error 006:185 No Preference Module 006:186 Illegal Argument...
  • Page 403 007:024 Too Many References 007:025 Connection Timed Out 007:026 Connection Refused By Target 007:027 Mbuf Too Small For Mbuf Operation 007:028 Socket Module Already Attached 007:029 Path Is Not A Socket 008:001 Line Down Or Layer 1 Error On Attach. 008:002 Connection Error - Connection Not Made.
  • Page 404 150:023 Can’t Perform Operation 150:024 Invalid File ID 150:025 DFN Internal Problem 150:026 Not A Directory 150:027 No Permission 150:028 File Table Full 150:029 File Hasn’t Been Locked 150:030 Not Cached 150:031 File in Use - Cannot Open 150:032 File Already Marked 150:033 Backup/Restore/Copy Already In Progress 150:034 Arch Unit No Longer Valid 150:035 No Backup In Progress...
  • Page 405 111:023 DCC BTDI high 111:030 DCC Program Init Failed - Timeout 111:040 DCC Debug Request Timeout 111:050 DCC-MDR - Unknown Request Code 111:051 DCC-MDR - Invalid Parameter 111:052 DCC-MDR - Invalid Overlay Address 111:060 ODIF Path Already Open 111:061 ODIF Path Not Open 111:062 ODIF Open Mode Error 111:063 ODIF I/O Mode Error 111:100 DCC Startup Failed - Timeout...
  • Page 406 151:004 OMF Error Sample Read 151:005 OMF Error Sample Write 151:006 OMF Error Decompress 151:007 OMF No Data 151:008 OMF Source MOB List 151:009 OMF No Media Descriptor 151:010 OMF Bad TIFF Version 151:011 OMF Bad Descriptor Sample Rate 151:012 OMF Bad Descriptor Length 151:013 OMF Buffer To Small 151:014 OMF Internal MDO error 151:015 OMF Bad Compression Format...
  • Page 407 151:050 OMF Bad Q Table 151:051 OMF Bad AC Table 151:052 OMF Bad DC Table 151:053 OMF Bad Frame Index 151:054 OMF Bad Frame Offset 151:055 OMF Bad Data Address 151:056 OMF Bento Problem 151:057 OMF Bad Object 151:058 OMF Bad Index 151:059 OMF Internal ANF 151:060 OMF Bad A Structure 151:061 OMF Internal NAT...
  • Page 408 151:096 OMF Invalid LRC BLEN 151:097 OMF LRC Descriptor Error 151:098 OMF LRC Mono Only 151:099 OMF LRC Bad Sample Size 151:100 OMF LRC No Seek 071:001 GFX Unknown Attribute Type 071:002 GFX Invalid Attribute Value 071:003 GFX Incompatible or Unknown Graphics Card 071:004 GFX Control Latch Error 071:005 GFX Invalid GFX Object 071:006 GFX Link Error...
  • Page 409 146:028 Flight - AckPort Released 254:001 ESPMSG Too Many Receivers 254:002 ESPMSG Too Many Senders 254:003 ESPMSG Too Many Ports 254:004 ESPMSG No Receiver For Port 254:005 ESPMSG No Sender 254:006 ESPMSG Version Error 254:007 ESPMSG Invalid Port Id 254:008 ESPMSG Invalid Receiver Id 254:009 ESPMSG Not Owner Of Receiver 254:010 ESPMSG Port Already Linked To Receiver 254:011 ESPMSG Global Directory Module Not Linked...
  • Page 410 083:019 Cant Get Media Catalogue Number From CD 083:020 Unable to Get Table of Contents From CD 083:021 Cant Get ISRC Number From CD 083:022 Can’t get size of Audio File 083:023 Can’t Seek to Start of Audio File 083:024 Could not Read in WAV Header 083:025 RIFF ID Not Found in WAV File Header 083:026 WAVE ID Not Found in WAV File Header 083:027 FORMAT ID Not Found in WAV File Header...

  • Page 411: Blue Key Reference

    30.3 B EFERENCE A - Arm Shows the amount of recording time left on the current disk drive, the record mode, the monitor mode and the level meters. D - Devices Shows the devices currently connected to the system. E - EQ Shows the EQ applied to a clip.

  • Page 412: Os/9 Commands

    30.4 OS/9 C OMMANDS Function: Display or change file attributes Syntax: attr [<opts>] {<path> [<opts>] <permissions>} Attributes: d s pe pw pr e w r ‘-’ turns attribute on ‘-n’ turns attribute off Options: do not print attributes after changes directory to search is execution directory get list of file names from standard input -z=<path>...
  • Page 413 Function: Generate crc for a file Syntax: crc [-<options>] <file> [-<options>] Options: generate default output file -f=<file> specify output file display help replace output file Function: Display system date and time Syntax: date [<opts>] Options: print day, seconds past midnight in julian time print hour:minute:sec in military format Dcheck...
  • Page 414 ELDIR Function: Delete a directory Syntax: deldir [<opts>] {<dir> [<opts>]} Options: delete directories without asking questions delete files with no write permission get list of directory names from standard input -z=<path> get list of directory names from <path> Function: Print Disks/Tape Drives Found and Mounted on The System Syntax: df [<opts>] Options:...
  • Page 415 ISKINIT Function: Initialise a disk drive Syntax: diskinit <device>[ <size>] <device> = device name <size> = total sectors (DD.TOT) (dec or $hex) Options: -a=<number of allocated sectors> -c=<sectors/cluster> (default = 1) -d=<min sectors in root dir> ... <device> is image file -m=<max sectors in bit map>...
  • Page 416 Dont Limit Test to 4096 MB Do non seek test on last <option r> Mb of Disk -www Write to Disk !!!!! Dont Attempt to Find Sync Card Shared RAM Print Seek Table -l=<num> Run Task at priority <num> (default:1024) Dont restore synchronous variables on exit DMA into DCC Memory Function: Formatted display of contents of a device...
  • Page 417 Function: Find a file Syntax: find [<opts>] [<root directory>] <file> Options: show directories searched find all occurrences Function: Report free space on disk Syntax: free [<opts>] {<device> [<opts>]} Options: -b=<size> buffer size Function: Connect to a remote internet site and transfer files Syntax: ftp [<opts>] [<host>] [<opts>] Options:...
  • Page 418 Function: Searches input module for lines matching expression Syntax: grep [<opts>] [<expression>] {[<path>] [<opts>]} Options: count match lines -e=expr same as simple expression -f=file read ‘file’ for expression(s) print only filenames with matches number each output line (file relative) silent mode invert sense of compare (list non-matches) get list of file names from standard input -z=<path>...
  • Page 419 Function: Link a module in memory Syntax: link [<opts>] {<modname> [<opts>]} Options: get list of module names from standard input. -z=<path> get list of module names from <path> Function: List a file Syntax: list [<opts>] {<path> [<opts>]} Options: get list of file names from standard input -z=<path>...
  • Page 420 Function: Keep track of modules for a file Syntax: make {[<-opts>] [< target file >] [< macros >]} Options: don’t use built-in rules don’t use built-in rules for object files debug mode, print out the file dates in makefile double debug mode, very verbose -f[=]<xxx>...
  • Page 421 Keep filenames as is when doing a transfer List Library files within MDR Files Extract files from Archive Device Debug Enable Function: Creates boot on disk Syntax: os9gen {<opts>} <device> {<path>} {<opts>} Options: -b=<size> copy buffer size (default 64k) extended boot (large >64k or fragmented) -q=<path>...
  • Page 422 NLINK Function: Unlink modules from memory Syntax: unlink [<opts>] {<modname> [<opts>]} Options: get list of module names from standard input -z=<path> get list of module names from <path> PGRADE Function: Utility to Install an MFX release from File or Tape - Version 1.15 Syntax: upgrade -<options>...
  • Page 423 If only option t is specified then default SBF device is /mt0 The Default name of the release file when not a tape device is the name of the MFX revision in the current data directory. If filename ends in ‘/’ then it specifies the name of the directory in which the release file is to be created with default name If a source release file is specified with option u then an update file is generated to update from the source release to the current release.

  • Page 424: Ecns

    30.5 ECN The following pages contain tables detailing the current Engineering Chane Notices for the plus MFX3 MFX3 plus Service Manual...
  • Page 425 1mm exposed. Drill out the hole under RV2 to 4mm. Place a transistor standoff (Fairlight Part no: SDTD3001, RAE Part no: T05-Standoff) in the hole before placing the trim pot. This spacer is to keep the pot away from the board to avoid shorting tracks.
  • Page 426 Delete or remove 1k trim pot at RV2 (ESP part # POTR6117) ECN 152. pots on the MFX010 card are to moved to the MFK Solder cable assembly (Fairlight P/N CABM6259) into the holes (on component side) vacated by the card. above trim pots using the following connections;...
  • Page 427 4. Install 220R 1W resistors at R76 and R77. voltage selection between FAME and non FAME 5. Ensure, that for a Non FAME console, that the power cable from back panel to J1 is Fairlight P/N consoles will be done by moving two jumpers CABM2000.
  • Page 428 1. Change the Female D Connector at P4 to Plummer insufficient reach and therefore do not protrude far Fairlight P/N: JDF9062 enough out of the dress panel. This has been Desc: DB9M Footprint = 9.4mm reach, Solder locating lugs, Select Gold (Au) >= 0.25um/10u".
  • Page 429 5. Change Assembly Revision Label to Rev 1.1 Note to Subcontractors: Modify all WIP of AIO2_V5 Cards Note to Fairlight Production: Modify all WIP of AIO2_V5 Cards Changes to ECN 282.1: Items 3 and 4 in details added from withdrawn ECN 280. Special Note added.
  • Page 430 George THE TRACK Improve SNR to achieve a minimum of 97 dB 1. A multilayer ceramic capacitor added, SMD 0603, 68 pF, >/= 50V, +/- 20% or better (Fairlight part # Potkonyak CUTTING AND output level on all channels at all sampling rates.
  • Page 431 6. Link (0R0 Resistor, Fairlight Part No. RME0001) in location JP3 removed 7. Pads for Links (0R0 Resistor, Metal Film, >= 0.125W, 1%, SMD0805, Fairlight Part No. RME0001) in locations JP9, JP12, JP13, JP28 and JP29 added. Final configuration to be detrmined on test.
  • Page 432 27-Apr-99 Analog O/P Card George THE TRACK Improve SNR to achieve a minimum of 97 dB 1. A multilayer ceramic capacitor added, SMD 0603, 68 pF, >/= 50V, +/- 20% or better (Fairlight part # MFX 294.1 Potkonyak CUTTING AND output level on all channels at all sampling rates.
  • Page 433 2. Lift Pins 1 and 5 on four IC-s (SSM2143) U23, U24, U25 and U26 and connect a resistor between each AO2 CARD +15, 16 lifted pin and its pad. Use the following Resistor: 5k6, SMD 0805, Metal Film, 1% (Fairlight Part Number & 18 dBu INPUT RME9206).
  • Page 434 MOTHERBOAR Potkonyak by cutting it to 585 mm length and stripping each end. Crimp a Lug, Fairlight part # CONG8152 to one end of cable. 2. Similarly, prepare a black PVC insulated cable, of the same size, cut to 610 mm length.
  • Page 435 Compliled by Noel Plummer Page 11 of 42 ECNs for AMB8 Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details AMB8 08-Dec-94 Analog Mother Chris Alfred Fitment of extra brace to provide extra rigidity to Please see attached drawings identifying location and alignment of Brace to the Mother Board.
  • Page 436 2. Install an 1 x 8 SIL Header (Fairlight P/N CONG5272-8) at RN2. Metres. 3. Install 4 shorting plugs (Fairlight P/N COND6747) on header above at RN2 1-2, RN2 3-4, RN2 5-6, RN2 7-8. 4. Use WXCG3.DLD program to load CG4 Lattice devices.
  • Page 437 Note to Subcontractors: Modify all WIP of ESP-CG4 Cards ESP-CG4 27-May-99 Colour Graphics Mario Reversal of ECN 258 1. ADD three IC HCPL2630 at locations U24 U25 U26 (Fairlight Pn: SIGB1025) MFX 305 4 and Mixer Card Paolino To maintain compatability of the ESP-CG4 2.
  • Page 438 (90059-0009), Nextron (281-11-60 or 281-11-2X or 281-11-3X)" Avnet, Interconnections, Adilam, Amtron 2. Header 6 x 2, Fairlight P/N CONG5233-6 has been changed to CONG5624-6 which has been defined Connector Header 6 x 2 (stick header), Select Gold >= 10u", Max height above PCB = 8.7 mm, Total Pin length = 11.3 + 0.5, -1.1 mm...
  • Page 439 Murata P/N DD104-989CH390J50. (263) of this ECN. of the variable cap C13 can be substantially Replace L2 with Inductor 0.15uH, 2% , 1.27 A, 0.07 ohm, Q >= 45, SRF >= 420 MHz, Fairlight P/N reduced. TCA2430 (specially selected) The full turn adjustment range will then be from Replace C25 with a varactor Diode BB809, Fairlight P/N SDTD5040, cathode closest to U23 (same as about 1.2 to 3.0 Volts.
  • Page 440 Compliled by Noel Plummer Page 16 of 42 ECNs for DIO Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details ESP-DIO 28-Apr-94 Digital IO Card Chris Alfred DUART communications MFX 9 Connect U19/13 to U10/21 (68681FN) Connect U19/11 to U10/20 Cut solder side track to U26/12 (3486) Connect U26/12 to U26/8 *XIRQ to PA7...
  • Page 441 Fairlight logo on silkscreen. ESP-DIO-E & 08-Oct-98 DIO (EMC) Noel DIO detection failure with power cycled at 3 UNITS IN WIP: Replace 74LS14 chip (Fairlight part # SITA0014) with 74HC14 in location U33. MFX 253.1 ESP-DO-E CARD & DO Plummer...
  • Page 442 Compliled by Noel Plummer Page 18 of 42 ECNs for DIO Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details Insert the right hand pin (pin 1) of the DS1233 into the other hole of C22. Slide 9mm of insulation onto the left hand pin (pin 3) of the IC and insert it into the left hand HOLE of R29 (side closest C22).
  • Page 443 MFX 253.1 ESP-DIO-E & 08-Oct-98 DIO (EMC) Noel DIO detection failure with power cycled at 3 UNITS IN WIP: Replace 74LS14 chip (Fairlight part # SITA0014) with 74HC14 in location U33. ESP-DO-E CARD & DO Plummer seconds OFF interval UNITS IN FIELD: If the DIO detection problem is found, replace 74LS14 chip in location U33 on the DIO (EMC) CARD card with 74HC14 chip.
  • Page 444 Compliled by Noel Plummer Page 20 of 42 ECNs for DO Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details ESP-DIO-E & 30-Mar-99 DIO (EMC) Mario This ECN applies to To gain access to the trim pots on the AIO2 and 1.
  • Page 445 ESP-LTC & ESP- ESP-LTC-C 02-Dec-98 LTC and AES Noel The ESP-LTC PCB has been redesigned. The New Revision ESP-LTC Blank PCB - Rev 3 Fairlight P/N PWAEESPLTCR3 LTC-E I/O card Plummer new PCB is revision 3. It incorporates all mods The new PCB features the following enhancements: (including EMC) up to revision 2.3.
  • Page 446 Compliled by Noel Plummer Page 22 of 42 ECNs for MFK Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details MFX 152.2 ESP-MFK ESP-MFK 28-Oct-96 Console Leith Stewart This ECN to be 1. There is not enough space to install JP2 and Delete or remove connectors JP2 and JP3.
  • Page 447 Compliled by Noel Plummer Page 23 of 42 ECNs for MID Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details MFX 5 ESP-MIDI 28-Apr-94 SYNC IO Chris Alfred Additional synchronisation features. MCLKIN from AES reference. Connect U23/19 (CS8411) to JP5/45. VSYNC reference Support and Connect U5/3 (LM1881) to JP5/46 and U16/3 (74HC251).
  • Page 448 Compliled by Noel Plummer Page 24 of 42 ECNs for MID Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details Wire - ESP-MIDI: 21 - U23/11, 22 - U16/3, 23 - U16/14, 24 - U16/4, 25 - U17/12, 26 - U17/5, 27 - JP5/45, 28 - JP5/35, 29 - U18/40, 30 - U18/31, 31 - U18/8, 32 - U12/11, 33 - JP5/46, 34 - JP5/42, 35 - JP5/40, 36 - JP5/38.
  • Page 449 This problem is still under investigation by ARTI (the manufacturer of the TR1) and Fairlight. After this modification, the TR1 will start in test mode approximately once in 60 power-cycles.
  • Page 450 Compliled by Noel Plummer Page 26 of 42 ECNs for MID Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details MFX 129.2 PWBMESPMIDI PWBMESPMIDI- 14-Oct-96 MIDI Card. Leith Stewart Applicable to all To modify the current MIDI card to meet EMC The following changes are required as part of a system modification to make the MFX3 rack meet machines with a requirements.
  • Page 451 Compliled by Noel Plummer Page 27 of 42 ECNs for MID Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details MFX 249.1 ESP-MIDI & ESP-MIDI-C 4.8x 5.0x 20-Jul-98 Midi and Sync Noel The ESP-MIDI PCB has been redesigned. The New Revision ESP-MIDI Blank PCB - Rev 5 P/N PWAEESPMIDIR5 ESP-MIDI-E Control card...
  • Page 452 Details 1MFXCSLPSAN, 16-Oct-97 CONSOLE Noel A number of MFX+ consoles have recently been Replace the DIN connector with a locking type (Fairlight P/N COND6784, Preh P/N 71430-070, Farnell MFX 229 1MFXCSLPO2N, MFX+ S/A , O2R, Plummer shipped with a non-locking type DIN connector on P/N 437-220) as per attached drawing PSU2001.DW2 rev 1.7.
  • Page 453 MFX 248 Plummer changed for the following reasons. This file is included with documentation in the wxcgpc7.zip file available from the Fairlight BBS. Refer to To fix clicks in audio during record. wxcgpc7.doc for instructions. To allow use of Symbios 53C810 based cards.
  • Page 454 Compliled by Noel Plummer Page 30 of 42 ECNs for PLL Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details ESP-PLL 10-Oct-94 Phase Locked Chris Alfred Connect WCLKREF to external PLL connector Change U23 to 74LS244. MFX 33 Loop Card JP4.
  • Page 455 23-Feb-99 Phased Lock George This ECN replaces The 9 pin D connectors on this card have too 1. Change the Male D Connector at P1 and P2 to Fairlight P/N: COND6047/M Loop Card EMC Potkonyak ECN 279 (a much reach causing the support panel to bend.
  • Page 456 GSKTD3720. 1MFXCSLPSAN, 16-Oct-97 CONSOLE Noel A number of MFX+ consoles have recently been Replace the DIN connector with a locking type (Fairlight P/N COND6784, Preh P/N 71430-070, Farnell MFX 229 1MFXCSLPO2N, MFX+ S/A , O2R, Plummer shipped with a non-locking type DIN connector on P/N 437-220) as per attached drawing PSU2001.DW2 rev 1.7.
  • Page 457 Compliled by Noel Plummer Page 33 of 42 ECNs for RGB01 Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details CAB5068 11-Dec-96 Cable Assy 14R Leith Stewart There is not enough excess length to allow easy New specifications for the following cable have been released;...
  • Page 458 Relabel the PCB Rev. 2.3. ESP-RIO 18-Nov-98 REAR INPUT Noel The ESP-RIO PCB has been redesigned. The New Revision ESP-RIO Blank PCB - Rev 3 Fairlight P/N PWAEESPRIOR3 MFX 273.1 OUTPUT CARD Plummer new PCB is revision 3. It is functionally equivalent The new PCB features the following changes and enhancements: to assembly revision 2.3.
  • Page 459 Compliled by Noel Plummer Page 35 of 42 ECNs for SYN Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details ESP-SYN 29-Jun-94 Sync Card Chris Alfred Additional design features. TSBEN driven by tri-state buffer MFX 4 Change U11 to 74F125 Connect U11/1 to U11/12...
  • Page 460 Compliled by Noel Plummer Page 36 of 42 ECNs for SYN Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details MFX 22 ESP-SYN 20-Jul-94 Sync Card Chris Alfred Better damping of PCLK signal. Change RN21 to 10R 8 pin resistor pack Noise on WREF signal causing shared memory WREF noise...
  • Page 461 Compliled by Noel Plummer Page 37 of 42 ECNs for SYN Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details MFX 124.1 ASYMFX3SYNX ASYMFX3SYNX 20-Feb-96 SYNC I/O Leith Stewart Applicable to all To modify the current Sync module to meet EMC Modifications to the Sync I/O module are required for EMC compliance.
  • Page 462 Compliled by Noel Plummer Page 38 of 42 ECNs for SYN Card as at 11/6/99 Current ECN Number Assembly Assembly Date Description Name Special Note Reason Details ESP-SYN 09-Nov-95 Sync Card Erik de This is a Special Enable 10 Mb Ethernet Functions on Sync Card Place 16 pin DIL socket at U16.
  • Page 463 ESP-SYN 20-Jan-99 Sync Card Noel The ESP-SYN PCB has been redesigned. The New Revision ESP-SYN Blank PCB - Rev 4 Fairlight P/N PWAEESPSYNR4 MFX 276.1 Plummer new PCB is revision 4. It incorporates all mods up The new PCB features the following enhancements: to 3.3, therefore assembly revision 4.0 is...
  • Page 464 MFX 250 17-Jul-98 Turbo SCSI Noel The ESP-TSR PCB has been redesigned. The New Revision ESP-TSR Blank PCB - Rev 5 Fairlight P/N PWAEESPTSR5 Plummer new PCB is revision 5. Rev 5 PCB incorporates all mods up to 4.1 therefore assembly revision 5.0 is equivalent to assembly revision 4.1.
  • Page 465 Mario higher transfer rates, SCSI data transfer rate is approx 10MB/sec. 2. Replace X1, 20 MHz Crystal Osc Module (Fairlight part # CRYC9031), with a 40 MHz Crystal Osc Paolino the software installed Module, 14 Pin DIL, 4 Pin Package, CMOS Output, 5 ns Rise/Fall Output Time, Temperature stability +/- MUST BE 14.2.25 or...
  • Page 466 HCMOS Compatible module. Change specification for X3 with the following; Fairlight P/N CRYC9044 - CRYS OSC 66.000MHZ HCMOS, 50% DUTY CYCLE Change : 174.1 Assembly Revision number changed to 3.1, Crystal description enhanced. 174.2 Added rev 2.x cards.

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