NXP Semiconductors PN5190 Design Manual
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NXP Semiconductors PN5190 Design Manual

NXP Semiconductors PN5190 Design Manual

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AN12549
PN5190 antenna design guide
Rev. 1.1 — 23 April 2021
562211
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Information
Content
Keywords
PN5190, NFC antenna design, NFC antenna tuning
Abstract
This document describes the NFC antenna design and tuning related to
the PN5190. This includes the Dynamic Power Control 2.0 functionality. It
gives some layout recommendations as well some guidelines, how to adjust
("calibrate") the DPC.
Application note
COMPANY PUBLIC

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Summary of Contents for NXP Semiconductors PN5190

  • Page 1 PN5190, NFC antenna design, NFC antenna tuning Abstract This document describes the NFC antenna design and tuning related to the PN5190. This includes the Dynamic Power Control 2.0 functionality. It gives some layout recommendations as well some guidelines, how to adjust (“calibrate”) the DPC.

  • Page 2: Revision History

    AN12549 NXP Semiconductors PN5190 antenna design guide Revision history Revision history Date Description 1.1. 20210423 Section 3.4 "Layout recommendation for HVQFN" added 20210120 First official released version AN12549 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

  • Page 3: Introduction

    PN5190 antenna design guide Introduction The antenna design for the PN5190 is not much different than the antenna design for most of the other NXP reader ICs in general. However, some PN5190 specific details need to be considered to get an optimum performance.

  • Page 4: Nfc Reader Antenna Design

    AN12549 NXP Semiconductors PN5190 antenna design guide NFC reader antenna design For the NFC operation three different communication modes are specified in [4]: 1. In the card emulation mode (CM) the NFC device can be used in (existing) NFC reader infrastructure. In the CM the NFC device behaves in principle like a PICC, as defined in [2].
  • Page 5 AN12549 NXP Semiconductors PN5190 antenna design guide 1. k = coupling coefficient 2. Φ = magnetic flux Figure 1. Magnetic coupling between reader (PCD) and card (PICC) According to the ISO/IEC 14443 the PICC antenna coils can be categorized into the classes 1 …6, as shown in...
  • Page 6 AN12549 NXP Semiconductors PN5190 antenna design guide The ISO/IEC 14443 does not specify an operating volume. The reader manufacturer needs to guarantee that within the operating volume - that they themselves define - all related ISO/IEC 10373-6 tests can be passed.

  • Page 7: Field Strength

    AN12549 NXP Semiconductors PN5190 antenna design guide Note: This application note does not replace the detailed test description in the ISO/IEC 10373-6. There is no common certification process for ISO/IEC14443 compliance in place, even though many national bodies use the ISO/IEC 14443 to operate the electronic passports and electronic ID cards.

  • Page 8: Load Modulation

    Figure 6 shows a minimum required setup to test and optimize the load modulation performance of the PN5190 NFC Reader. The NFC Cockpit controls the PN5190 in the PNEV5190B (or in any customer design). The AWG (Keysight 33511B with arbitrary license) can easily be controlled by: 1.

  • Page 9: Emvco Specifics

    2. From a trigger output of an oscilloscope, which triggers itself by the sent waveshapes. Those waveshapes (RF trace) can be traced with a simple pickup coil. 3. From a PN5190 test signal, which indicates that the command has been sent (e.g. falling edge of TxActive).

  • Page 10: Emvco Analog Test With Version 3.0

    AN12549 NXP Semiconductors PN5190 antenna design guide 2.2.1 EMVCo analog test with version 3.0 With the introduction of the version 3.0 of EMVCo Contactless specification, the test effort has increased a lot. For the reader tests three calibrated EMVCo TestPICCs are required.

  • Page 11: Emvco Operating Volume

    The simulation results can be taken as reference to estimate the design effort especially for small antennas compared to “normal” antenna sizes. Note: The PN5190 allows a more flexible antenna design, since it drives more power into the antenna than other NFC Reader ICs, while at the same time the DPC 2.0 controls the power transfer as well as the TxShaping at closer distances.

  • Page 12: Emvco Wave Shapes

    AN12549 NXP Semiconductors PN5190 antenna design guide 1. Simulation of a square antenna 2. These simulation results do neither take any specific environment nor loading effects into account. Figure 9. EMVCo POS Reader Antenna size 2.2.4 EMVCo wave shapes The PCD needs to send the related pulse(s): It may send an EMVCo WUPA and / or WUPB (or standard REQA / REQB).

  • Page 13: Emvco Lma

    WvePlayer tool allows to provide both signal forms according to the EMVCo specification, but the AWG support of the NFC Cockpit does not. Technically the PN5190 does not make any difference between “negative” and “positive” load modulation, so basically it is good enough to test either one.

  • Page 14: Pn5190 Antenna Requirements

    PN5190 antenna design guide PN5190 antenna requirements The PN5190 uses the NXP NFC standard antenna circuit, as well known with other NFC NXP reader ICs. The PN5190 is optimized to support the NFC, ISO and EMVCo with a minimum of additional components.

  • Page 15: Q Factor

    The cut-off frequency defines the “symmetry” of the antenna. For “asymmetric” antenna tunings (like e.g. used for the CLRC663), the cut-off frequency is typically For the PN5190 a “symmetric” antenna design is recommended, which requires a lower cut-off frequency: AN12549 All information provided in this document is subject to legal disclaimers.

  • Page 16: Emc Filter Inductor

    L0. 3.2 Comparison to PN5180 antenna design In principle the antenna design for the PN5190 is the same as the one for the other NXP NFC reader ICs (like e.g. the PN5180). However, the PN5190 provides some new features, which need to be considered to get the best performance.

  • Page 17: Receiver Performance

    3. Place the capacitor of RX line close to PN5190. 4. Place the inductor L0 very close to PN5190 to have shorter TX line. For the routing, the following guide lines can be given: 1. Route TX line in Top Layer (due to huge current).
  • Page 18 AN12549 NXP Semiconductors PN5190 antenna design guide 1. Screenshot with multiple layers Figure 12. PN5190 Layout Reference example AN12549 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Application note Rev. 1.1 — 23 April 2021...

  • Page 19: Pn5190 Bga Power Supply Circuit Recommendation

    Especially for the DC/DC-Converter the layout needs to be carefully designed. The PN5190 is optimized to support the EMVCo operating volume with 3.3 V input supply. Therefore the TX output can drive up to ITVDD = 350 mA. Based on a power supply voltage VDDPA = TVDD = 5.7 V that means a possible total power consumption...
  • Page 20 AN12549 NXP Semiconductors PN5190 antenna design guide 3. Provide Cu shape. If shape is not possible, then route with wide trace (150mils) 4. No vias allowed 5. BOOST_LX is noisy source, so sensitive signals should be far away from this net Figure 14. Layout example for VBATPWR, VDDBOOST, and BOOST_LX...
  • Page 21 AN12549 NXP Semiconductors PN5190 antenna design guide Figure 16. Layout example for VDDNV, VDDC, and VDDPA VUP: • Place component as close as possible to VUP pad • Place low value capacitor close to the pin • Try to place the components on the same side of the chip •...
  • Page 22 AN12549 NXP Semiconductors PN5190 antenna design guide Figure 18. Layout example for VREF, VMID, and TXVCM Table 1. Power supply design considerations Keep the parasitic capacitance and inductance value lower or equal than this value. Net name Parasitic Parasitic inductance Max VCC...

  • Page 23: Pn5190 Bga Gnd Design Recommendation

    AN12549 NXP Semiconductors PN5190 antenna design guide 3.3.3 PN5190 BGA GND design recommendation VSSPWR: 1. Drop a separate via for VSS_PWR to GND and do not share with any other pin Figure 19. Layout example for the VSS_PWR VSS_SUB: • VSS SUB must be separated from VSS_PWR •...
  • Page 24 AN12549 NXP Semiconductors PN5190 antenna design guide VSS_NFC: • It should directly connect to GND plane • It should not share with any GND pin of the BGA Figure 21. Layout example for the VSS_PLL, VSS_DIG, and VSS_NFC Table 2. GND design considerations...

  • Page 25: Pn5190 Bga Clock Design Recommendation

    3.3.4 PN5190 BGA clock design recommendation Clock: • Place XTAL and the associated components as close as possible to the PN5190 • Keep traces as close as possible and keep the length equal • Keep load capacitance close to the crystal •...
  • Page 26 4. No Test point allowed. 5. No silk label on RF traces. 1. Screenshot with multiple layers Figure 23. PN5190 HVQFN layout reference example AN12549 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
  • Page 27 AN12549 NXP Semiconductors PN5190 antenna design guide 1. Screenshot with multiple layers Figure 24. PN5190 HVQFN Tx layout reference example AN12549 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Application note Rev.

  • Page 28: Pn5190 Hvqfn Power Supply Circuit Recommendation

    Especially for the DC/DC-Converter the layout needs to be carefully designed. The PN5190 is optimized to support the EMVCo operating volume with 3.3 V input supply. Therefore the Tx output can drive up to ITVDD = 350 mA. Based on a power supply voltage VDDPA = TVDD = 5.7 V that means a possible total power consumption...
  • Page 29 5. BOOST_LX is noisy source, so sensitive signals should be far away from this net. Figure 26. PN5190 HVQFN layout example for VBATPWR, VDDBOOST, and BOOST_LX Figure 27. PN5190 HVQFN layout example 2 for VBATWPR, VDDBOOST, and BOOST_LX VDDNV: • Place 0.22 µF capacitor as close as possible to VDDNV pad •...
  • Page 30 • Provide shape or thicker trace width (30 mil or more) • Try to avoid via 1. Screenshot with multiple layers Figure 28. PN5190 HVQFN layout example for VDDNV, VDDC, and VDDPA VUP: • Place component as close as possible to VUP pad •...

  • Page 31: Pn5190 Hvqfn Gnd Recommendations

    2. Route with wide trace 1. Screenshot with multiple layers Figure 30. PN5190 HVQFN layout example for VREF, VMID, and TXVCM Table 3. PN5190 HVQFN Power supply design considerations Keep the parasitic capacitance and inductance value lower or equal than this value.

  • Page 32: Pn5190 Hvqfn Clock Design Recommendations

    3.4.4 PN5190 HVQFN clock design recommendations Clock: • Place XTAL and the associated components as close as possible to the PN5190 • Keep traces as close as possible and keep the length equal • Keep load capacitance close to the crystal •...
  • Page 33 AN12549 NXP Semiconductors PN5190 antenna design guide 1. Screenshot with multiple layers Figure 32. PN5190 HVQFN layout example for the clock AN12549 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Application note Rev.

  • Page 34: Pn5190 Antenna Tuning

    NXP Semiconductors PN5190 antenna design guide PN5190 antenna tuning The following description focuses on the PCD antenna for the PN5190. 4.1 NFC antenna tool If no other starting point is available, the NXP NFC antenna design tool on the NFC...

  • Page 35: Antenna Tuning Calculation Excel Sheet

    AN12549 NXP Semiconductors PN5190 antenna design guide 4.2 Antenna tuning calculation excel sheet Alternatively the known excel sheet can be used, like for the PN5180 or any other NXP NFC reader ICs. The same example from Section 4.1 is shown in Figure 1.
  • Page 36 AN12549 NXP Semiconductors PN5190 antenna design guide 1. Measured with Rohde & Schwarz ZVL (see [7]) 2. L = 1.19 µH, R = 2.9 Ω Figure 35. Antenna coil measurement example 1 1. Measured with minVNA Pro and VNA/J (see and [10]) Figure 36. Antenna coil measurement example 2...

  • Page 37: Antenna Circuit Simulation

    AN12549 NXP Semiconductors PN5190 antenna design guide In this example, the antenna coil is measured with these values: L = 1.17 … 1.19 µH ≈ 2.9 … 3.3Ω Coil = not measured, can be estimated The inductance can be measured quite accurate, but the resistance is not very accurate due to the relationship between R and jωL.

  • Page 38: How To Interpret The Smith Chart

    AN12549 NXP Semiconductors PN5190 antenna design guide 1. This circuit uses ideal components! Figure 38. RFSIM99 smith chart plot This simulation can be used now to fine-tune the circuit with realistic components: 1. The values should fit into the given E-series. Example: Instead of C2 = 197.2 pF a value of C2 = 180 pF in parallel to 18 pF can be used.
  • Page 39 AN12549 NXP Semiconductors PN5190 antenna design guide That example indicates losses of 1 Ω per inductor (at the operating frequency, which is quite realistic). 1. The L0 inductor (real component) contains losses, which are manually added. Figure 39. Circuit derived from the Calculation including losses...

  • Page 40: Smith Chart: C0

    AN12549 NXP Semiconductors PN5190 antenna design guide Good L0 with R = 1.5 Ω Bad L0 with R = 5 Ω Figure 41. Measure the inductor loss 4.4.2 Smith chart: C0 The impact of the value of C0 (EMC filter capacitor) can also be read from the smith...

  • Page 41: Smith Chart: C1

    AN12549 NXP Semiconductors PN5190 antenna design guide C0 ok, Cut off frequency ok C0 too high, Cut off frequency too low Figure 43. Smith chart: C0 too high 4.4.3 Smith chart: C1 The effect of C1 can also be estimated from the smith chart, as shown in...

  • Page 42: Smith Chart: C2

    AN12549 NXP Semiconductors PN5190 antenna design guide 4.4.4 Smith chart: C2 The effect of C2 can also be estimated from the smith chart, as shown in Figure C2 too low, Impedance too inductive C2 too high, impedance too capacitive Figure 45. Smith chart: impact of C2 4.5 Correction of the simulated circuit...
  • Page 43 AN12549 NXP Semiconductors PN5190 antenna design guide Figure 46. Corrected simulation circuit 1. The simulated impedance is slightly higher than the target. Figure 47. Smith chart plot of the corrected tuning circuit AN12549 All information provided in this document is subject to legal disclaimers.

  • Page 44: Measure The Real Circuit

    AN12549 NXP Semiconductors PN5190 antenna design guide 4.6 Measure the real circuit With these values, the tuning can be assembled now. Assuming that all the values are correct and the same as simulated the measured impedance plot must be the same like the simulated one.

  • Page 45: Adapt The Simulation

    AN12549 NXP Semiconductors PN5190 antenna design guide 4.7 Adapt the simulation To simplify the exercise, the measurement pot is saved S1P-file, and then added into the simulation file, as shown in Figure 49. First Assembly, simulated and measured S11: Simulation plot S22: measured plot Figure 50. Comparison of simulation and measurement...
  • Page 46 AN12549 NXP Semiconductors PN5190 antenna design guide • It can also be shown that the estimated losses of the L0 inductors were too high. So in this case the resistance, which indicates the L0 losses, are reduced to R = 0.7 Ω.

  • Page 47: Correct The Simulation

    AN12549 NXP Semiconductors PN5190 antenna design guide 4.8 Correct the simulation After the unknown values have been adapted in such a way, that the simulation matches the reality, in a final step the tuning needs to be corrected in such way to get a symmetrical tuning to meet the target impedance.

  • Page 48: Finalize Tuning

    AN12549 NXP Semiconductors PN5190 antenna design guide 4.9 Finalize tuning The real measurement (already shown as S11-File in Figure 54) then shows the correct tuning, which is already finally tuned, as shown in Figure 1. No further fine-tuning is required.

  • Page 49: Rx Circuit

    The value must be: Crx = 1 nF Rrx = 560…1500 Ω More details tbd. Figure 56. PN5190 complete antenna circuit (including RX) AN12549 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

  • Page 50: Pn5190 And Dynamic Power Control (Dpc)

    Figure Below 20 mm the maximum power transfer is exceeded as well as the ITVDD limit of the PN5190. That might both destroy the PICC and the PCD, and at least violates the specifications. Note: The PN5190 has an overcurrent protection, which switches off the RF field in case of over temperature, as well as an over temperature protection, which resets the PN5190 in case of over temperature.

  • Page 51: First Step Of Dpc: Current Limiter

    (including a hysteresis), the VDDPA is reduced automatically. This does not only protect the PN5190, but also helps to keep the field strength limits (of ISO, NFC or EMVCO). For EMVCo POS design, the easiest way is to measure the ITVDD with the TestPICC (e.g.
  • Page 52 285 mA +/- 20 mA. This protects the PN5190 and the overall power supply circuit. Note: The default control range of the VDDPA is limited to 2.2 V … 5.7 V, using the RDON feature.

  • Page 53: Second Step Of Dpc: Current Reduction

    So in addition to the current limiter (“target current”), the PN5190 DPC offers a current reduction lookup table (DPC_LOOKUP_TABLE, see [1]), which allows a reduced current for each of the 43 VDDPA steps (if TXLDOVDDPALOW = 1.5 V).
  • Page 54 AN12549 NXP Semiconductors PN5190 antenna design guide As soon as the loading changes, and the ITVDD exceeds the 320 mA, the DPC needs to switch the power level. Load = 5.7 V / 320 mA = 17.8 Ω -> VDDPA(new) = 17.8 Ω ∙ 300 mA = 5.3 V VDDPA(target) = 17.8 Ω...

  • Page 55: Pn5190 Dpc Calibration

    Figure 61. EMVCo power transfer with manual current reduction (target) 5.4 PN5190 DPC calibration To operate the PN5190 with optimum performance, only a few settings must be defined. These settings can easily be adjusted with the NFC Cockpit. 5.4.1 Set target current...
  • Page 56 It is recommended to set the target current, but not to change the hysteresis value (other than for test purposes). The target current should be such, that the PN5190 does not reduce the VDDPA without major loading. For EMVCo: The TestPICC1 might be good to check the power transfer in 4 cm distance, which gives a reasonable amount of loading (depending on PCD antenna size).

  • Page 57: Set Current Reduction

    3. Read the current ITVDD. Note: Be aware that with disabled DPC there is no current limiter. The resulting current ITVDD depends on the loading condition, and might exceed the PN5190 limits, if not taken care by the user! AN12549 All information provided in this document is subject to legal disclaimers.

  • Page 58: Nfc Cockpit Current Reduction Calibration Fast Method

    AN12549 NXP Semiconductors PN5190 antenna design guide 5.4.2.1 NFC Cockpit current reduction calibration fast method The NFC Cockpit provides a simple support to calibrate the DPC. It calculates 7 LUT entries out of a measurement procedure. The user needs to enter the target condition (= target ITVVD) for 7 different VDDPA levels.
  • Page 59 AN12549 NXP Semiconductors PN5190 antenna design guide 1. All measurements done Figure 65. DPC Calibration with NFC Cockpit, measurements done Then the NFC cockpit switches to the second subtab, and 7 entries are indicated in the LUT as shown in Figure 66.
  • Page 60 AN12549 NXP Semiconductors PN5190 antenna design guide 1. The empty entries need to be filled manually (interpolation). Figure 66. DPC Calibration with NFC Cockpit, LUT start To fill the missing LUT entries, the in-between values can simply be interpolated, like shown in Figure As soon as all LUT entries are filled, they can be saved into EEPROM, using the <Save...

  • Page 61: Nfc Cockpit Current Reduction Calibration Accurate Method

    AN12549 NXP Semiconductors PN5190 antenna design guide 1. The complete LUT must be saved to EEPROM Figure 67. DPC Calibration with NFC Cockpit, all LUT entries filled 5.4.2.2 NFC Cockpit current reduction calibration accurate method The manual interpolation normally is accurate enough. However, the LUT can be filled manually with an accurate measurement for each of the given VDDPA values, if needed.
  • Page 62 AN12549 NXP Semiconductors PN5190 antenna design guide 1. 50 mm x 30 mm antenna Figure 68. Example of DPC Calibration, using DPC_LUT excel sheet In this example, the EMVCo TESTPICC (EMVCo 2.6) is used to load and define the DPC current values. The measurement starts with disabled DPC, VDDPA = 5.7 and the TestPICC placed in 70 mm above.
  • Page 63 AN12549 NXP Semiconductors PN5190 antenna design guide This measurement needs to be done for all VDDPA steps. For each step, the conditions are: 1. the power transfer is at its target, 2. the load is lower than the load in the previous (higher) VDDPA step.
  • Page 64 AN12549 NXP Semiconductors PN5190 antenna design guide Table 5. Current reduction LUT example ...continued In case of ambiguity, the higher current is taken. VDDPA / [V] ITVDD / [mA] Load / [Ω] LUT VDDPA Current reduction 15.88 15.48 14.88 14.29 13.61 12.87...
  • Page 65 AN12549 NXP Semiconductors PN5190 antenna design guide With these settings, the overall power transfer with all 3 TestPICCs of EMVCo 3.0 can be met. Note: The calibration for EMVCo can be done with either of the TestPICCs. Even the old EMVCo 2.6 TestPICC can be taken (as shown in this example).

  • Page 66: Pn5190 Rx

    PN5190 antenna design guide PN5190 RX The PN5190 receiver itself is completely different than the known RX of PN5180 or CLRC663. It uses DSP with matched filters, providing a higher sensitivity and better robustness. The build Contactless Test Station (CTS) can be used to optimize settings and performance, and for debugging.

  • Page 67: References

    [17] NFC Antenna Design Hub, NFC Antenna Design Hub [18] PN5180 Antenna design tools, PN5180 Antenna design tools [19] AN12551 PN5190 design-in recommendations, will be available on https:// www.nxp.com/docs/en/application-note/AN12551.pdf AN12549 All information provided in this document is subject to legal disclaimers.

  • Page 68: Legal Information

    Purchase of NXP ICs with NFC technology products using NXP Semiconductors products, and NXP Semiconductors Purchase of an NXP Semiconductors IC that complies with one of the accepts no liability for any assistance with applications or customer product Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/ design.
  • Page 69 NXP Semiconductors PN5190 antenna design guide Tables Tab. 1. Power supply design considerations ....22 Tab. 4. PN5190 HVQFN VSS routing ......32 Tab. 2. GND design considerations ......24 Tab. 5. Current reduction LUT example ...... 63 Tab. 3.
  • Page 70 NFC operating volume ........13 Fig. 48. Smith chart plot of the corrected circuit ... 44 Fig. 11. TX part of the PN5190 antenna circuit .... 14 Fig. 49. First Assembly, simulated and measured ..45 Fig. 12. PN5190 Layout Reference example ....18 Fig.

  • Page 71: Table Of Contents

    Finalize tuning ..........48 NFC reader antenna design ....... 4 4.10 RX Circuit ............49 ISO/IEC 14443 specifics ........4 PN5190 and Dynamic Power Control (DPC) ..50 2.1.1 Field strength .............7 Bad example with no DPC ......50 2.1.2 Wave shapes ............. 7 First step of DPC: Current limiter .....51...

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