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IWR6843, IWR6443 Single-Chip 60 to 64GHz mmWave Sensor

1 Features

FMCW transceiver
– Integrated PLL, transmitter, receiver, Baseband,
and ADC
– 60 to 64GHz coverage with 4GHz continuous
bandwidth
– Four receive channels
– Three transmit channels
– Supports 6-bit phase shifter for TX Beam
forming
– Ultra-accurate chirp engine based on fractional-
N PLL
– TX power: 12dBm
– RX noise figure:
12dB
– Phase noise at 1MHz:
–93dBc/Hz
Built-in calibration and self-test
– Arm
®
Cortex
®
-R4F-based radio control system
– Built-in firmware (ROM)
– Self-calibrating system across process and
temperature
– Embedded self-monitoring with no host
processor involvement on Functional Safety-
Compliant devices
C674x DSP for advanced signal processing
(IWR6843 only)
Hardware accelerator for FFT, filtering, and CFAR
processing
Memory compression
Arm-R4F microcontroller for object detection, and
interface control
– Supports autonomous mode (loading user
application from QSPI flash memory)
Internal memory with ECC
– IWR6843: 1.75MB, divided into MSS program
RAM (512KB), MSS data RAM (192KB), DSP
L1 RAM (64KB) and L2 RAM (256KB), and L3
radar data cube RAM (768KB)
– IWR6443: 1.4MB, divided into MSS program
RAM (512KB), MSS data RAM (192KB), and
L3 radar data cube RAM (768KB)
– Technical reference manual includes allowed
size modifications
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SWRS219F – OCTOBER 2018 – REVISED APRIL 2025
Other interfaces available to user application
– Up to 6 ADC channels (low sample rate
monitoring)
– Up to 2 SPI ports
– Up to 2 UARTs
– 1 CAN-FD interface
– I2C
– GPIOs
– 2 lane LVDS interface for raw ADC data and
debug instrumentation
Functional Safety-Compliant
– Developed for functional safety applications
– Documentation available to aid IEC 61508
functional safety system design up to SIL 3
– Hardware integrity up to SIL-2
– Safety-related certification
IEC 61508 certified upto SIL 2 by TUV SUD
Non-Functional safety variants also available
Power management
– Built-in LDO network for enhanced PSRR
– I/Os support dual voltage 3.3V/1.8V
Clock source
– 40.0MHz crystal with internal oscillator
– Supports external oscillator at 40MHz
– Supports externally driven clock (square/sine)
at 40MHz
Easy hardware design
– 0.65mm pitch, 161-pin 10.4mm × 10.4mm flip
chip BGA package for easy assembly and low-
cost PCB design
– Small solution size
Operating conditions
– Junction temp range: –40°C to 105°C
IWR6843, IWR6443

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Summary of Contents for Texas Instruments IWR6843

  • Page 1: Features

    IWR6843, IWR6443 SWRS219F – OCTOBER 2018 – REVISED APRIL 2025 IWR6843, IWR6443 Single-Chip 60 to 64GHz mmWave Sensor • Other interfaces available to user application 1 Features – Up to 6 ADC channels (low sample rate • FMCW transceiver monitoring) –...
  • Page 2: Applications

    ABL (FCBGA, 161) 10.4mm × 10.4mm Tape and Reel For more information, see Section 13, Mechanical, Packaging, and Orderable Information. For more information, see Section 11.1, Device Nomenclature. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 3: Functional Block Diagram

    Data Osc. & ROM Temp Radar Data Memory Radio Processor 768 kB DSP Sub-System Sub-System RF/Analog Sub-System (Customer Programmed) (TI Programmed) Figure 4-1. Functional Block Diagram Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 4: Table Of Contents

    7.11 Thermal Resistance Characteristics for FCBGA 13.1 Packaging Information..........Package [ABL0161].............34 13.2 Tray Information for ABL, 10.4 × 10.4 mm .....82 7.12 Timing and Switching Characteristics..... Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 5: Device Comparison

    SWRS219F – OCTOBER 2018 – REVISED APRIL 2025 5 Device Comparison Unless otherwise noted, the device-specific information, in this document, relates to both the IWR6843 and IWR6443 devices. The device differences are highlighted in Table 5-1, Device Features Comparison.
  • Page 6 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT PA pin. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty.
  • Page 7: Related Products

    Review products that are frequently purchased or used in conjunction with this product. products for IWR6843 Reference The IWR6843 TI Designs Reference Design Library is a robust reference design library designs for spanning analog, embedded processor and connectivity. Created by TI experts to help IWR6843 you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
  • Page 8: Terminal Configuration And Functions

    QSPI_CS_N QSPI[3] VNWA VDDIN _CLKOUT _INTR GPIO_31 VSSA GPADC4 NRESET GPIO_33 VDDIN GPIO_35 GPIO_37 VIOIN_18 VIOIN QSPI_CLK QSPI[0] QSPI[2] Not to scale Figure 6-1. Pin Diagram Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 9 VSSA VSSA VSSA VSSA VSSA VSSA VSSA _13RF2 _13RF2 VSSA VSSA VSSA VSSA VIN_18BB VSSA VSSA VSSA _13RF1 Not to scale Figure 6-2. Top Left Quadrant Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 10 _14SYNTH GPADC5 VSSA VSSA CLKM VIOIN SPIA_MOSI GPADC6 _18DIFF SPIA_CS_N SPIA_CLK SPIA_MISO SPIB_MOSI SPIB_CLK VIOIN SYNC_OUT SPIB_MISO VIN_SRAM Not to scale Figure 6-3. Top Right Quadrant Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 11 _CLKOUT _OUT GPADC1 GPADC2 GPADC3 SYNC_IN GPIO_32 GPIO_34 GPIO_36 GPIO_38 VSSA GPADC4 NRESET GPIO_31 GPIO_33 VDDIN GPIO_35 GPIO_37 Not to scale Figure 6-4. Bottom Left Quadrant Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 12 GPIO_47 VDDIN QSPI[1] DMM_SYNC _RESET PMIC SPI_HOST_ QSPI_CS_N QSPI[3] VNWA VDDIN _CLKOUT INTR_1 VIOIN_18 VIOIN QSPI_clk QSPI[0] QSPI[2] Not to scale Figure 6-5. Bottom Right Quadrant Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 13: Signal Descriptions

    PWM Module 3 - Sync Output GPIO_0 General-purpose I/O GPIO_1 General-purpose I/O GPIO_2 General-purpose I/O GPIO_3 General-purpose I/O GPIO_4 General-purpose I/O GPIO_5 General-purpose I/O GPIO_6 General-purpose I/O Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 14 Programmable clock given out to external MCU or the processor MSS_UARTA_RX Main Subsystem - UART A Receive F14, N4, R11 MSS_UARTA_TX Main Subsystem - UART A Transmit H14, N13, N5, R4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 15 Open drain fail safe output signal. Connected to PMIC/ NERROR_OUT Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. PMIC_CLKOUT Output Clock from IWR6843 device for PMIC H13, K13, P9 QSPI[0] QSPI Data Line #0 (Used with Serial Data Flash) QSPI[1]...
  • Page 16 Power 1.8V supply for CMOS IO VIN_18CLK Power 1.8V supply for clock module VIOIN_18DIFF Power 1.8V supply for LVDS port Power Voltage supply for fuse chain Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 17 Analog IO dedicated for ADC service out on production hardware for field ANAMUX / GPADC5 Analog IO dedicated for ADC service debug VSENSE / GPADC6 Analog IO dedicated for ADC service Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 18: Pin Attributes

    0xFFFFEA80 Output Disabled Pull Down GPIO_32 DMM1 GPIO_33 TRACE_DATA_2 0xFFFFEA84 Output Disabled Pull Down GPIO_33 DMM2 GPIO_34 TRACE_DATA_3 0xFFFFEA88 Output Disabled Pull Down GPIO_34 DMM3 EPWM3SYNCO Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 19 NERROR_IN 0xFFFFEA44 Input NERROR_OUT NERROR_OUT 0xFFFFEA4C Hi-Z (Open Drain) PMIC_CLKOUT SOP[2] 0xFFFFEA68 During Power Up Output Disabled Pull Down GPIO_27 PMIC_CLKOUT CHIRP_START CHIRP_END FRAME_START EPWM1B EPWM2A Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 20 DSS_UART_TX QSPI_CS_N GPIO_6 0xFFFFEA40 Output Disabled Pull Up QSPI_CS_N SPIB_CS_N RS232_RX GPIO_15 0xFFFFEA74 Input Enabled Pull Up RS232_RX MSS_UARTA_RX BSS_UART_TX MSS_UARTB_RX CAN_FD_RX I2C_SCL EPWM2A EPWM2B EPWM3A Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 21 DSS_UART_TX SPIB_CLK GPIO_5 0xFFFFEA24 Output Disabled Pull Up SPIB_CLK MSS_UARTA_RX MSS_UARTB_TX BSS_UART_TX CAN_FD_RX SPIB_CS_N GPIO_4 0xFFFFEA28 Output Disabled Pull Up SPIB_CS_N MSS_UARTA_TX MSS_UARTB_TX BSS_UART_TX QSPI_CLK_EXT CAN_FD_TX Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 22 0xFFFFEA58 Input Enabled Pull Up MSS_UARTA_RX SOP[0] 0xFFFFEA5C During Power Up Output Enabled GPIO_24 MSS_UARTA_TX MSS_UARTB_TX BSS_UART_TX NDMM_EN GPIO_18 0xFFFFEA54 Input Enabled Pull Down BSS_UART_TX CAN_FD_RX Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 23 Pull Up: Internal pullup • Pull Down: Internal pulldown • An empty box means No pull. 9. Pin Mux Control Value maps to lower 4 bits of register. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 24 QSPI_CS_N 0xFFFFEA40 NERROR_IN 0xFFFFEA44 WARM_RESET 0xFFFFEA48 NERROR_OUT 0xFFFFEA4C 0xFFFFEA50 0xFFFFEA54 0xFFFFEA58 0xFFFFEA5C MCU_CLKOUT 0xFFFFEA60 GPIO_2 0xFFFFEA64 PMIC_CLKOUT 0xFFFFEA68 SYNC_IN 0xFFFFEA6C SYNC_OUT 0xFFFFEA70 RS232_RX 0xFFFFEA74 RS232_TX 0xFFFFEA78 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 25 (A '1' here overrides any i/p value on this IO with a desired value) FUNC_SEL Function select for Pin Multiplexing (Refer to the Pin Mux Sheet) Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 26: Specifications

    JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process Corner pins are rated as ±750 V Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 27: Power-On Hours (Poh)

    = 6 mA) VIOIN – 450 Low-level output threshold (I = 6 mA) (1.8V Mode) 0.45 (1.8V Mode) 0.96 NRESET SOP[2:0] (3.3V Mode) 0.65 (3.3V Mode) 1.57 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 28: Vpp Specifications For One-Time Programmable (Otp) Efuses

    TI device inoperable and TI will be unable to confirm the TI device conformed to TI device specifications prior to the attempted eFuse. CONSEQUENTLY, in these cases of faulty EFUSE programmability, TI WILL HAVE NO LIABILITY. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 29: Power Supply Specifications

    SWRS219F – OCTOBER 2018 – REVISED APRIL 2025 7.6 Power Supply Specifications Table 7-1 describes the four rails from an external power supply block of the IWR6843 device. Table 7-1. Power Supply Rails Characteristics SUPPLY DEVICE BLOCKS POWERED FROM THE SUPPLY...
  • Page 30: Power Consumption Summary

    2. APLL Power Down state The allowed state transitions are shown in Figure 7-1. This flow chart shows the sequence of steps for entering and exiting power save mode. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 31 APLL APLL Power APLL Power Down APLL Power Down ANALOG – OFF APLL – OFF DIGITAL – 40MHz Figure 7-1. Power Save Mode State Transition Diagram Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 32: Rf Specification

    P1dB parameters with respect to receiver gain programmed. NF (dB) In-band P1DB (dBm) RX Gain (dB) Figure 7-2. Noise Figure, In-band P1dB vs Receiver Gain Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 33: Cpu Specifications

    Family) L2 Memory Clock Speed Main Subsystem Tightly Coupled Memory - A (Program) (R4F Family) Tightly Coupled Memory - B (Data) Shared Shared L3 Memory Memory Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 34: Thermal Resistance Characteristics For Fcbga Package [Abl0161]

    N/A = not applicable 7.12 Timing and Switching Characteristics 7.12.1 Power Supply Sequencing and Reset Timing The IWR6843 device expects all external voltage rails to be stable before reset is deasserted. Figure 7-3 describes the device wake-up sequence. Submit Document Feedback Copyright ©...
  • Page 35 8 ms (XTAL Mode) OUTPUT 850 µs (REFCLK Mode) MCU_CLK_OUT in autonomous mode, where IWR6843 application is booted from the serial flash, MCU_CLK_OUT is not enabled by default by the device bootloader. Figure 7-3. Device Wake-up Sequence Copyright © 2025 Texas Instruments Incorporated...
  • Page 36 7.12.2.1 Clock Specifications The IWR6843 requires external clock source (that is, a 40-MHz crystal or external oscillator to CLKP) for initial boot and as a reference for an internal APLL hosted in the device. An external crystal is connected to the device pins.
  • Page 37: Specification

    Phase Noise at 100 kHz –152 dBc/Hz Phase Noise referred to 40 MHz Phase Noise at 1 MHz –153 dBc/Hz Duty Cycle Freq Tolerance –50 Freq Tolerance –50 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 38 – v(SPCL- c(SPC)M polarity = 0) 10.5 SIMO)M Valid time, SPISIMO data valid after SPICLK high, (clock 0.5t – v(SPCH- c(SPC)M polarity = 1) 10.5 SIMO)M Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 39 The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Figure 7-5. SPI Controller Mode External Timing (CLOCK PHASE = 0) Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 40 1) *t c(VCLK) c(VCLK) T2CDELAY Hold time, SPICLK high until CS inactive (clock polarity = 1) (T2CDELAY + (T2CDELAY + 1) *t – 1) *t c(VCLK) c(VCLK) Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 41 The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 42 SWRS219F – OCTOBER 2018 – REVISED APRIL 2025 Figure 7-7. SPI Controller Mode External Timing (CLOCK PHASE = 1) Figure 7-8. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1) Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 43 PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t = 2t ≥ 25 ns. c(SPC)S c(MSS_VCLK) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 44 (clock polarity = 1) SPISOMI SPISOMI Data Is Valid SPISIMO Data SPISIMO Must Be Valid Figure 7-10. SPI peripheral Mode External Timing (CLOCK PHASE = 1) Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 45 SPI communication timing of the typical interface protocol. 2 SPI clocks 0x1234 0x4321 0x5678 0x8765 MOSI 0xDCBA 0xABCD 16 bytes MISO Figure 7-11. SPI Communication Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 46 SWRS219F – OCTOBER 2018 – REVISED APRIL 2025 7.12.4 LVDS Interface Configuration The supported IWR6843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging.
  • Page 47: General-Purpose Input/Output

    Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate). The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback...
  • Page 48: Serial Communication Interface (Sci)

    Capability to use Direct Memory Access (DMA) for transmit and receive data • Two external pins: RS232_RX and RS232_TX 7.12.7.1 SCI Timing Requirements UNIT f(baud) Supported baud rate at 20 pF 921.6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 49 C-bus compatibility mode • The combined format in 10-bit address mode (the I2C sends the target address second byte every time it sends the target address first byte) Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 50 LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t su(SDA-SCLH) Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 51 SPI devices that launch data on the falling edge in Clock Mode 0. P = SCLK period in ns. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 52 All required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual. P = SCLK period in ns. M = QSPI_SPI_DC_REG.DDx + 1, N = 2 Figure 7-15. QSPI Read (Clock Mode 0) Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 53: Write Data

    POL=0 sclk Command Command Write Data Write Data Bit n-1 Bit n-2 Bit 1 Bit 0 d[0] d[3:1] SPRS85v_TIMING_OSPI1_04 Figure 7-16. QSPI Write (Clock Mode 0) Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 54 Delay time, ETM trace clock low to ETM data valid d(ETMTRACE CLKl- ETMDATAV) l(ETM) h(ETM) r(ETM) f(ETM) cyc(ETM) Figure 7-17. ETMTRACECLKOUT Timing Figure 7-18. ETMDATA Timing Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 55 DMM clk falling edge to DATA hold time dh(DMM) l(DMM) h(DMM) cyc(DMM) Figure 7-19. DMMCLK Timing ssu(DMM) sh(DMM) DMMSYNC DMMCLK DMMDATA dsu(DMM) dh(DMM) Figure 7-20. DMMDATA Timing Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 56: Jtag Interface

    7.12.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG PARAMETER UNIT Delay time, TCK low to TDO valid d(TCKL-TDOV) TDI/TMS SPRS91v_JTAG_01 Figure 7-21. JTAG Timing Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 57: Detailed Description

    • Gesturing In terms of scalability, the IWR6843 device could be paired with a low-end external MCU, to address more complex applications that might require additional memory for a larger application software footprint and faster interfaces. The IWR6843 has an embedded DSP for signal processing, processing the radar signals for FFT, magnitude, detection, and other applications.
  • Page 58: Subsystems

    In this mode, the 1-V supply needs to be fed on the VIN_13RF1, VIN_13RF2, and VOUT PA pin; whereas, the four receive channels can all be operated simultaneously. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 59 8.3.1.1 Clock Subsystem The IWR6843 clock subsystem generates 60 to 64 GHz from an input reference of 40-MHz crystal. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an X3 multiplier to create the required frequency in the 60 to 64 GHz spectrum.
  • Page 60 Figure 8-3. Transmit Subsystem (Per Channel) 8.3.1.3 Receive Subsystem The IWR6843 receive subsystem consists of four parallel channels. A single receive channel consists of an LNA, mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the same time an individual power-down option is also available for system optimization.
  • Page 61: Processor Subsystem

    The C674x DSP and L1/L2 RAM portion of the DSP subsystem is not supported on the IWR6443 device and therefore, the available memory is 1.4MB compared to 1.75MB on the IWR6843 device. For more information on the features supported and not supported on each device, see the Device Features Comparison table.
  • Page 62: Other Subsystems

    The host interface can be provided through a SPI, UART, or CAN-FD interface. In some cases the serial interface for industrial applications is transcoded to a different serial standard. The IWR6843 device communicates with the host radar processor over the following main interfaces: •...
  • Page 63: Boot Modes

    Table 8-1 enumerates the relevant SOP combinations and how these map to bootloader operation. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 64 (or device firmware patch – Supplied by TI) to the serial flash Debug Mode Bootloader is bypassed and R4F processor is halted. This allows user to connect emulator at a known point Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 65: Flashing Mode

    Serial FLASH User Application And device firmware Flashing UART FLASHING Program Integrated MCU Radar UTILITY ARM Cortex-R4F Section Data Figure 8-7. Figure 5. Bootloader Flashing Mode Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 66 If a valid image (or the QSPI Serial Flash is not found), the bootloader initializes the SPI port and awaits for the image transfer. This operation comes handy for configurations where the IWR6843 is interfaced to an external processor which has its own nonvolatile storage hence can store the user application and the IWR6843 device’s firmware image.
  • Page 67: Monitoring And Diagnostics

    The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot process. Once the application code takes up the control, Watchdog can be configured again for mode and timings based on specific customer requirements. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 68 R4F TCMs. R4F TCM Memories PBIST is triggered by MSS R4F Bootloader at the boot time and it does not proceed further if the fault is detected. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 69 PAs, DSP etc) which is monitored during the inter-frame period. Tx Power Monitors Device architecture supports power detectors at the Tx output. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 70 Refer to the Device Safety Manual or other relevant collaterals for more details on applicability of all diagnostics mechanisms. For Certification details, refer to the Device product folder. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 71 SWRS219F – OCTOBER 2018 – REVISED APRIL 2025 9.1.1 Error Signaling Module When a diagnostic detects a fault, the error must be indicated. IWR6843 architecture provides aggregation of fault indication from internal diagnostic mechanisms using a peripheral logic known as the error signaling module (ESM).
  • Page 72: Applications, Implementation, And Layout

    Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB. • Altium XWR6843 EVM Design Files • XWR6843 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 73: Device And Documentation Support

    IWR6843 device. For orderable part numbers of IWR6843 devices in the ABL0161 package types, see the Package Option Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.
  • Page 74: Tools And Software

    Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 75: Trademarks

    All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 76: Revision History

    • (QSPI Switching Characteristics): Updated cycle time, sclk to 12.5ns.............52 • (Boot Modes): Added Boot Modes section....................... • (Monitoring and Diagnostic Mechanisms):Added Device Safety Manual note..........Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 77 Global: Updated/Changed A2D to ADC......................• (Features) : Updated Functional-Safety Compliance Certification Collateral............. • (Device Information) : Added additional Secure production parts for IWR6843..........• Updated/Changed Functional Block Diagram ....................• (Device Comparison):Updated/Changed SIL row to reflect Functional Safety-Compliance for IWR6843..
  • Page 78: Mechanical, Packaging, And Orderable Information

    This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 79: Package Outline

    1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 80 NOT TO SCALE 4223365/A 10/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated...
  • Page 81 BASED ON 0.125 mm THICK STENCIL SCALE:10X 4223365/A 10/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: IWR6843 IWR6443...
  • Page 82: Tray Information For Abl, 10.4 × 10.4 Mm

    7.62 13.40 16.80 17.20 IWR6843ABGABL FC/CSP 8 × 22 315.0 135.9 7.62 13.40 16.80 17.20 IWR6843ABSABL FC/CSP 8 × 22 315.0 135.9 7.62 13.40 16.80 17.20 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: IWR6843 IWR6443...
  • Page 83 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated...

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