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HopeRF CMT2187A User Manual

210-960 mhz ook/(g)fsk transmitter soc
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210-960 MHz OOK/(G)FSK Transmitter SoC
Sub-1G Transmitting Micro-controller
1. This document describes the functions, operations, and usage of the CMT2187A. It is guidance for
engineers who uses the CMT2187A.
2. This manual is limited by the length of the document, and the referred registers of the chip function
modules are only listed. Please refer to the CMT2187A Register Detailed Manual for detailed register
description. Users can understand the chip functions more efficiently by referring to this document.
Copyright © By HOPERF
CMT2187A
User guide
Page
Rev 0.2 | 1/96
AN261-CMT2187A User Guide
CMT2187A
www.hoperf.com

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  • Page 1 Sub-1G Transmitting Micro-controller User guide 1. This document describes the functions, operations, and usage of the CMT2187A. It is guidance for engineers who uses the CMT2187A. 2. This manual is limited by the length of the document, and the referred registers of the chip function modules are only listed.

  • Page 2: Working Condition

    AN261-CMT2187A User Guide MCU Feature Sub-1G Transmitting Module Attributes  CPU kernal  Working frequency: 210 - 960MHz High performance single instruction period 1T-8051 kernal  Modulated Mode: OOK / ASK Supports up to 26MHz (XOSC) or 24Mhz (HFOSC) ...

  • Page 3: Product Information

    It also supports single-wire input hardware clock recovery module, which is convinient for the kernel to collect the external data synchronously (such as RX receiving data). Combined with CMOSTEK's NextGenRFTM series receivers, CMT2187A can be applied in a wide range of ultra-low power wireless network.

  • Page 4: Table Of Contents

    AN261-CMT2187A User Guide Categories SYSTEM ARCHITECT ............................... 7 SYSTEM OPERATING PROCESS AND WORKING MODE ................... 8 ............................8 YSTEM PERATING ROCESS ............................9 YSTEM PERATING .............................. 11 ROTECT ECHANISM DEBUGGING AND BURNING INTERFACES ......................11 1-WIRE O ....................12 NLINE...
  • Page 5 AN261-CMT2187A User Guide GPIO D ............................. 36 IGITAL UTPUT GPIO A ..........................36 NALOG NPUT AND UTPUT GPIO D ..........................36 IGITAL NPUT APPING GPIO D ..........................38 IGITAL UTPUT APPING GPIO L ..........................44 EVEL LIPPING ETECTION ..............................46...
  • Page 6 AN261-CMT2187A User Guide WATCHDOG (WDT) MODULE ..........................79 15.1 ..............................79 ASIC UNCTION 15.2 ..............................79 ELATED EGISTER SLEEP TIMERMODULE ............................80 16.1 ..............................80 ASIC UNCTION 16.2 LPOSC C ..............................80 ALIBRATION 16.3 ..............................80 ELATED EGISTER COMPARATOR ........................错误!未定义书签。...

  • Page 7: System Architect

    1 System Architect Embedded with a sub-1 GHz OOK / (G)FSK transmitter， CMT2187A is a high-performance 8051 wireless MCU. The user program is burned in the 4K Bytes MTP, which can be operated at clock frequency up to 26MHz. The chip integrates the below major modules: ...

  • Page 8: System Operating Process And Working Mode

    AN261-CMT2187A User Guide 2 System Operating Process and Working Mode 2.1 System Operating Process The system operation process of CMT2187A is shown as follows: POR power on reset RSTn pin reset Initial power on BOR voltage detection reset Watchdog reset The burner burns MTP burning mode？...

  • Page 9: System Operating Mode

    AON_SFR_03 register comparator work timed out  GPIO state remain unchanged Comparing from the power consumption in all four modes, Normal > IDLE > STOP. CMT2187A has two power www.hoperf.com Copyright © By HOPERF Page Rev 0.2 | 9/96...
  • Page 10 The Retention mode allows the chip to recover from its previous state immediately after a STOP wake-up and continue working without having to restart the program. In Retention mode, all RAM data is stored; MTP and EEPROM data can be stored without power. Table 2-2. CMT2187A Stores Contents in STOP Mode Power Storage...

  • Page 11: Protect Mechanism

    AN261-CMT2187A User Guide Power Configuration Number Module name Save State Work status Supply saved Mode √ √ UART × ULPLDO √ √ Port 0 × ULPLDO √ √ Port 1 × ULPLDO √ × × ULPLDO √ Timer A ×...

  • Page 12: 1-Wire Online Debugging And Burning Interfaces

    MTP burning. The following shows figure of tool connection and interface connection between the debugger and CMT2187A. It should be noted that the 1-Wire debugging interface needs to occupy pin D10, and it is recommended that the user leave this pin empty during the debugging phase. MTP burning is implemented through the three-wire S3S interface.

  • Page 13: S3S Bus Burning Interface

    4 T8051XC3 Micro Controller 4.1 Processor Architecture CMT2187A adopts T8051XC3 as the core controller of the system, including an enhanced 1T-8051 kernal, single period operating instruction, which is compatible to the MCS-51 command serial. The structure is shown as Chart 4-1.

  • Page 14: Instruction Sets

    Comparing to the CPU kernal, the GPIO belongs to peripheral and Port0 and Port1 can be mapping to GPIOs. T8051XC3 adopts an 8-bit SFR bus to connect the above mention peripherals. CMT2187A supports more peripherals, which are connected to the kernel via the SFR bus. In addition, the kernel uses a separate IDATA bus to connect to internal storage IRAM, and a shared CODE/XDATA bus to connect to MTP and XRAM respectively.

  • Page 15: 8051 Cores Initial Register

    4.3 8051 Core Initial Register The core 8051 initial associated register group is shown in the following table. For the specific content and meaning of each register, please refer to the CMT2187A Register Detailed Manual. Table 4-1. Initial Registers of 8051 Core...

  • Page 16: Memory Structure

    0x0000 0x0000 0x00 0x0000 Chart 5-1. CMT2187A Storage and Logical Address CMT2187A storage area consists of 3 spaces.  Program Code Space The space where 8051 kernel code is stored and loaded to run, the carrier is 4K Bytes MTP that can be erased multiple times.

  • Page 17: Special Feature Registers（Sfr

    5.2 Special Feature Registers（SFR） 8051 kernel can access SFR directly for it is the internal memory space. CMT2187A serial products are rich in features and related configured SFR, so we do access distribution by page, that is Page 0 and 1. Page 0 contains most of the peripheral configuration and control, and Page 1 contains registers of the EEPROM and the PA power configuration.

  • Page 18: Always-On Domain Register (Aon Reg)

    AN261-CMT2187A User Guide directly access the corresponding SFR, otherwise it is easy to cause configuration errors. The SFR is powered by the ULPLDO in STOP mode, ensuring that most configurations of the peripherals can be saved in low leakage. 5.3 Always-on Domain Register (AON REG) The always on (AON) domain system is powered directly by DVDD and it contains the watchdog, sleep timer, I/O change detection, and 32-byte register AON REG.

  • Page 19: Reset Structure

    7 Clock Structure 7.1 Clock Source The CMT2187A has three master clock sources, namely the 26 MHz high speed crystal oscillator XOSC, the 24 MHz internal high speed RC oscillator HFOSC, and 32 kHz internal low speed RC oscillator LFOSC. A refined clock gating mechanism is embeded inside the chip so that users can save as much power as possible.
  • Page 20 AN261-CMT2187A User Guide Analog Digital Core debug_clk cpu_clk ana_clk 13 MHz tx_clk ee_clk ioint_clk port0_clk div_bypass Sub-1G TX port1_clk PLL Reference mcu_clk timer0_clk timer1_clk uart_clk spim_clk spis_clk timera_clk timerb_clk cdr_clk 26 MHz XOSC hfosc_xo_sel lbd_clk sys_clk lfcal_clk hfosc_div2_en hfcal_clk lfosc_clk...

  • Page 21: Clock Calibration

    AN261-CMT2187A User Guide 7.2 Clock Calibration When the chip is shipped, HFOSC and LFOSC will be calibrated and the results will be burned to the MTP. The hardware correction module can also be invoked by manipulating the SFR register to correct the two clocks while using.
  • Page 22 AN261-CMT2187A User Guide corresponding SFR register. Clock gating is turned on by default. It is recommended that the user turn off the gated clock of the module that does not need to work immediately at the beginning of the program after configuring all SFR, and turn on the clock only when the module needs to be configured, controlled, and used.
  • Page 23 AN261-CMT2187A User Guide SFR Name Clock Gate Module Address Control Page 0x33 EE_MANU 0x92 INTCTL_0 0x93 INTCTL_1 0x94 INTCTL_2 0x95 INTCTL_3 0xA1 GPIO_INA_SEL 0xA2 GPIO_INB_SEL 0xA3 GPIO_INC_SEL 0xA4 GPIO_IND_SEL IO and Interrupt IOINT_CLK_EN 0xA5 GPIO_INE_SEL Controller 0xA6 GPIO_INF_SEL 0xA9 GPIO_ING_SEL...
  • Page 24 AN261-CMT2187A User Guide SFR Name Clock Gate Module Address Control Page 0xBD TACCR0_L 0xBE TACCTL0_H 0xBF TACCTL0_L 0xC0 TACCR1_H 0xC1 TACCR1_L 0xC2 TACCTL1_H 0xC3 TACCTL1_L 0xC4 TACCR2_H 0xC5 TACCR2_L 0xC6 TACCTL2_H 0xC7 TACCTL2_L 0xC8 TACNT_H 0xC9 TACNT_L 0xCA TBCLK_DIV_H 0xCB...

  • Page 25: Related Register

    AN261-CMT2187A User Guide SFR Name Clock Gate Module Address Control Page AON_REG switch module Notes: [1] The configuration of the LBD register affects part of the TX circuit function, so the gated clock is drivenby TX_CLK_EN, and the LBD_CLK_EN gated clock only drives the LBD module itself. It is necessary to detect the battery voltage before the transmission to compensate the transmission power in operation, so it is recommended that user turns on TX_CLK_EN and LBD_CLK_EN at the same time before transmission.

  • Page 26: Interrupts And Wakeup

    As mentioned in the previous section, only system peripherals in the normally open domain can support wakeup system in STOP mode, which we call the wakeup source. The wakeup source of CMT2187A mainly comes from the following three functional modules: ...

  • Page 27: Interrupt Source And Interrupt Control

    8.3 Interrupt Source and Interrupt Control The wakeup sources for CMT2187A have been described in the previous section. Since they support a pure wakeup system, it can also be understood as the wakeup source system. The CMT2187A interrupt source that will be introduced in this section is mainly associated with the 8051 operating, that is, the specific processing of the interrupt response based on the code operation.

  • Page 28: External Interrupt Mapping

    AN261-CMT2187A User Guide 0x0073 External interrupt 7 IPL1[7] Notes: The T8051XC3 core controller has a minimum interrupt response time of 3 system clocks, which are provided by the internal 24MHz RC oscillator HFOSC or the external 26MHz crystal oscillator XOSC.
  • Page 29 AN261-CMT2187A User Guide COMP0_FLAG COMP1_FLAG INT_POLAR<0> IO_CHANGE_FLAG INT0 COMP0_OUT I/O Change Scan (Rising / Falling COMP1_OUT Edge Detection) D0 – D11 INT_POLAR<2> SLEEP_TMO_FLAG INT1 Sleep Timer INT2_SEL<3:0> TA_TMR_INT TA_CCR0_INT Timer A Interrupts TA_CCR1_INT TA_CCR2_INT TX FIFO Interrupt TX_SYM_EMPTY SPI_TXMTY INT_POLAR<2>...
  • Page 30 AN261-CMT2187A User Guide Chart 8-2. Peripheral interrupt source and eight external interrupt mapping Inter Interrupt Interrupt Descripti Inter Interrupt Interrupt Descript rupt Selection source rupt Selection source INT2_SEL = 0000 TA_TMR_INT INT3_SEL = 0000 TA_TMR_INT INT2_SEL = 0001 TA_CCR0_INT Timer A...

  • Page 31: Related Register

    AN261-CMT2187A User Guide Inter Interrupt Interrupt Descripti Inter Interrupt Interrupt Descript rupt Selection source rupt Selection source INT4_SEL = 1101 Interrupt INT5_SEL = 1101 Interrupt INT4_SEL = 1110 INT5_SEL = 1110 INT4_SEL = 1111 INT5_SEL = 1111 INT6_SEL = 0000...
  • Page 32 AN261-CMT2187A User Guide default Name address Function page values Interrupt enabling register 1 IEN1 0xE6 0x00 IRCON1 0xF1 0x00 Peripheral interrupt request flag register Interrupt priority register 1 IPL1 0xF6 0x00 INTCTL_0 0x92 0x00 INT0 - INT7 Interrupt polarity selected register...

  • Page 33: Gpio Module

    AN261-CMT2187A User Guide 9 GPIO Module 9.1 Basic Function The CMT2187A series chips support up to 6 GPIOs, which are GPIO0, GPIO1, GPIO6. GPIO7, GPIO8, GPIO10. And the operating modes are as followed. Table 9-1. GPIO Operating Modes Property 1...
  • Page 34 AN261-CMT2187A User Guide Dn_open_drain Dn_out OUTPUT Dn_pd_odrv Dn_pd_pullup Dn_pd_pullup2 Dn_pd_idrv ~Dn_pd_idrv 500k Dn_in Dn_pd_idrv INPUT Dn_pd_pulldown ~Dn_pd_idrv ~Dn_pd_pullup ~Dn_pd_pullup2 Dn_pd_ana ANALOG Dn_ana ~Dn_pd_ana Chart 9-1. GPIO Functional Diagram Table 9-2. Function Description of GPIOs Port Name Signal type Description General IO PAD...

  • Page 35: Gpio Digital Input

    AN261-CMT2187A User Guide Port Name Signal type Description control signal otherwise Dn_pd_odrv = 1; When Dn is used as the digital input mode, Dn_pd_idrv = 0, otherwise Dn_pd_idrv Dn_pd_idrv = 1 When the Dn is used as a digital input mode, the corresponding...

  • Page 36: Gpio Digital Output

    AN261-CMT2187A User Guide 9.4 GPIO Digital Output When GPIO is configured as output:  the output channel is enabled.  Open drain output mode： If the output register is 0, the output NMOS is enabled. If the output register is 1, the output NMOS and PMOS are disabled, and GPIO is in a high resistance state.
  • Page 37 AN261-CMT2187A User Guide t0_gpio_sel<3:0> Sync by t0_in SYS_CLK as INT2 – INT7 sources ioc_detected Change Scan Read through GPIO_IN_SFR<11:0> Chart 9-2. Functional Block Diagram of GPIO as Digital Inputs By configuring the register t0_gpio_sel<3:0>, the user can select any digital input signal from D0-D11 that is synchronized by SYS_CLK to send to the external input t0_in of Timer 0.

  • Page 38: Gpio Digital Output Mapping

    AN261-CMT2187A User Guide Peripheral MUX Selection Signal MUX Output Purpose Module Output TA_CCI1_GPIO_SEL<3: ta_cci1_in One of the Timer A external capture source 0> TB_CCI0_GPIO_SEL<3: tb_cci0_in One of the Timer B external capture source 0> Timer B GPIO_ING_SEL TB_CCI1_GPIO_SEL<3: tb_cci1_in One of the Timer B external capture source 0>...
  • Page 39 AN261-CMT2187A User Guide Select Item Function mosi_out Data output of SPI master mode miso_out Data input of SPI slave mode Access register chip selection output of CMT specific 4-wire in SPI csb_out master mode Access FIFO chip selection output of CMT specific 4-wire in SPI...
  • Page 40 AN261-CMT2187A User Guide GPIOn Selected signal and code value Output signal source GPIO1_OUT_SEL<3:0> = 4'd10 csb_out GPIO1_OUT_SEL<3:0> = 4'd11 ta_ccr0_out GPIO1_OUT_SEL<3:0> = 4'd12 ta_cc1_out GPIO1_OUT_SEL<3:0> = 4'd13 ta_ccr2_out GPIO1_OUT_SEL<3:0> = 4'd14 t0_ov_out GPIO1_OUT_SEL<3:0> = 4'd15 t1_ov_out GPIO2_OUT_SEL<3:0> = 4'd0 gpio_out_sfr<2>...
  • Page 41 AN261-CMT2187A User Guide GPIOn Selected signal and code value Output signal source GPIO4_OUT_SEL<3:0> = 4'd3 tb_cc1_out GPIO4_OUT_SEL<3:0> = 4'd4 tb_ccr2_out GPIO4_OUT_SEL<3:0> = 4'd5 nss_out GPIO4_OUT_SEL<3:0> = 4'd6 sck_out GPIO4_OUT_SEL<3:0> = 4'd7 miso_out GPIO4_OUT_SEL<3:0> = 4'd8 mosi_out GPIO4_OUT_SEL<3:0> = 4'd9 fcsb_out GPIO4_OUT_SEL<3:0>...
  • Page 42 AN261-CMT2187A User Guide GPIOn Selected signal and code value Output signal source GPIO6_OUT_SEL<3:0> = 4'd12 ta_cc1_out GPIO6_OUT_SEL<3:0> = 4'd13 ta_ccr2_out GPIO6_OUT_SEL<3:0> = 4'd14 t0_ov_out GPIO6_OUT_SEL<3:0> = 4'd15 t1_ov_out GPIO7_OUT_SEL<3:0> = 4'd0 gpio_out_sfr<7> GPIO7_OUT_SEL<3:0> = 4'd1 port0_out<7> GPIO7_OUT_SEL<3:0> = 4'd2 tb_ccr0_out GPIO7_OUT_SEL<3:0>...
  • Page 43 AN261-CMT2187A User Guide GPIOn Selected signal and code value Output signal source GPIO9_OUT_SEL<3:0> = 4'd5 nss_out GPIO9_OUT_SEL<3:0> = 4'd6 sck_out GPIO9_OUT_SEL<3:0> = 4'd7 miso_out GPIO9_OUT_SEL<3:0> = 4'd8 mosi_out GPIO9_OUT_SEL<3:0> = 4'd9 rxd0_out GPIO9_OUT_SEL<3:0> = 4'd10 txd0_out GPIO9_OUT_SEL<3:0> = 4'd11 ta_ccr0_out GPIO9_OUT_SEL<3:0>...

  • Page 44: Gpio Level Flipping Detection

    AN261-CMT2187A User Guide GPIOn Selected signal and code value Output signal source GPIO11_OUT_SEL<3:0> = 4'd14 t0_ov_out GPIO11_OUT_SEL<3:0> = 4'd15 t1_ov_out Notes: [1]. The default mapping is controlled by the GPIO_OUT_SFR<11:0> register group and for the reason that the register group does not support the bit access mode, so the control output needs to follow the "read-change-write" mode.
  • Page 45 AN261-CMT2187A User Guide D11_IN Strong-Pull Week-Pull D10_IN D9_IN D8_IN D7_IN D6_IN D5_IN D4_IN D3_IN D2_IN D1_IN D0_IN Chart 9-3. Independent Key Connection Diagram D0-D11 in the figure below are all connected to the ground, so these ports can all enble the pull-up digital input port mode, and configure Dn_POLAR (n generally refers to any number from 0-11, each IO has a corresponding polarity selection bit) to 1, that is, the normal state is 1.
  • Page 46 AN261-CMT2187A User Guide According to the above connection method, D0-D11 is a matrix keyboard consist of D5-D11, which is used as a set of input detection, and D0-D4, which is used as a set of output control. Before entering the STOP mode, user needs to configure D0-D4 as digital output mode, with output value of 0.
  • Page 47 AN261-CMT2187A User Guide default Name address Functions page values GPIO_ING_SEL 0xA9 0x00 GPIO Input function mapping GPIO_OUTA_SEL 0xAA 0x00 GPIO output function mapping GPIO_OUTB_SEL 0xAB 0x00 GPIO output function mapping GPIO_OUTC_SEL 0xAC 0x00 GPIO output function mapping GPIO_OUTD_SEL 0xAD 0x00...

  • Page 48: Timer0 Module

    AN261-CMT2187A User Guide 10 Timer0 Module 10.1 Basic Function Timer0 is a 16-Bit programmable timer/counter that can be configured with TMOD registers to select how it works, start or stop counting, and generate counting overflow interrupts. Timer0 supports 3 working modes and they are shown as Table 10-1.

  • Page 49: Timer 0 Mode 1

    AN261-CMT2187A User Guide  If TMOD.GATE0 is set to 1, the gate control trigger counting is selected. it requires high level of external interrupt t0_int0_n and Ton.tr0 to trigger Timer0 counting.  If TMOD.GATE0 is set to 0, Timer0 counting is triggered as the TCON.TR0 is set to 1 ...

  • Page 50: Related Register

    AN261-CMT2187A User Guide Chart 10-3. Block diagram of Timer 0 mode 2 When Timer0 works in Mode2, the counter is automatically overloads with initial value of 8 bits, and when the TL0 count overflows, it automatically loads the value saved by TH0 (the initial value), making TL0 re-count from the initial value.

  • Page 51: Timer1 Module

    AN261-CMT2187A User Guide 11 Timer1 Module 11.1 Basic Function Timer1 is a 16-Bit programmable timer/counter that can be configured with TMOD registers to select how it works, start or stop counting, and generate count overflow interrupts. Timer 1 supports 3 kinds of working modes, which are shown in the following table.

  • Page 52: Timer 1 Mode 1

    AN261-CMT2187A User Guide  If TMOD.GATE1 is set to 1, the gate control trigger counting is selected. it requires high level of external interrupt t1_int1_n and TCON.TR1 to trigger Timer1 counting.  If TMOD.GATE1 is set to 0,Timer1 counting is triggered as the TCON.TR1 is set to 1 ...

  • Page 53: Related Register

    AN261-CMT2187A User Guide Chart 11-3. Block Diagram of Timer1 Mode2 When Timer1 works in Mode2, the counter is automatically overloads with initial value of 8 bits, and when the TL1 count overflows, it automatically loads the value saved by TH1 (the initial value), making TL1 re-count from the initial value.

  • Page 54: Spi Module

    AN261-CMT2187A User Guide 12 SPI Module 12.1 Basic Function The serial peripheral interface (SPI) allows the chip and peripherals to communicate in a half/full duplex, synchronous and serial manner. It supports master mode and slave mode from the operating manner view.

  • Page 55: Configuration Option

    AN261-CMT2187A User Guide (CPOL = 1) (CPOL = 0) MISO from master MOSI from slave to slave Chart 12-1. SPI Interface Timing（CPHA = 1） CPOL = 1 CPOL = 0 MISO from master MOSI from slave to slave Chart 12-2. SPI Interface Timing（CPHA = 0）...

  • Page 56: Working Mode

    AN261-CMT2187A User Guide SCK will be high in IDLE state; if SPI_CKPOL_SEL is set 0, SCK will be low in IDLE state. The following figure shows the edge of data sampling and transmitting when configured with different clock polarities and phases.

  • Page 57: Status Flag

    AN261-CMT2187A User Guide SPI_CTL_0.SPI_BIDI_MODE ； includes full duplex half-duplex. Three variables SPI_CTL_0.SPI_BIDI_OEN；SPI_CTL_0.SPI_RX_ONLY can be configured as the following list and acheive 4 working modes. Table 12-2. SPI Module Operating Modes SPI_BIDI_MODE SPI_RX_ONLY SPI_BIDI_OEN Mode Selection Working Mode Priority 1'b0 1'b0...
  • Page 58 AN261-CMT2187A User Guide  Busy flag（SPI_CTL2.SPI_BUSY flag bit） ，when the SPI is in the process of transmission, the flag bit wil be pulled high.  Send buffer free flag (SPI_CTL2.SPI_TXMTY flag bit); When the SPI is configured with new transmiting data, the flag bit will be pull low. When the new transmitting data is configured and transmited successfully, the flag bit will be pull high.

  • Page 59: Uart Module

    AN261-CMT2187A User Guide 13 UART Module 13.1 Basic Function The on-chip UART of CMT2187A is a flexible full-duplex asynchronous transceiver fully compatible with the 8051 architecture. The baud rate is configured by the software and supports the following 4 operating modes. ...
  • Page 60 AN261-CMT2187A User Guide SBUF0 Write 12xT PCLK PCLK PCLK txd0 rxd0_o PCLK Chart 13-2. Transmission Timing Diagram for UART in Mode 0 Mode0 receiving structure diagram is shown in the below figure. SBUF0 Read SBUF0 RX Shift Register rxd0_o Data In rxd0_i...

  • Page 61: Asynchronous Full - Duplex Mode With Configurable Baud Rate (Mode 1 And Mode 3)

    AN261-CMT2187A User Guide SCON0 Write 12xT PCLK PCLK PCLK txd0 PCLK rxd0_i REN0 PCLK SBUF0 D[7:0] Chart 13-4. Receiving Timing Diagram of UART in Mode 0 13.3 Asynchronous Full-duplex Mode with Configurable Baud Rate (Mode 1 and Mode 3) Both mode 1 and mode 3 of the UART module are asynchronous full-duplex transceiver mode with variable baud rates.
  • Page 62 AN261-CMT2187A User Guide The frame formats of mode 1 and mode 3 are shown in the below figures. STOP STOP Chart 13-5. Frame Format of Mode 1 and Mode 3 of UART The baud rates in mode 1 and mode 3 depend on overflow rate of Timer1. The transmission and receiving block diagrams are shown in the below figures.
  • Page 63 AN261-CMT2187A User Guide Configure Timer1 to generate the baud rate:  TMOD.M1[1:0] is configured as 10 (Timer1 in mode 2), TMOD.GATE1 is configured as 0, and TMOD.C/T1 is configured as 0.  Write the 8-bit initial count value to the TH1.

  • Page 64: Asynchronous Full - Duplex Mode With Fixed Baud Rate (Mode 2)

    AN261-CMT2187A User Guide When the mode 1 or mode 3 receiving mode of UART is enabled, the receiving enable bit SCON0.REN0 must be set 1 first, then the RxD pin state is sampled at 16 times of the baud rate, then wait for the falling edge of the start bit.
  • Page 65 Timer1 overflow period. It's the most simple but practical when Timer 1 operating in mode 2. However, the CMT2187A HFOSC clock source supports relatively limited frequencies, namely 24 MHz and external 13 MHz (generated by 26 MHz/2). Therefore, the corresponding baud rate options are also limited.
  • Page 66 The higher baud rate is basically unable to be used. In order to enable CMT2187A to support more baud rate options, it is embedded with enhanced mode on chip. CMT2187A can set USART_SEL (located in SFR register USART_CTL) to 1, otherwise canceling the 12 frequency divider in front of the Timer1 clock source and directly provide Timer1 from FPCLK as the clock source, as shown in the following figure.

  • Page 67: Related Register

    AN261-CMT2187A User Guide Table 13-2. UART baud rate errors in enhanced mode (Timer1 Mode 2) SMOD=1 SMOD=0 Target Baud TH1 Setting Actual Baud Actual Baud rate Setting Error rate Value Error rate rate rate: Value 4800 4808 0.16% 9600 9615 0.16%...

  • Page 68: Timer A/Timer B Module

    AN261-CMT2187A User Guide 14 Timer A/Timer B Module Both Timer A and Timer B consist of a 16-bit timer/counter and three capture/comparators, enabling multiple capture/comparators, PWM outputs, and time intervals for counting trigger conditions. Timer A has multiple interrupt modes that trigger overflows and capture/comparators from the timer/counter. Characteristics of Timer A / Timer B includes：...

  • Page 69: Operation Method

    AN261-CMT2187A User Guide Note: The structure of Timer A and Timer B are identical. The figure above shows the structure of Timer A. 14.1 Operation Method The operation of Timer A/Timer B module is controlled by software. TACCR0TH/TBCCR0TH mentioned in this section is a configurable 16-bit count threshold.
  • Page 70 AN261-CMT2187A User Guide 14.2 Up Mode In Up mode, user can configure the count threshold TACCR0TH or TBCCR0TH to any value, and TACNT (or TBCNT) will increase from 0 to the threshold TACCR0TH (or TBCCR0TH) repeatedly, with the count period being TACCR0TH (or TBCCR0TH) +1.

  • Page 71: Continuous Mode

    AN261-CMT2187A User Guide 14.3 Continuous Mode In continuous mode, TACNT (or TBCNT) is increased from 0 to 0xFFFF repeatedly, reset and then counts from 0. In this mode, the 3 sets of capturer/comparator CCR0 ~ CCR2 have the same function and operate independently, which is different with the up mode.
  • Page 72 AN261-CMT2187A User Guide calculated via the equation of TACCR0TH =TACCR0TH+ n, the same goes for ta_ccr1. TACCR1THb TACCR1THc TACCR1THd TACCR0THd TACCR0THb TACCR0THc 0xFFFF TACCR1THa TACCR0THa Chart 14-6. Schematic for Independent Operation of Each Capture/Compare of Timer A (Same for Timer B) 14.4 Up / Down Mode...
  • Page 73 AN261-CMT2187A User Guide 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SYS_CLK TACNT TACCR0TH-1 TACCR0TH TACCR0TH-1 TA_CCR0_INT TA_TMR_INT Chart 14-8. Schematic for Interrupt of Timer A Working in Up/ Down Mode The up / down mode can support the application requiring Dead Time between two output signals. For example, 2 outputs that drive an H-bridge synchronously while cannot output a high level at the same time to avoid overload.
  • Page 74 AN261-CMT2187A User Guide 14.5 Capture/compare Module Timer A / B contains 2 to 3 independent capture/compare modules for capturing TACNT (or TBCNT) data or generating time intervals. Note that, in Up and Up / Down modes, TACCR0 (TBCCR0) is used as a period register and cannot store captured values.

  • Page 75: Compare Mode

    AN261-CMT2187A User Guide Read Trigger capture capture source Read Capture Recapture capture success result Trigger capture source No capture occurs after reading Clear the Trigger capture corresponding source COV bit Capture overflow COV=1 Trigger capture source Chart 14-11. Schematic for Capture Mode State and Interrupt of Timer A ...
  • Page 76 AN261-CMT2187A User Guide Table 14-2. Various Modes of Output Unit OUTMODE Mode Description REMARKS Direct mode, the output TA_OUTx is configured by Applicable to the 3 OUTPUT register CCRx_OUT. capture/compare modules. When TACNT counts to TACCRxTH, the output TA_OUTx is set and the state retains until Timer A is...
  • Page 77 AN261-CMT2187A User Guide 0xFFFF TACCR0TH TACCR1TH 输出模式1：置位 输出模式2：翻转/复位 输出模式3：置位/复位 输出模式4：翻转 输出模式5：复位 输出模式6：翻转/置位 输出模式7：复位/置位 EQU0 EQU1 EQU0 EQU1 EQU0 Timer INT Timer INT Timer INT Chart 14-12. Schematic for Timer A Output in Up Mode  Example for output in continuous mode...

  • Page 78: Related Register

    AN261-CMT2187A User Guide 0xFFFF TACCR0TH TACCR2TH 输出模式1：置位 输出模式2：翻转/复位 输出模式3：置位/复位 输出模式4：翻转 输出模式5：复位 输出模式6：翻转/置位 输出模式7：复位/置位 Timer INT EQU2 EQU0 EQU2 Timer INT EQU2 EQU0 EQU2 Chart 14-14. Schematic for Timer A Output Up / Down Mode 14.7 Related Register Table 14-3. 16-Bit Timer A and Timer B Register Set List...

  • Page 79: Basic Function

    AN261-CMT2187A User Guide default Name address Functions page values 0xC9 TACNT_L 0x00 0xCA TBCLK_DIV_H 0x00 TimerB clock source frequency division register 0xCB TBCLK_DIV_L 0x00 0xCC TBC_H 0x00 TimerB control register 0xCD TBC_L 0x00 0xCE TBCCR0TH_H 0x00 TimerB capture/compare module 0 register...
  • Page 80 16 Sleep TimerModule 16.1 Basic Function CMT2187A provides a built-in Sleep Timer to satisfy the low-power sleep and periodically wake-up applications. Clock source is provided by the system auxiliary clock (LFOSC). The Sleep Timer starts counting only in STOP mode and the system is woke up when the count overflows.

  • Page 81: Low Voltage Reset (Lvr)

    Low voltage reset refers to the reset signal of the chip when the power supply voltage falls below the VLVR threshold voltage. The default reset release voltage of the CMT2187A is 1.8V when it is powered on for the first time.
  • Page 82 19 Sub-1G Transmitting Module 19.1 Introduction Sub-1G transmitter module is embedded in CMT2187A, adopting the phase locked loop (PLL) of fractional frequency division technology and using 26MHz XOSC, which realizes different transmission frequency points through different frequency division ratio set by software. The module supports OOK/(G)FSK modulation, which is based on the direct synthesis of RF frequency.
  • Page 83 480MHz-630MHz. 19.2 PA Output Method CMT2187A adopts an efficient single-ended Class E PA structure, with transmitting power up to +13dBm PA has the feature of adjustable RAMP slope, as shown in the figure below. By using the TxSoC RFPDK tool software, after setting the target working parameters, the corresponding PA Ramping parameter will be automatically generated.
  • Page 84 AN261-CMT2187A User Guide plln pllk 配置 配置 TX基带信号生成模块 1级 2级 plln 缓存 缓存 AFC/ symbol速率配置 高斯变换 频率控制 （SFR） pllk (analog) FSK/OOK配置 8bit基带数据组 1~8bit单bit基带信号 （SFR） empty Power code nodata 单端差分选择 RAMP done Idac code ramp时间配置 LBD检测结果 基带数据发射长度 …… （SFR） PA功率 PA功率...
  • Page 85 AN261-CMT2187A User Guide  Baseband data transmitting type: The working mode after transmitting the last bit of data (no further filling), which can be configured to: stop transmitting, cycle transmitting the last filling data group, transmitting normal 0 or transmitting normal 1.
  • Page 86 AN261-CMT2187A User Guide Table 20-1. Comparison of the CMT2187A Direct mode and Buffer mode Buffer Direct Contrasting Description Mode Mode Buffer mode is generated by TX baseband signal generation module rate clock, this clock source is from 26MHz crystal, so...

  • Page 87: Package Outline

    Value 0xC9 0x00 PA_POWER_TH_0 Transmitting data rate compensating register 0, 2.05V 20 Package Outline The CMT2187A package information is shown in the following: A2 A 0.25 θ Chart 21-1. SOP14 Package Table 21-1. SOP14 Package Scale Dimension (mm) Symbol...
  • Page 88 YYWW is the date number set by the packaging factory. YY represents the last 2 digits Second Line of the year and WW represents the work week Printing ①②③④⑤⑥ is the internal tracking number 22 Other Related Document Table 23-1. Other Related Document of CMT2187A Document Document Name Description www.hoperf.com Copyright © By HOPERF Page Rev 0.2 | 88/96...
  • Page 89 AN261-CMT2187A User Guide Number CMT2187A Develop environment Construction of develop environments, quick construction user guide CMT2187A Register Description Manual Detail information of the registers www.hoperf.com Copyright © By HOPERF Page Rev 0.2 | 89/96...

  • Page 90: Revise History

    AN261-CMT2187A User Guide 23 Revise History Table 24-1. CMT2187A Revise History Released Version Update chapter Update records Date Initial version 2024/09/27 Review and delete the SDR related description 2025/3/31 www.hoperf.com Copyright © By HOPERF Page Rev 0.2 | 90/96...
  • Page 91 Copyright. Sheen Hope Microelectronics Co., Ltd. All rights are reserved. The information furnished by HOPERF is believed to be accurate and reliable. However, no responsibility is assumed for inaccuracies and specifications within this document are subject to change without notice. The material contained herein is the exclusive property of HOPERF and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOPERF.
  • Page 92 AN261-CMT2187A User Guide Appendix A Table 25-1. T8051XC3 Instruction Set Mnemonic Description Opcode Bytes Cycles Arithmetic Operations 0x28.. ADD A, Rn Add Register to Accumulator ..0x2F ADD A, direct Add direct data to Accumulator 0x25 0x26 ADD A, @Ri Add indirect data to Accumulator...
  • Page 93 AN261-CMT2187A User Guide Mnemonic Description Opcode Bytes Cycles DA A Decimal Adjust 0xD4 Logical Operations 0x58.. ANL A, Rn AND Accumulator with Register ..0x5F ANL A, direct AND Accumulator with direct data 0x55 0x56 ANL A, @Ri AND Accumulator with indirect data...
  • Page 94 AN261-CMT2187A User Guide Mnemonic Description Opcode Bytes Cycles 0xE6 MOV A, @Ri Move indirect data to Accumulator 0xE7 MOV A, #data Move immediate data to Accumulator 0x74 0xF8.. MOV Rn, A Move Accumulator to Register ..0xFF 0xA8.. MOV Rn, direct Move direct data to Register ..0xAF...
  • Page 95 AN261-CMT2187A User Guide Mnemonic Description Opcode Bytes Cycles 0xD6 XCHD A, @Ri Exchange Accumulator nibble with indirect 0xD7 Boolean (Bit-Wise) Operations ANL C, bit AND Carry with direct bit 0x82 ANL C, /bit AND Carry with direct bit inverted 0xB0...
  • Page 96 AN261-CMT2187A User Guide Mnemonic Description Opcode Bytes Cycles Return from subroutine 0x22 RETI Return from interrupt 0x32 SJMP rel Short jump 0x80 No operation 0x00 www.hoperf.com Copyright © By HOPERF Page Rev 0.2 | 96/96...

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