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Ampex TBC-6 Service Manual

Digital time-base corrector (pal)
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Catalog No. 1809670-01
Issued: August 1985
TBC-6
DIGITAL TIME-BASE
CORRECTOR (PAL)
SERVICE MANUAL
AMPEX

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  • Page 1 Catalog No. 1809670-01 Issued: August 1985 TBC-6 DIGITAL TIME-BASE CORRECTOR (PAL) SERVICE MANUAL AMPEX...
  • Page 2 Prepared by A VSD Technical Publications Ampex Corporation 401 Broadway Redwood City, CA 94063 Copyright 1985 by Ampex Corporation Catalog No. 1809670-01 Issued: August 1985...
  • Page 5 Don't take chances. fully trained. Ampex equipment should be operated and maintained by fully quali.fied personnel. 2 Do not touch heavily loaded or overheated components without precaution to avoid If someone seems unable to free himself while burns.

  • Page 6: Good Practices

    In maintammg the equipment covered m this manual, please keep in mind the following standard good practices: When connecting any instrument (oscilloscope, waveform monitor, etc.) to a high-frequency output, use the appropriate termination resistor at the input of the instrument, unless the instrument is terminated internally. 2 When inserting or removing printed wiring assemblies (PW As), cable connectors, or fuses, always turn off power to the affected portion of the equipment.
  • Page 7 Operation of this equipment in a residential area is likely to cause interference in which case the user at his own expense will be required to take whatever measures may be required to correct the interference. Ampex 1809670-01 vii/viii...
  • Page 9 Related Publications General Description • Features. Functional Description. Physical Description. Typical Applications. Specifications Introduction General Description • TBC-6 Simplified Block Diagram Discussion Signal Processing Video Input PWA Input Video Processing. Monitor Video Sync Strip Video Tape Vertical Detection • 2-11 2-10 Tape H-Sync and Video Mute •...

  • Page 10: Table Of Contents

    Power Supply Check. 3-12 Power Supply Adjustment ..3-13 System Phase Adjustment 3-14 Unity Gain. 3-15 Burst/VCO A/D Ramp • 3-16 Velocity Compensation Gain and Quadrant Discriminator 3-10 3-17 Memory System PWA Alignments • 3-10 Ampex 1809670-01...
  • Page 11 Removing and Replacing AC Power Switch Assembly ....SECTION 5 SUPPLEMENTAL INFORMATION Introduction • • • • • • • • • Selectable Jumper Options • • Ampex 1809670-0...
  • Page 12 Test Points. • • • • • • • • • • • • • • • • • • • • • • • • TBC-6 Motherboard PW A 5-1 4 Adjustments ....

  • Page 13: List Of Illustrations

    FIGURE TITLE PAGE LIST OF ILLUSTRATIONS Typical TBC-6 System Configuration Simplified Block Diagram TBC-6 Signal Flow, Block Diagram . . . Video Input PW A, Block Diagram 2-15 Tape Clock PW A, Simplified Block Diagram . . . 2-16 Tape Clock PW A, Block Diagram...

  • Page 14: List Of Tables

    LIST OF TABLES TITLE TABLE PAGE TBC-6 Printed Wire Assemblies ..TBC-6 Specifications 2-32 Line Counter Sequence 3 -1 Test Equipment • . . . Video Input PWA Jumper Locations Tape Clock PW A Jumper Locations...
  • Page 16 T e e - a c o r r e c t o m e - B as e i gi t al T i T B C � D - 0 1 1 8 0 9 6 7 0 A m p e x 1 - 0...

  • Page 17: Section 1 General Information

    This manual provides information necessary to operate and maintain the PAL version of the TBC-6 Digital Time-Base Corrector (DTBC), Ampex Part No. 1451605. This section is an introduction to the TBC-6, its features and system specifications. Theory of Section 2,...

  • Page 18: Typical Applications

    Blanking and sync are inserted in the resultant video to form the composite video output signal. The TBC-6 is a self-contained unit that may be mounted in a table-top cabinet, a VTR console, or rack mounted. Electronic circuits are contained on four individual printed wiring assemblies (PWAs) which plug into a motherboard PWA.
  • Page 20 TBC-6 Table 1-2. TBC-6 Specifications Physical Characteristics Height: (133 mm) 5.25 in. Width: (500 mm) 19.7 in. Depth: (549 mm) 21.625 in. Weight: (18 kg) 40 lb ° ° ° ° Operating temperature: to + 40 C) 32 to 104...

  • Page 23: General Description

    TBC-6 SECTION 2 THEDRV DF DPERATIDN This section describes TBC-6 functional operation and interrelation of PW As in the system. Also included are block diagrams of the overall system and individual PWAs that comprise the system. Time-base correction compensates for timing errors introduced when video signals are recorded on magnetic tape.
  • Page 24 TBC-6.SIMPLIFIED BLOCK DIAGRAM DISCUSSION TBC-6 The TBC-6 Digital Time-Base Corrector affords correction over a 14-line window, slow-motion processing to 1-1/2X forward when used with the Ampex VPR-6, and recognizable pictures in shuttle to 300 in/s. In addition to a choice of two...
  • Page 25 RF IN TIMING � DETECTOR MEMORY READ/WRITE CONTROL CONTROL ReAO TIMING REFERENCE VIDEO REFERENCE REF VIDEO SYNC LOOP-THROU GENERATOR VIDEO OUTPUT TIMING ADVANCE REFERENCE [}:::> +5V SENSE ---·� POWER D CDNN<CTOR _________ _ INTERFACE SUPPLY +12V AC POWER -12V Ampex 1809670-01...
  • Page 26 TBC-6 SYNC-COHERENT SYNC-COHERENT SU BCARRIER _____ .;_ __ ,:_,_�.:..-----------------------------------------------------------------------------------------fO)suBCARRIER OUTPUT ENCODE Fsc DECODE Fsc � � INPUT VIDEO INPUT VIDEO DIGITAL REF 4Fsc BURST > I■-■■ READ4Fsc TIME-BASE <l> ERROR MONITOR 32-LINE I■-■■■ MONITOR TIME BASE ERROR DATA cavcoAV MEMORY...
  • Page 27 TBC back panel. SIGNAL PROCESSING See Figure 2-2. Video input to the TBC-6 is routed from the rear panel connectors to the Video Input PW A. In the Video Input PW A, either video A or video B is...
  • Page 28 TBC-6 ---------- TTL DOs (VPR) DROPOUT ENCODER FF ( DROPOUT) E (HIGH VIDEO) V I DEO HIGH HIGH VIDEO COLOR ROCESSOR TR I -STATE HETERODYNE PROCESSING FILTER _:S,,,---------, CLAM CHROMA CONVERTER INVERTER L ______ 4 F sc VIDEO V I DEO...
  • Page 29 @-..i .._ CHROMA CLAMP CONVERTER VIDEO IN INVERTER BYPASS VIDEO MONITOR VIDEO OUT NORMAL SYNC STRIPPER BURST COLOR SYNC PROCESSING PROCESSING AUXILIARY VIDEO L ______ _ ,------ DIGITAL BURST TAPE H UP/DOWN GATED SYNC TAPE V L ___ _ Ampex 1809670-01...
  • Page 30 VIDEO IN ____ _J L _________________ ______________ P::J ___________ _ _______ � - �� �-o_ u _ T P_ u _ _ _ -- ________ ZERO OFFSET (VPR) Figure 2-2. TBC-6 Signal Flow, Block Diagram (Sheet 2 of 2) Ampex 1809670-01...
  • Page 31 r-------------------�------�---- SERIAL-TO- ARALLEL- ARALLEL TO-SERIAL DROPOUT CONVERTER CONVERTER ENSATOR :> READ- INSERT 1----Y QUEUE ERWORD 16 X 1 11/, ,,,,,, DATA � LOGIC .,___ � I� ..DELAY II,. 32 LINE EMORY SYNC WRITE IN 13 B, IL...A 8 ..BUFFER �...
  • Page 32 - - - -, ,- - ------ DIGITAL BURST TAPE H VEL COMP WRITE UP/DOWN TAPE CLOCK PWA GATED SYNC INFO ---------� TAPE V L ________ _ ___________ _J Figure 2-2. TBC-6 Signal Flow, Block Diagram (Sheet 1 of %)
  • Page 34 Tape Clock PW A. The filter clamp establishes a fixed back porch level for the TBC-6 and a reference level for the AID converter. In the A/D converter the video is sampled, at a tape 4Fsc rate, converted and routed to the Memory System PWA.
  • Page 35 INPUT VIDEO A or INPUT VIDEO B is selected for use within the TBC-6. The clamping circuit is set to maintain a back-porch level of 0V. The clamp is inhibited when there is no sync and is enabled by an output (input clamp) from the sync strip video circuits.
  • Page 36 TBC-6 ELEC NPUT GAIN ANEL) O AMAL/BY 75 0. ------c / • D::..-<') ..75 0. MONI � OUTPUT CLAM H 2) ),,6. ACK PA _Q_,e_ _ ... � />---------------V\/1 . -------1 -�----· -----------------------------------•�- ""'l-1t-----------------------------•-� CLAM H 2) VIDEO ( ►...
  • Page 37 •-------------------! >----- �, DECODE Fsc SUBC V AXIS ◄.- ERROR XTAL � (TAPE CLOCK) SERVO HET/SLOW ♦ SERVO ERROR V • RF DROPOUT DETECTER BURST SAMPLE SUBC ENCODE Fsc (TAPE CLOCK) TAPE RF 39 ___________________________________________________ _. (BACK PANEL) Ampex 1809670-01...
  • Page 38 TBC-6 DROPOUT ENCODE BUS FLOAT INPUT DATA A/D CLAMP MEMORY SYSTEM TRI- STATE LATCH CLAMP TAPE H SYNC (TAPE CLOCK) TRI- TAPE VERT STATE VERT LATCH �-----... ------------------------------------4162 (TAPE CLOCK) DETECTOR GATED SYNC .-------... ------------------------------------t171 (TAPE CLOCK) --------..-�v ►...
  • Page 39 RF DROPOUT -, -- ------ ------ -------------- • (SH 1) \ DROPOUT ENCODE L... (VPR CONN) BUS FLOAT TAPE DROPOUT A/D CLAMP TRI- STATE LATCH CLAMP I • )lo ---- ---- •..J A/D VIDEO (SH 1) - ..TRI- STATE VERT LATCH DETECTOR...
  • Page 40 TBC-6 crosses an estimated 50% point in a negative direction and drives positive when the sync reaches the 50% point going in a positive direction. The 50% crude pulse drives a sampler where sync tip and back porch level are extracted. By adding sync tip and back porch level and dividing by two an analog 50% sync voltage is obtained.
  • Page 41 TBC-6 circuits, as selected by the input switch, goes to the AID filter. The filter output goes to the AID clamp which clamps the filtered video to the AID reference level to establish a fixed, consistent level. The AID converter samples the analog level using tape 4Fsc timing from the Tape Clock PWA.
  • Page 42 TBC-6 crosses an estimated 50% point in a negative direction and drives positive when the sync reaches the 50% point going in a positive direction. The 50% crude pulse drives a sampler where sync tip and back porch level are extracted. By adding sync tip and back porch level and dividing by two an analog 50% sync voltage is obtained.
  • Page 43 TBC-6 circuits, as selected by the input switch, goes to the A/D filter. The filter output goes to the AID clamp which clamps the filtered video to the AID reference level to establish a fixed, consistent level. The AID converter samples the analog level using tape 4Fsc timing from the Tape Clock PWA.
  • Page 44 Memory System PW A. The Tape Clock PW A also generates the tape 4Fsc signal used in the Video Input PWA and Memory System PWA. The TBC-6 contains three VCO circuits, one normal VCO and two search VCOs. At normal play and slow-motion speeds, the normal VCO tracks incoming horizontal sync and provides a sync gate which prevents noise from triggering the horizontal sync circuits.
  • Page 45 TBC-6 The discussion of the Tape Clock PWA refers to Figure 2-5 and includes details on the following circuits : Tape vertical processing Tape horizontal processing Normal VCO Search VCO Multiplexer output logic 2-18 Tape Vertical Processing Within the tape vertical processing circuits (TVPC) the off-tape vertical sync is used to generate tape referenced vertical timing throughout the TBC.
  • Page 46 ENCODE/DECODE 7.8 kHz AND 3.9 kHz ENCODE/ DECODE DECODE Fsc V-AXIS AND VECTOR COMPENSATION QUALIFY GATE 1/2 LINE UP/DOWN WIDE/NARROW FLYWHEEL SYNC MULTIPLEX SEARCH VCO 0.4Fsc GATED SYNC OUTPUT CIRCUITS VCO WRITE SYNC TERMINATE 4Fsc Figure 2- Tape Clock PW Simplified Block Diagr,: Ampex 1809670-01...
  • Page 48 VCO WRITE TIMING _ �----- 1/2 LINE (-)(SH 1) SEARCH GATED SYNC COUNTER � DOWN DIGITAL 1/2 LINE <l> COMP INHIBIT SYNC TERMINATE LOGIC -'-1135 PHASE- LOCKED LOOP PULSE Figure� Tape Clock PWA, Block Diagr (Sheet 2 o Ampex 1809670-01...
  • Page 49 TBC-6 ,.-:> 7-fl.. WRITE TIMING (SH 2) ENCODE 7.8 kHz (SH 1) HETERODYNE DIVIDER ENCODE 3.9 kHz (SH 1) (-c4) TAPE 4Fsc (SH 2) SWITCH ENCODE Fsc I"J"' Fsc RESET (SH 1) .J'L.JL "1.11. ENCODER DIVIDER RAMP GENERATOR (.;-4) <l>MOD...
  • Page 50 TBC-6 2-20 Normal VCO The normal VCO consists of a voltage-controlled oscillator, a digital phase comparator, and a normal counter. The normal VCO 4Fsc output clocks the divide­ by-1135 normal counter. One output of the normal counter is an H-rate pulse, designated phase-lock loop pulse.

  • Page 51: Memory System Pwa (Continued)

    TBC-6 2-23 Encode/Decode Fsc The encode and decode circuits utilize dividers (counters), ramp generators, and phase modulators to generate the encode and decode Fsc signals used in the color circuitry and an encode Fsc signal used during heterodyne operation. During heterodyne the decode Fsc is generated by a burst lock oscillator on the Video Input PW A.
  • Page 53 TBC-6 During forward shuttle, input data rate is considerably faster than output data rate. It is often necessary to write two superwords during one read/write superword cycle. The dual-load function makes this possible by allowing an input superword to be loaded into its respective location during write B as well as write A. The dual­...
  • Page 54 TBC-6 REF COMP SYNC VIDEO MUTE REF 7.8 kHz REF H ---- '--- REF 4Fsc ---- ---- REF V REF V/64 VEL COMP_ COLOR FRAME WRITE VEL COMP WRITE WRITE 7.8 kH2 WRITE 7-.8 kHz ---- '--- -TAPE ---- 4Fsc...

  • Page 55: Write Control Logic

    4Fsc rate. To accommodate the timing difference, the write-in buff er has the ability to hold up to four superwords and to provide the serial-input function. The TBC-6 uses an array of byte-wide registers to buffer the data from the Converter into superwords, each of which are 16 bytes long.
  • Page 56 ADDRESS WRITE VCO VERT CONTROL LED DISP TAPE V/2 SEARCH SLOW ADDRESS AND CONTROL STEP FORWARD 1 OR 2 VEL COMP WRITE STEP BACK 1 OR 2 WRITE 7.8 kHz Figure 2· Memory System PW Simplified Block Diagr1 Ampex 1809670-01...
  • Page 57 TBC-6 During forward shuttle, input data rate is considerably faster than output data rate. It is often necessary to write two superwords during one read/write superword cycle. The dual-load function makes this possible by allowing an input superword to be loaded into its respective location during write B as well as write A. The dual­...
  • Page 58 DATA RING COUNTER SAMPLE RING TIME-BASE LATCHES COUNTER ERROR � PROFILE <l>MOD READ GENERATOR TIME NE529 4Fsc BASE � READ RAMP READ 4Fsc 4Fsc TIME BASE ERROR READ BURST COHERENT START READ Figure� Memory System PWA, Block Diagr Ampex 1809670-01...
  • Page 59 The TBC-6 uses an array of byte-wide registers to buffer the data from the A/D Converter into superwords, each of which are 16 bytes long.

  • Page 60: Read Control Logic

    TBC-6 2-30 Read Control Logic Data is read from memory using timing derived from reference 4Fsc. Reference vertical presets a read line address counter which divides reference horizontal by 16. Reference 4Fsc drives a 16-bit shift register which is preset by reference horizontal and generates output enable signals OEl through OE16.

  • Page 61: Video Output Pwa

    • Adds sync, burst, and reference timing to time-base-corrected video. Provides VIDEO OUT 1 and VIDEO OUT 2 outputs from the TBC-6 and a • processed TBC video signal to the to the input PW A •...

  • Page 62: Reference Sync And Timing

    TBC-6 The discussion of the output video PWA refers to Figure 2-8 and includes details on reference sync and timing generation and video processing. 2-36 Reference S yn c and Timing In the reference sync and timing circuits, the reference 4Fsc oscillator is phase­...

  • Page 63: Sync/Burst H-Calibrate Circuit

    TBC-6 routed to the normal and advanced sync PROMS and represents the type of line at that particular position in the frame. The ALC is clocked by the H 4Fsc signal and counts the number of pixels (0-1134) along the line. This information is converted to addresses (along-line address) and routed to a line (segment) PROM.
  • Page 65 WFM SHAPER SHIFTER CLAMP BLANKING .., (SH 3) VIDEO 2 SYNC ON-OFF COMP SYNC WPM SYNC ---..►t SHAPER (SH 2) BURST LEVEL BURST ----...i BURST ENV MULTIPLIER F LAG SHAPER (SH 3) SUB- CARRIER ------------------ (SH 2) Ampex 1809670-01...
  • Page 66 ► CLAMP PULSE VIDEO (SH 2) � � .;... -J-. � OUTPUT LATCH LATCH 8-BIT VIDEO MECL DATA SINX/X EQ. - � BLACK CLAMP CLIP �v- � VAR. READ BLACK CLIP MECL 4Fsc 4Fsc o.s. o.s. CLAMP MECL TTL MECL CONTRO L LINEARIZER CHROMA <l>...
  • Page 67 TBC-6 ADVANCED ✓ BURST GATE (SH 3) LINE - ALONG LI� ADV COMP SYNC UNe SSGMeNT ADDRESS PROM � ADV VERT L50-L53 ADVANCE LAB (7.8 kHz) S/B WINDOW(+) (SH 3) "ER REF H(- ) ADVANCED LINE �;�� TYPE OFFSET H(+)
  • Page 68 BIT 2 BIT 2 BIT 3 BIT 3 H 4Fsc REF 7.8 kHz H 2Fsc ..REF H( ) H(-) ZERO OFFSET LINE SYNC RETARD LINE COUNT (A0-A11) COUNTER ,..SIN-COS � i--- GENERATOR i..,. V/2 RESET(+) RESET (+) RESET H (-) 100 HzSIN REF PRESENT ( 100 Hz COS...
  • Page 69 REF H(- ) H (-) � LINE COUNT ER ..V /2 RESET (+) RESET(+) � RESET H (-) REF PRESENT ( BURST PRESENT(-) SYNC _,.. 'IDEO LUMA L OW INPUT SYNC RESET H(-) PASS STRI P FIL TEA CALIB MONO (-) ..
  • Page 70 NO. BURST GATE (SH 2): SYNC COMP BLANKING (SH 2) MONO (-) (SH 2) _ BURST BU AST FLAG (SH 1) FLAG SEARCH GENERA TOR gure 2· COLOR PRESENT COLOR PRESENT Video Outpu t PW (INPUT) S1mphf1ed Block Diagn (Sheet 3 of Ampex 1809670-01...
  • Page 71 Transition Transition Timing Timing Segment Beginning Segment Beginning Number ofSegment Operation Number of Segment Operation H sync (trailing) Burst gate (falling) Clamp pulse (rising) 27.3 Broad pulse (rising) Clamp pulse (falling) 1.76 32.0 Equalizing pulse (falling) 2.35 Equalizing pulse (rising) 34.35 Equalizing pulse (rising) H sync (rising)
  • Page 72 TBC-6 The reference Fsc is routed to the reference divider from which four Fsc signals are generated each with a 90 ° phase difference. The burst swing, having been detected in the reference 7 .8 kHz detector, generates the 7 .8 kHz that is used to modulate (supply burst swing to) the previously mentioned four Fsc signals.
  • Page 73 TBC-6 2-44 Read Pulse Generator The read pulse generator supplies a read pulse that allows accurate reading of information in the memory. The read pulse generator rephases the sync composite blanking signal with reference 4Fsc in order to establish an H coherent start-read reference.

  • Page 74: Preventive/Periodic Maintenance

    TBC-6 does not require preventive maintenance. MAINTENANCE ACCESS The TBC-6 consists of four large PWA assemblies installed in slots in a card cage enclosure, which provides interconnection at the board edges via a motherboard or backplane interconnect. All PW As are interchangeable from slot to slot. The top...
  • Page 75 The full complement of test equipment is not always used. Use of a particular instrument is called out where required in the procedure. Field testing of the TBC-6 cannot provide complete isolation of each PW A from system interactivity, as is the case in factory testing. It is helpful to remain aware of the functional signal paths as they proceed from board to board and from input to output, as they determine the order in which certain adjustments are made.
  • Page 76 Figure 3-1. Test Equipment Setup Results indicated in the procedures define normal operating parameters of the TBC-6. To isolate faults, make checks at points described in the procedures and check the waveform/voltage levels given. During such checks avoid unnecessary adjustments, as many of the controls are used to trim circuit tolerances at the time of manufacture and are not intended for field adjustment.
  • Page 77 3- 8 PRELIMINARY GUIDELINES Consult this check-list before beginning any alignment of the TBC-6. 1. Always install the TBC-6 power jumper to reflect the line voltage require­ ment. 2. Always perform a visual mechanical inspection of all accessible assemblies for any apparent physical damage before beginning any alignment.

  • Page 78: System Adjustments

    TBC-6 6. Power supply voltages should always be within tolerance before any adjust­ ment is made. SYSTEM ADJUSTMENTS System adjustments include power supply adjustments, unity gain adjustment, system phase adjustment, and velocity compensation adjustment. 3-10 Power Supply Check and Adjustment The power supply system.

  • Page 80: System Phase Adjustment

    TBC-6 3-13 SYSTEM PHASE ADJUSTMENT Use the following procedure to adjust TBC-6 subcarrier and horizontal phase to match EBU standard PAL house reference. Figure 3-3 shows location of controls on Video Output PW A. HOAIZ SUSC PHASE PHASE ��..c: � -o- □ -i-o-o-l-o- Figure 3-3.
  • Page 81 3-14 Unity Gain In order to properly set up unity gain on the TBC-6, the preliminary adjustments should be done on the Video Output PW A, then the Video Input PW A. The final adjustment is then done on the Video Output PW A. The following steps describe the proper sequence.
  • Page 82 TBC-6 c. Verify that output vectors displayed on vectorscope do not break up when video level control R218 is adjusted through entire range. If not proceed to step d. d. Readjust R161 and Rl62 on Video Input PWA and repeat step c.
  • Page 83 TBC-6 STEP 2 Tri-level waveform should display levels of +0.lV and +1.9V for the upper two levels of the waveform. If not proceed to step 3. STEP 3 Adjust offset control R167 and gain control R87 to obtain levels of +0.1 V and +1.9V for the upper two levels of the waveform.

  • Page 84: Balance

    TBC-6 3-18 Balance The balance adjustment aligns the difference amplifier that is used to derive the first order approximation. STEP 1 On Memory System PWA observe TP4 and set R262 on Tape Clock PWA to lV ±0.lV. STEP 2 On Memory System PWA observe Ul00-1 and adjust R39 for 0V ±0.lV.
  • Page 85 R119. STEP 5 Adjust burst amplitude for 286 mV, using R47. Note Terminate the video signal with 75Q at the oscilloscope for this procedure. Ideally, a high-accuracy differential plug-in would be used for this measurement. 3-12 Ampex 1809670-01...

  • Page 86: Signal Timing Checks And Alignment

    TBC-6 3-23 SIGNAL TIMING CHECKS AND ALIGNMENT The paragraphs that follow provide the means to ensure that the different elements of the output video signal comply with EBU standards for their duration and relative delay. 3-24 H-Sync Level Using sync level control R283, adjust H sync amplitude for 286 mV.

  • Page 87: Vco Frequency And Phase Comparator Alignment

    TBC-6 STEP 4 Turn TBC power on. Set R445 for 500 mVp-p subcarrier measured at TP49. STEP 5 Turn R461 slowly counterclockwise. Note that the subcarrier at TP49 goes to less than 30 mVp-p. STEP 6 Turn R461 slowly clockwise. Note that subcarrier goes to more than 500 mV and jumps back to 500 mVp-p.
  • Page 88 TBC-6 STEP 6 Adjust tape-h reset qualify delay control R269 for a smooth trace through the vertical region as shown in Figure 3-7. ----- I ••••• --E�• TPl with R269 Adjusted Too Far Counterclockwise 1111 TPl with R269 Correctly Adjusted Figure 3-7.

  • Page 89: Shuttle Damping

    TBC-6 STEP 7 Disconnect output video from channel 2 of the scope. Connect channel 2 scope probe to TP42. Fine tune R269 to obtain a smooth trace through the vertical interval and 1.0V for the upper voltage level at TP42.

  • Page 90: Slow-Motion Adjustments

    TBC-6 STEP 6 On the picture monitor, switch the scan switch to pulse cross and the input mode switch to A-B. STEP 6 Ensure that right-hand green LED is illuminated on the Memory System PWA, EDIT READY is on and INVERT is off.

  • Page 91: Slow-Motion Vector Compensation

    TBC-6 Note This may be done by observing vector jitter at both ends of variable play range and adjusting R 76 to try to equalize jitter at both ends. Minimize the jitter using R45 across entire range of variable play.

  • Page 92: Removal And Replacement

    SECTION 4 REMOVAL AND REPLAC EMENT GENERAL This section describes removal and reinstallation of the TBC-6 replaceable parts. The unit illustrated in this section is shown without a front door assembly, slide members, or trim pieces for clarity. 4 -2...
  • Page 93 (This can be done without disconnecting the harness as illustrated in Figure 4-3.) Replace card cage assembly as follows: STEP 6 Set assembly in unit and slide it back until motherboard connectors protrude through rear panel. Examine harness to make sure it is not pinched. Ampex 1809670-01...

  • Page 94: Coaxial Connector

    TBC-6 COAX CARD CONNECTORS CAGE MOTHERBOARD (EIGHT) • CROSS-RECESSED CHASSIS SCREWS (SIX) Figure 4-3. Card Cage Replaceable Components STEP 7 Start two forward capscrews on bottom of unit. STEP 8 Start four cross-recessed screws at front of assembly and then the remaining capscrews.

  • Page 95: Filter Capacitor

    TBC-6 STEP 1 Remove card cage assembly as described in steps 1 through 5 of paragraph 4-3. STEP 2 Unsolder two leads of connector to be removed. STEP 3 Remove two connector retaining screws and remove connector. Replace coaxial connector as follows:...

  • Page 96: Assembly

    TBC-6 STEP 3 Remove two screws and set power supply between chassis and cage. (See Figure 4-4.) CARD MOTHERBOARD CAGE TRANSFORMER CHASSIS HARNESS ----- ·--- @v,@W,w;,y,q;,;;oWH,,,,:.« ✓, W ?///& ✓,Wk,,,: ,,., .< ////ffe/$//$;//;,Mv/MI'_,� --�-N TERMINAL AC INPUT BLOCKS HARNESS Figure 4-4. Motherboard and Power Supply Replacement...

  • Page 97: Removing And Replacing The Power Supply

    REMOVING AND REPLACING THE POWER SUPPLY 4- 8 REMOVING AND REPLACING THE POWER TRANSFORMER TBC-6 STEP 11 Place power supply in position in chassis with harnesses between power supply and chassis side. STEP 12 Start two screws that secure power supply. Verify that harnesses will not be pinched and then tighten screws.
  • Page 98 TBC-6 STEP 2 Remove power supply as described in steps 1 through 3 of paragraph 4-7. Note Observe arrangement of harnesses between transformer (Refer to Figure 4-4.) and rear comer of chassis. Before replacing trans­ former, these harnesses must be restored to their original position or difficulty will be experienced in positioning the transformer.
  • Page 99 Remove two screws holding switch assembly cover and remove cover. (See Figure 4-5.) STEP 3 Remove two standoffs. Lift switch assembly off studs and disconnect linkage. STEP 4 Disconnect switch assembly harness from terminal block. 4- 8 Ampex 1 8 09670-01...
  • Page 100 TBC-6 Replace ac power switch as follows: STEP 5 Set switch assembly on mounting studs and connect linkage. STEP 6 Replace standoffs finger tight. STEP 7 Tighten standoff. Press and release POWER pushbutton to verify that linkage moves freely. If linkage sticks, loosen standoffs, shift switch assembly position, and repeat this step.

  • Page 102: Supplemental Information

    TBC-6 SECTION 5 SUPPLEMENTAL INFORMATION INTRODUCTION This section contains detailed lists and drawings which supplement the maintenance information and procedures. Selectable Jumper Options Tables 5-1 through 5-4 are lists of individual jumpers and their recommended settings. If a problem is encountered during installation or after maintenance on any PWA, check jumper selection on individual assemblies.
  • Page 103 TBC-6 Table 5-1. Video Input PWA Jumper Locations Jumper Description Position Option Search dropout range On (normal) Factory test RF dropout Normal VPR-20 Test ramp Normal Test ramp H-gate Normal Removed Factory test Vertical Broad pulse (normal) Equalizing pulse (VPR-20 only)
  • Page 105 TBC-6 Table 5-2. Tape Clock PWA Jumper Locations (Continued) Jumper Option Description Position Tape vertical Normal Factory test Color present Normal Factory test Normal Vertical noise 7.8 kHz reset On (normal) On (normal) Write vertical processor Qualify Normal Factory test...
  • Page 106 Option Jumper Description Position TBC-6 Table 5-3. Memory System PWA Jumper Locations (Continued) Normal Read 4Fsc output Factory test Removed Normal Read 4Fsc oscillator Factory test Normal Quadrant offsets Factory test Normal Line-by-line error Factory test Factory test On (normal)
  • Page 107 Factory test Removed DIA output Normal Factory test Composite sync Advanced reference Vertical drive Normal Sync blank Removed Factory test Reference 4Fsc Normal Removed Factory test TBC-6 Table 5-4. Video Output PWA Jumper Locations Jumper Description Position Option Ampex 1809670-01...
  • Page 108 Normal VCO error voltage A-ground +12VA -12VA TBC-6 Test Points Tables 5-5 through 5-8 list test points located on each PW A and give a brief description of the signal at the test point. Table 5-5. Video Input PW A Test Points Table 5-6.
  • Page 109 25 Hz mod H-sync +5VD Quadrature select Table 5-7. Memory System PWA Test Points Read 4Fsc oscillator error voltage -12VA +12VA Cycle clock generator output Next line time base error and Start Read quadrant error +5VD ° Time-base error within 90 Ampex 1809670-01...
  • Page 110 V/32 counting circuit V/2 reset Step left +5VD Ref present TBC-6 Motherboard PWA Table 5-9 is a list of TBC-6 Motherboard PWA signals and their descriptions. Table 5-9. Motherboard PWA Signal Pinouts Signal Analog Ground Power Supply Analog Ground Power Supply...
  • Page 111 J6 RF Input RF Ground J6 RF Input RF Ground Power Supply Analog Ground Power Supply Analog Ground Jl-32 (VTR) Step Forward 2 TBC-6 Table 5-9. Motherboard PWA Signal Pinouts (Continued) Signal Source/PW A (Continued next page) 5-10 Ampex 1809670-01...
  • Page 112 Video Outpu t Analog Ground Power S u p pl Analog Ground Power Suppl Power Suppl 14-19 TBC-6 Table 5 - 9. Motherbo ard PWA Si gn al Pinouts (Continued) Source/PW A Video Output Video Output Video Output} (Continued nex t page...
  • Page 113 TBC-6 Table 5-9. Motherboard PWA Signal Pinouts (Continued) Source/PW A Signal Power Supply -5Vdc Power Supply Analog Ground Power Supply Analog Ground Power Supply Analog Ground Power Supply Analog Ground Power Supply -12 Vdc Power Supply -12 Vdc Power Supply...
  • Page 116 TBC-6 Table 5-10. Video Input PWA Adjustments (Continued) Reference Designation Function 6 MHz LPF adjustment 6-MHz LPF adjustment Color processor LPF filter adjustment Ll 1 Color processor LPF filter adjustment Color processor chroma inverter peaking coil ' Color processor chroma BPF adjustment...
  • Page 117 TBC-6 Table 5-10. Video Input PWA Adjustments (Continued) Reference Designation Function R470 Color processor chroma inverter balance R472 Front panel video input level Color processor LPF adjustment Color processor LPF adjustment 6 MHz LPF adjustment Color processor delay equalizer adjustment Table 5-11.
  • Page 118 R117 R118 R119 TBC-6 Table 5-12. Memory System PW A Adjustments Reference Designation Function Read 4Fsc oscillator frequency DC offset, 4Fsc oscillator error Quadrature error adjust Quadrature error adjust Velocity compensator balance Velocity compensator gain (best blue vector). Line error test (see J4)
  • Page 119 Nonstandard sync/burst phase (J12 B-C) R443 Sync generator advance reference output sync/burst phase R481 TBC video clamp pulse delay R483 TBC video output burst flag delay TBC video low pass filter adjustment TBC-6 Table 5-13. Video Output PWA Adjustments (Continued) 5-18 Ampex 1809670-01...
  • Page 120 INTRODUCTION TBC-6 SECTIDN 6 CDMPDNENT LDCATIDNS This section contains jumper and component location drawings of the four TBC-6 PAL printed wiring assemblies. Component Locations Figures 6-1 through 6-4 illustrate the location of the individual jumpers on each PWA. To find the use of any particular jumper, ref er to the tables in section 5. If a problem is encountered during installation or after maintenance on any PW A, check jumper selection on individual assemblies.
  • Page 122 TBC-1 R119 R19 3 R463 R162 R161 Figure 6- TBC-6 Video Input PW Component Locati<J Ampex 1809670-01...
  • Page 123 TBC-6 TP19 TP41 TP18 J14 R167 TP43 J4 JS TP42 R269 Figure 6-2. TBC-6. Tape Clock PWA, Component Locations Ampex 1809670-01...
  • Page 124 TBC-1 " '" {.l [J) Figure 6 TBC-6 Memory System P-W Component Locatic Ampex 1809670-01...
  • Page 126 Parallel-to-serial converter, 2-24 Memory System PWA, 2-21 Phase comparator alignment , 3-14 Tape Clock PWA, 2-15 Power supply replacement, 4-6 TBC-6, 2-3 Power transformer replacement, 4-6 Video Input PW A, 2-9 Preventive maintenance, 3-1 Video Output PW A, 2-29 Burst level adjustment, 3-11...
  • Page 127 Replacments: TBC-6 block diagram, 2-5 Test equipment, 3-1-3-3 AC power switch, 4-8 Test points, 5-7 Card cage components, 4-1 Fan units, 4-7 Unity gain adjustment, 3-8 Power supply, 4-6 Power transformer, 4-6 VCO controls, 2-12 VCO frequency align m ent, 3 - 14...
  • Page 129 AMPEX PCN30285 Printed in USA...

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