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SOLOMON SYSTECH SSD1623 Manual

96 segments with common 3-level generic display driver cmos
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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a product under development. Solomon Systech reserves the right to change
or discontinue this product without notice.
http://www.solomon-systech.com
SSD1623
Rev 0.10
SSD1623
Product Preview
96 Segments with Common
3-Level Generic Display Driver
CMOS
P1/44
Nov 2007
Copyright  2007 Solomon Systech Limited

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Summary of Contents for SOLOMON SYSTECH SSD1623

  • Page 1 Product Preview 96 Segments with Common 3-Level Generic Display Driver CMOS This document contains information on a product under development. Solomon Systech reserves the right to change or discontinue this product without notice. http://www.solomon-systech.com Copyright  2007 Solomon Systech Limited SSD1623 Rev 0.10...

  • Page 2: Table Of Contents

    DC ELECTRICAL CHARACTERISTICS ................. 31 AC CHARACTERISTICS..................... 33 14.1 ..............................33 ESET TIMING 14.2 ............................34 OWER EQUENCE 14.3 ............................35 OWER DOWN EQUENCE 14.4 DC/DC ..............................36 START UP MCU INTERFACE TIMING....................37 APPLICATION CIRCUIT ....................38 Solomon Systech Nov 2007 P 2/44 Rev 0.10 SSD1623...
  • Page 3 TABLES 3-1: O ...........................5 ABLE RDERING NFORMATION 5-1: SSD1623 ..........................12 ABLE PAD COORDINATES 8-1: R ..............................18 ABLE EGISTER ABLE 11-1: M ............................30 ABLE AXIMUM ATINGS 12-1: DC O ..........................30 ABLE PERATING ATING 13-1: DC C ............................31 ABLE HARACTERISTICS 13-2: T .....................33...
  • Page 4 FIGURES 4-1: SSD1623 B ..........................6 IGURE LOCK IAGRAM 4-2: SSD1623 DC/DC B .........................6 IGURE LOCK IAGRAM 5-1 : SSD1623 ) ....................8 IGURE LAYOUT DIAGRAM AD FACE UP 5-2 : SSD1623V ) ....................9 IGURE PAD LAYOUT IRE BOND CHIP 5-2 : SSD1623V ) ....................10...

  • Page 5: General Description

    GENERAL DESCRIPTION SSD1623 is a CMOS generic display driver with controller. It has 95 segments, 1 background segment and 1 common output. Each segment / common is capable of 3-voltage levels output. SSD1623 is designed for SPI interface with hardware address map setting pin, allowing two SSD1623 connected to same SPI bus, increasing the available number of segments.

  • Page 6: Block Diagram

    VSSA VCTRL DC / DC Controller Command Interface regulator VBAT SI, SO, CLS, CE#, SCLK, Components for booster ADDR_MAP, RES#, SYN, BUSY, VCMP, TPA : SSD1623 DC/DC Block Diagram Figure 4-2 Solomon Systech Nov 2007 P 6/44 Rev 0.10 SSD1623...
  • Page 7 8x Configurations By pass C3AP C3AN VCP3 VCP1 VCP4 6x Configurations By pass By pass C3BP C3BN C3AP C3AN VCP1 VCP4 4x Configurations By pass By pass C3AP C3AN VCP1 VCP4 SSD1623 Rev 0.10 P 7/44 Nov 2007 Solomon Systech...

  • Page 8: Die Pad Floor Plan

    DIE PAD FLOOR PLAN Figure 5-1 : SSD1623 layout diagram (Pad face up) Pad structure C Pad structure A Solomon Systech Nov 2007 P 8/44 Rev 0.10 SSD1623...

  • Page 9: Figure 5-2 : Ssd1623V Pad Layout (Wire Bond Chip )

    Figure 5-2 : SSD1623V- Bare chip pad layout Pad structure Unit in um Pad structure C Pad structure A Pad structure D (No wire bonding) Pad structure B SSD1623 Rev 0.10 P 9/44 Nov 2007 Solomon Systech...

  • Page 10: Figure 5-2 : Ssd1623V Pad Layout (Wire Bond Chip )

    Figure 5-3 : SSD1623Z – Gold bumped chip pad layout Pad structure Unit in um Pad structure C Pad structure A Pad structure B Pad structure D Solomon Systech Rev 0.10 SSD1623 Nov 2007 P 10/44...

  • Page 11: Figure 5-3 : Ssd1623 Alignment Mark

    Figure 5-4 : SSD1623 alignment mark Alignment mark Unit in um SSD1623 Rev 0.10 P 11/44 Nov 2007 Solomon Systech...

  • Page 12: Table 5-1: Ssd1623 Pad Coordinates

    Table 5-1: SSD1623 pad coordinates Pad No Pin Name Pad No Pin Name VCTRL -1959.8 733.3 VBAT -1742.8 -907.0 -1959.8 659.3 -1647.1 -907.0 -1959.8 585.3 C3AP -1551.4 -907.0 SCLK -1959.8 511.3 C3AN -1455.7 -907.0 -1959.8 437.3 C3BP -1360.0 -907.0 BUSY -1959.8...
  • Page 13 937.0 SEG8 -953.1 937.0 SEG7 -1022.1 937.0 SEG6 -1091.1 937.0 SEG5 -1160.1 937.0 SEG4 -1229.1 937.0 SEG3 -1298.1 937.0 SEG2 -1367.1 937.0 SEG1 -1436.1 937.0 SEG0A -1505.1 937.0 COMA -1669.6 937.0 SSD1623 Rev 0.10 P 13/44 Nov 2007 Solomon Systech...
  • Page 14 61um x 41um Alignment Mark: Type Size Coordinate (Centre of marks) + shape 30um x 30um 2001.8, 939.8 + shape 30um x 30um -1942.0, -815.1 pin1 30um x 20um -1920.8, 816.3 Solomon Systech Nov 2007 P 14/44 Rev 0.10 SSD1623...

  • Page 15: Pin Description

    Voltage power pin for segment and common driving Power Voltage power pin for segment and common driving SEG[95:1] Output Segment output SEG0A SEG0B Output Background segment output COM0A COM0B Output Common output pins SSD1623 Rev 0.10 P 15/44 Nov 2007 Solomon Systech...

  • Page 16: Functional Block Description

    IC, then logic zeros will be output on the SO pin for the remainder of the transaction. Field # of bits Content Read / Write Address (IC and register) Dead bit Data / Command Total Solomon Systech Nov 2007 P 16/44 Rev 0.10 SSD1623...

  • Page 17: Figure 7-1: Sample Spi Transfer

    DATA 0 DATA 1 DATA 23 DATA 0 Figure 7-2: Consecutive SPI Transfers Preamble First Address Preamble Another Address 24 Bits Data 24 Bits Data 24 Bits Data 24 Bits Data SSD1623 Rev 0.10 P 17/44 Nov 2007 Solomon Systech...

  • Page 18: Register Table

    SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA Register Table. Table 8-1: Register Table Register Register Name Description Bit23 Bit22 Bit21 Bit20 Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address...

  • Page 19: Command Descriptions

    All common and segment output pins output V1 level 0111 All common and segment output pins output V0 level 1000 All common and segment output pins become HiZ state Others Follow ram data SSD1623 Rev 0.10 P 19/44 Nov 2007 Solomon Systech...
  • Page 20 E_CLK_Div[3:0] Divider for external clock to 32kHz No divide (Default) Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 Solomon Systech SSD1623 Nov 2007 P 20/44 Rev 0.10...
  • Page 21 Lock[1:0] - lock register Normal operations (Default) Normal operations Normal operations Lock stage. Once these lock bits are set, only unlock bit can be set. No other register settings are accepted. SSD1623 Rev 0.10 P 21/44 Nov 2007 Solomon Systech...
  • Page 22 10111 DOFF_out[1:0] - All output segments and commons will be ended at certain level LUT setting Output end level Hi-Z VSS (Default) VTH[2:0]: Set Threshold for battery voltage VTH[2:0] 2.1 (Default) Solomon Systech SSD1623 Nov 2007 P 22/44 Rev 0.10...
  • Page 23 Temperature sensor enables, allow digital output of temperature sensing block. other: Temperature sensor disables. (Default) DCDis[1:0] DC/DC Discharge timing setting 4ms (Default) 16ms VSEN_En VBAT voltage sensor enables. VBAT voltage sensor disables. (Default) SSD1623 Rev 0.10 P 23/44 Nov 2007 Solomon Systech...
  • Page 24 Bypass the stage 4 of charge pump circuit. Normal operation. (Default) Stage2_level Multiple level of the stage 2 of charge pump circuit is x3. Multiple level of the stage 2 of charge pump circuit is x2. (Default) Solomon Systech SSD1623 Nov 2007 P 24/44 Rev 0.10...
  • Page 25 0x43 0x49 0x4E 0x51 0x59 0x60 0x69 0x6F 0x77 0x7B BUSY: Indicates the chip is running waveform update. Please don’t send data and update the chip when the chip is running. SSD1623 Rev 0.10 P 25/44 Nov 2007 Solomon Systech...
  • Page 26 Indicates no waveform update is on-going. Update is allowed when the chip is idle. Solomon Systech SSD1623 Nov 2007 P 26/44 Rev 0.10...
  • Page 27 [1:0] / DHL_V [1:0] / DLL_V [1:0] / C_V [1:0] Output status Hi-Z Tn[5:0] Output waveform duration 000000 - Skip 000001 – 111111 Waveform duration = Base unit times x Tn[5:0] SSD1623 Rev 0.10 P 27/44 Nov 2007 Solomon Systech...

  • Page 28: Figure 9-1: Illustration Of Output Waveform Under Different Phase Behavior Setting

    SEG with Data H to H transition [1:0] DHH_V 2n-1 [1:0] DHL_V SEG with Data H to L transition DHL_V [1:0] 2n-1 DLL_V [1:0] SEG with Data L to L transition DLL_V [1:0] 2n-1 [1:0] [1:0] 2n-1 Solomon Systech SSD1623 Nov 2007 P 28/44 Rev 0.10...

  • Page 29: Output Waveform

    Individual phase can be disabled during update. E.g. • Ph1 > Ph2 > Ph3 > Ph4, disable Ph5 • Ph1 > Ph2 > Ph 4, disable Ph3 and Ph5 • Ph3 > Ph5, disable Ph1, Ph2 and Ph4 Solomon Systech Rev 0.10 SSD1623 Nov 2007 P 29/44...

  • Page 30: Absolute Maximum Ratings

    Table 12-1: DC Operating Rating Symbol Parameter Test Condition Max Unit Supply voltage I/O supply voltage DDIO VCI regulator supply voltage Charge pump power supply Driver supply voltage Driver supply voltage Solomon Systech Nov 2007 P 30/44 Rev 0.10 SSD1623...

  • Page 31: Dc Electrical Characteristics

    V1 output voltage V0=30V, Loading V0/2 x 0.98 V0/2 V0/2 x at V1 = 5nF, 1MΩ 1.02 DIslp_vdd Deep Sleep mode VDDIO = VDD current =2.8V DC/DC off No clock No output load SSD1623 Solomon Systech Rev 0.10 P 31/44 Nov 2007...
  • Page 32 DC/DC on V0=36V Osc on with 32kHz No output load Iop_vci Operating current VDDIO = VDD =2.8V VCI=2.8V DC/DC on V0=36V Osc on with 32kHz VCOM / VSEG all tie to V1 Solomon Systech Nov 2007 P 32/44 Rev 0.10 SSD1623...

  • Page 33: Ac Characteristics

    Table 14-1: Reset Timing Characteristics (Unless otherwise specified, Voltage Referenced to V = 2.8V, V =2.8V) DDIO Symbol Parameter Unit Reset pulse width Reset completion time Complete Figure 14-1: Reset timing diagram complete RES# SSD1623 Solomon Systech Rev 0.10 P 33/44 Nov 2007...

  • Page 34: Power Up Sequence

    Note: In all cases, VDDIO and VCI (or VBAT) power up sequence should not have any impact on the driver/ display functionalities/ performance. Figure 14-2: Power up timing diagram V or V VDDIO/ VDD RES# (32KHz) SCLK Solomon Systech Nov 2007 P 34/44 Rev 0.10 SSD1623...

  • Page 35: Power Down Sequence

    Note: The IC performs DC/DC discharge on all high voltages during abnormal power supply removal to avoid any functional corruption upon next power up. Figure 14-3: Power down timing diagram or V VDDIO/ VDD RES# PDOWN (32KHz) SCLK SSD1623 Solomon Systech Rev 0.10 P 35/44 Nov 2007...

  • Page 36: Dc/Dc Start Up

    Panel Loading = 5nF Symbol Characteristic Min. Typ. Units DC/DC Start up transient VCIpeak current peak Start up settling time DCrs 90% of 36V DC/DC Figure 14-4: Typical DC/DC start up profile DCrs VCIpeak Solomon Systech Nov 2007 P 36/44 Rev 0.10 SSD1623...

  • Page 37: Mcu Interface Timing

    Time SO will remain stable after the falling edge of SCLK SOHLD (1) Equivalent to a maximum clock frequency of 26MHz. Figure 15-1: SPI Timing Diagram CKPER CEHIGH CKHIGH CEHLD CESU CKLOW SCLK SISU SIHLD SOSU SOHLD SSD1623 Solomon Systech Rev 0.10 P 37/44 Nov 2007...

  • Page 38: Application Circuit

    16 APPLICATION CIRCUIT Figure 16-1: Typical application diagram for 16x DCDC DISPLAY PANEL VDDA C3AP VDDIO C3AN VSSA C3BP C3BN VSSC SSD1623 VBAT VCP1 VCP1 VCP2 VCP3 VCP4 Ext 32kHz Solomon Systech Nov 2007 P 38/44 Rev 0.10 SSD1623...

  • Page 39: Figure 16-2: Typical Application Diagram For 12 Xdcdc

    Figure 16-2: Typical application diagram for 12x DCDC DISPLAY PANEL VDDA C3AP VDDIO C3AN VSSA C3BP VSSC C3BN SSD1623 VBAT VCP1 VCP1 VCP2 VCP3 VCP4 Ext 32kHz SSD1623 Solomon Systech Rev 0.10 P 39/44 Nov 2007...

  • Page 40: Figure 16-3: Typical Application Diagram For 8 Xdcdc

    Figure 16-3: Typical application diagram for 8x DCDC DISPLAY PANEL VDDA C3AP VDDIO C3AN VSSA C3BP VSSC C3BN SSD1623 VBAT VCP1 VCP1 VCP2 VCP3 VCP4 Ext 32kHz Solomon Systech Nov 2007 P 40/44 Rev 0.10 SSD1623...

  • Page 41: Figure 16-4: Typical Application Diagram For 6 Xdcdc

    Figure 16-4: Typical application diagram for 6x DCDC DISPLAY PANEL VDDA C3AP VDDIO C3AN VSSA C3BP VSSC C3BN SSD1623 VBAT VCP1 VCP1 VCP2 VCP3 VCP4 Ext 32kHz SSD1623 Solomon Systech Rev 0.10 P 41/44 Nov 2007...

  • Page 42: Figure 16-5: Typical Application Diagram For 4 Xdcdc

    Figure 16-5: Typical application diagram for 4x DCDC DISPLAY PANEL VDDA C3AP VDDIO C3AN VSSA C3BP C3BN VSSC SSD1623 VBAT VCP1 VCP1 VCP2 VCP3 VCP4 Ext 32kHz Solomon Systech Nov 2007 P 42/44 Rev 0.10 SSD1623...

  • Page 43: Table 16-1: Reference Capacitor Value

    Table 16-1: Reference Capacitor Value Part reference Value (uF) Min Rating 0.22 0.22 0.22 0.22 0.22 0.22 0.22 0.22 0.22 0.22 • Capacitor values requirement depends on panel loading and voltage setting. SSD1623 Solomon Systech Rev 0.10 P 43/44 Nov 2007...
  • Page 44 “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not con- vey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.

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