Qorvo ACT43750EVK2 User Manual

Evaluation kit

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USER'S GUIDE
ACT43750EVK2 User's Guide
Description
This document describes the characteristics and operation of the Qorvo ACT43750EVK2 evaluation kit (EVK). It provides setup and
operation instructions, schematic, layout, BOM, GUI, and test data. This EVK ships as a standalone board that can be evaluated
independently or with a GaN RF FET. The EVK is used for Qorvo's QPD1004 GaN RF FET, but can be easily modified for other GaN
FETs.
The ACT43750 is an integrated power solution that controls GaN RF FETs: Negative gate voltage, properly sequenced turn on and turn
off, automatic gate voltage/drain current calibration, and drain voltage switching. It is an ideal solution for radio frequency (RF) power
amplifiers (PAs) that demand fast transient, high current pulsed loads.
Features
Qorvo recommends that the user evaluate the EVK functionality with an RF PA and with the EVK connected to a PC running the
graphical user interface (GUI) software. The GUI allows the user to enable/disable the outputs and to customize the exact voltage and
current requirements for any specific RF PA being tested. The user can use the ACT43750 GUI to set the RF PA Idq bias current
requirement, and the EVK autonomously finds and stores the optimal gate voltage for the Idq bias current. After finding the optimal gate
bias voltage, the user can apply an RF signal to test the RF PA functionality.
Figure 1. ACT43750EVK2 Board
March 2023 Rev 1.0 | Subject to change without notice
1 of 30
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Summary of Contents for Qorvo ACT43750EVK2

  • Page 1 BOM, GUI, and test data. This EVK ships as a standalone board that can be evaluated independently or with a GaN RF FET. The EVK is used for Qorvo’s QPD1004 GaN RF FET, but can be easily modified for other GaN FETs.
  • Page 2: Hardware Setup

    ACT43750EVK2 Board Overview The ACT43750EVK2 generates the negative gate voltage required to drive a GaN FET RF PA. It generates this voltage from the 12V input bias voltage. It also provides the proper turn-on and turn-off sequencing between the gate and drain voltages. When Vg is commanded to turn on, the gate voltage will be -4.5V (default).
  • Page 3 USER’S GUIDE Figure 2. ACT43750EVK2 SET-UP Figure 3. ACT43750EVK2 + QPD1004EVK SET-UP March 2023 Rev 1.0 | Subject to change without notice 3 of 30 www.qorvo.com...
  • Page 4: Quick Start

    4. Open the J14 (ENG) 5. Connect the Qorvo USB-TO-I2C dongle cable to J11. The black wire connects to the AGND pin. 6. Optional: Connect a PWM generator to the J13 (ENTX) pin to AGND. The voltage level must be from 0V to 5V. Make sure the PWM generator is turned off.
  • Page 5 Confirm the drain voltage is zero Note: “ Enable Vdrain” function is only for continuous operation. For pulse operation, Apply PWM pulse to ENTX pin. Don’t push this button. March 2023 Rev 1.0 | Subject to change without notice 5 of 30 www.qorvo.com...
  • Page 6: Recommended Operating Conditions

    Table 1. Recommended Operating Conditions for ACT43750 Parameter Description Unit Vdrain Drain voltage Idrain Drain current Frequency Drain pulsed frequency V12V 12V DC bias 10.8 13.2 PWM On-Time µs Duty ratio March 2023 Rev 1.0 | Subject to change without notice 6 of 30 www.qorvo.com...
  • Page 7 8. auto-calibration should be done after steps 1-4 if testing with RF Power. The gate voltage will increase to around negative 2.5V at bias current 50mA for QPD1004. If the bias current is much higher than the target due to the RFPA March 2023 Rev 1.0 | Subject to change without notice 7 of 30 www.qorvo.com...
  • Page 8 4. Power off 12V DC power supply QPD1004EVB and ACT43750EVK2 System Test RFPA QPD1004 is used as a load of ACT43750EVK2. Note 1: Calibration resistor change is necessary for certain RFPA dc bias current. Please refer to App Note 2.
  • Page 9 4. Measure VG to confirm it’s -4.5V. 5. Power off the 50V voltage source 6. Wait for 2 seconds to discharge the drain voltage. 7. Turn off the 12V bias supply March 2023 Rev 1.0 | Subject to change without notice 9 of 30 www.qorvo.com...
  • Page 10: Test Results

    USER’S GUIDE Test Results Test condition, Input voltage=50V, Bias voltage=12V, Resistor load March 2023 Rev 1.0 | Subject to change without notice 10 of 30 www.qorvo.com...
  • Page 11 USER’S GUIDE Test condition, Input voltage=50V, Bias voltage=12V, RFPA QPD1004 March 2023 Rev 1.0 | Subject to change without notice 11 of 30 www.qorvo.com...
  • Page 12 AGND ActiveCiPS Connector PT16 GPIO PT3 ENTX2 PT31 PT32 ENTX ENTX2 XINT ENCAL AGND XINT 100k ACT43750EVK2 100k 100k AGND AGND AGND Figure 6. Schematic ACT43750EVK2 March 2023 Rev 1.0 | Subject to change without notice 12 of 30 www.qorvo.com...
  • Page 13 USER’S GUIDE Layout Figure 7. Assembly Top Layer March 2023 Rev 1.0 | Subject to change without notice 13 of 30 www.qorvo.com...
  • Page 14 USER’S GUIDE Figure 8. Top Layer Silk Screen March 2023 Rev 1.0 | Subject to change without notice 14 of 30 www.qorvo.com...
  • Page 15 USER’S GUIDE Figure 9. Layout Top Layer March 2023 Rev 1.0 | Subject to change without notice 15 of 30 www.qorvo.com...
  • Page 16 USER’S GUIDE Figure 10. Layer 2 – GND Plane March 2023 Rev 1.0 | Subject to change without notice 16 of 30 www.qorvo.com...
  • Page 17 USER’S GUIDE Figure 11. Layer 3 - GND Plane March 2023 Rev 1.0 | Subject to change without notice 17 of 30 www.qorvo.com...
  • Page 18 USER’S GUIDE Figure 12. Layout Bottom Layer March 2023 Rev 1.0 | Subject to change without notice 18 of 30 www.qorvo.com...
  • Page 19: Bill Of Materials

    USER’S GUIDE Bill of Materials ACT43750EVK2 BOM Descriptio Designat Footprint Manufactu Part Number Value Comme Capacitor, C1, C10, Nichicon PCV1K220MCL1GS 22uF/80V Prefer Aluminum C11, C12 Cap_PCV_10x or WE or 875076161003 12.7 Capacitor, C0603_H Standard Standard Ceramic, Capacitor, WCAP- 860130673002 22uF/50V Aluminum ATG5_6.3x11x...
  • Page 20 2.54, Male, 2P Unshroude J12, J13, 2.54, Male, 2P Header, con,hdr,254-4p Wurth 61300411121 2.54, Male, 4P Unshroude 2.54, Male, 4P Inductor, L25xx_MAPI_ Murata DFE252010F- 6.8uH/1.1A Electronic 6R8M=P2 March 2023 Rev 1.0 | Subject to change without notice 20 of 30 www.qorvo.com...
  • Page 21 33R00ELF Resistor, R0805_H Standard Standard Resistor, R0805_H Standard Standard 100R Resistor, R15, R17 R0805_H Standard Standard Resistor, R12, R13 R0805_H Standard Standard Resistor, R0603_H Standard Standard March 2023 Rev 1.0 | Subject to change without notice 21 of 30 www.qorvo.com...
  • Page 22 Standard 100k R26, R28, Resistor, R27, R32 R0603_H Standard Standard Resistor, R29, R0603_H Standard Standard R30, R31 PCB-0354-01 Standard Standard PCB-0354-01 HP34_QFN37- Qorvo ACT43750-101 ACT43750-101 ACT43750 March 2023 Rev 1.0 | Subject to change without notice 22 of 30 www.qorvo.com...
  • Page 23: Gui Installation

    USER’S GUIDE GUI Installation 1. Get GUI files from the Qorvo 2. Plug the Qorvo dongle USB-TO-I C cable into a free USB port. 3. The USB driver will be automatically installed. 4. Double click on the ACT43750 Customer GUI Rev0.5.exe to start the ACT43750EVK.
  • Page 24 For example, the frequency is 20KHz, P=2.5w. R10 must be larger size and higher power. It’s recommended to stack 2pc 66ohm 2512 size resistor (4w) replace the original resistor. March 2023 Rev 1.0 | Subject to change without notice 24 of 30 www.qorvo.com...
  • Page 25 ID – RF PA drain current, unit A. R1 – Current limit resistance, unit mΩ. Please refer to the schematics and layout for resistor connection and location. March 2023 Rev 1.0 | Subject to change without notice 25 of 30 www.qorvo.com...
  • Page 26 To reduce falling switching time, R12 and R13 should have smaller resistance value. To increase falling switching time, R12 and R13 should be larger resistance value. Please refer to schematics and layout for resistor connection and location. March 2023 Rev 1.0 | Subject to change without notice 26 of 30 www.qorvo.com...
  • Page 27 Dongle connector GND is aligned with the AGND pin of J11 as shown in Figure 3. GUI PWM function is available. Figure 3. Old dongle connection at J11 Dongle is “Qorvo Rev2.0”, which works with ACT43750 Customer GUI Rev0.5 Version 1 Dongle connector on PCB needs flip 180 deg.
  • Page 28 The rise time depends on the gate resistance R11. The default gate resistance R11=10Ω. The rise time is 10ns. The R11=100Ω, the rise time is 100ns. March 2023 Rev 1.0 | Subject to change without notice 28 of 30 www.qorvo.com...
  • Page 29 1. RF PA input signal is off. 2. Pull ENTX pin to logic low. 3. Turn off the drain power supply 4. Turn off the 12V bias voltage. March 2023 Rev 1.0 | Subject to change without notice 29 of 30 www.qorvo.com...
  • Page 30: Contact Information

    Data Sheet Information is suitable for use in a particular application. © 2020 Qorvo US, Inc. All rights reserved. This document is subject to copyright laws in various jurisdictions worldwide and may not be reproduced or distributed, in whole or in part, without the express written consent of Qorvo US, Inc.

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