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Aplex AVS-320-NP User Manual

Machine vision control, intel elkhart lake processor
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AVS-320
Machine Vision Control
Intel Elkhart Lake Processor
User's Manual
Version：1.10（20240820）
This publication, including all photographs, illustrations and software, is protected under international
copyright laws, with all rights reserved. Neither this manual, nor any of the material contained herein,
may be reproduced without written consent of the author.
All rights are reserved by Aplex Technology Inc.
The information in this document is subject to change
without notice. Please refer to your vendor for the latest information.

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Summary of Contents for Aplex AVS-320-NP

  • Page 1 Neither this manual, nor any of the material contained herein, may be reproduced without written consent of the author. All rights are reserved by Aplex Technology Inc. The information in this document is subject to change...

  • Page 2: Table Of Contents

    Contents CONTENTS ......................... 2 1 PACKING LIST ..........................4 2 DISCLAIMER ........................... 4 3 TRADEMARKS ..........................4 4 SAFETY NOTICES .......................... 4 5 INTRODUCTION ..........................5 5.1 SPECIFICATIONS ........................5 5.2 DIMENSIONS .......................... 7 5.3 JUMPERS AND CONNECTORS LOCATION ................. 9 5.4 JUMPERS SETTING AND CONNECTORS ................
  • Page 3 22. SATA-P2(OPTION) ....................... 16 23. SATA2(OPTION) ......................16 24. M2_M1 .......................... 16 25. H6 ..........................16 26. M2_B1........................... 16 27. H7 ..........................17 28. SIM1 ..........................17 29. GPIO(GPIO1) ....................... 17 30. PWR/HDD LED (LED5) ....................18 31. LED1,LED2,LED3,LED4,LED6,LED7,LED_M1,LED_B1..........18 32.

  • Page 4: Packing List

    The information in this document is subject to change without further notice. Please refer to your vendor for the latest information. In no event shall Aplex Technology Inc. be liable for hidden defects or damages of any kind, whether consequential or incidental, arising from improper use or installation of the product.

  • Page 5: Introduction

    5 Introduction AVS-320 is a Non-standard motherboard developed on the basis of Intel Elkhart Lake,which provides abundant peripheral interfaces to meet the needs of different customers.Also,it features one GbE port,two PoE Ports, 2-COM ports,4-Uart and one M.2 M-Key and one M.2 B-Key configuration.
  • Page 6 GPIO PH3.50mm,2x5 Pin Phoenix connector 4x DI 4x DO Battery Support CR2477 Li battery by 2-pin header (1000mAh) 1x SIM Card Holder by SIM1 Watchdog Timer Software programmable 1–255 levels ® Support Intel Power 1x 3-pin power input connector (DC24V) Management Switches and Power on/off switch by BT1...

  • Page 7: Dimensions

    5.2 Dimensions Mechanism Dimension: - 7 -...
  • Page 8 Main board Dimension: (units :mm) - 8 -...

  • Page 9: Jumpers And Connectors Location

    5.3 Jumpers and Connectors Location Board Top Board Bottom - 9 -...

  • Page 10: Jumpers Setting And Connectors

    5.4 Jumpers Setting and Connectors 1. CPU1: (FCBGA1493), onboard Intel Elkhart Lake Processors. Processor Model Number Cores/ Remarks Threads AVS-320-J6413-XX J6413 1.8~3.0GHz 4 / 4 AVS-320-J6412-XX J6412 2.0~2.6GHz 4 / 4 2. H1/H2/H3/H4(CPU SCREW HOLES): CPU FAN SCREW HOLES, Four screw holes for fixed CPU Cooler assemble. 3.

  • Page 11: Sw1

    6. SW1: (Switch), Auto Power on and PSE jumper setting. Mode Pin1 on Auto Power on (Default) Pin1 off Power button on (option) Pin4 on Disable PSE (option) Pin4 off Enable PSE (Default) Pin5 on Pin5 off Default Pin6 on Pin6 off Default CMOS clear swich, CMOS clear operation will permanently reset old BIOS settings to...

  • Page 12: Hdmi(Hdmi1)

    Pin3 8. BT1/P_SW1(option): Power on/off button, They are used to connect power switch button. The two pins are disconnected under normal condition. You may short them temporarily to realize system startup & shutdown or awaken the system from sleep state. Model P_SW1 ●...

  • Page 13: Jp2(Option)

    Pin# Signal Name DCD# (Data Carrier Detect) RXD (Received Data) TXD (Transmit Data) DTR (Data Terminal Ready) Ground DSR (Data Set Ready) RTS (Request To Send) CTS (Clear To Send) JP1 select Setting (RI/5V/12V) BIOS Setup：Serial Port 1 Configuration【RS-232】 RS422 (option): Pin# Signal Name 422_TX-...

  • Page 14: Com2(Com_2,Option)

    Close 3-4 COM2 Pin9 = +5V/1A (option) Close 5-6 COM2 Pin9 = +12V/1A (option) 14. COM2(COM_2,option): (Type DB9M),Serial port,standard DB9 Male serial port is provided to make a direct connection to serial devices. COM2 port is controlled by pins No.1~6 of JP2,select output Signal RI or 5V or 12V,For details, please refer to description of JP2 setting.

  • Page 15: Usb_9

    full-speed and low-speed signaling. Each USB Type A Receptacle (2 Ports) Current limited value is 2.0A. If the external USB device current exceeds 2.0A, please separate connectors into different Receptacle. 17. USB_9 (option) USB2_9： (Single USB typeA),I/O USB 2.0 connector, it provides up to 1 USB2.0 port,USB 2.0 allows data transfers up to 480Mb/s,support USB2.0 and full-speed and low-speed signaling.

  • Page 16: Poe(Lan3)

    21. PoE(LAN3) (RJ45 Connector),Gigabit PoE plus port by RJ45 with intel I210AT Controller, PoE standard IEEE 802.3af/at Power over Ethernet/PSE, PoE power supply type end-span, PoE power output per port max. 25.5 watts. 22. SATA_P2(option): (2.5mm Pitch 1x2 Wafer Pin Header), One onboard 5V output connectors are reserved to provide power for SATA devices.

  • Page 17: Sim1

    27. H7，M2.B1.G3: M2_B1 SCREW HOLES, H7 or M2.B1.G3 for M2_B1 card assemble. The height can be adjusted according to the equipment. M2_B1 Card size H7/ M2.B1.G3 (high) Remarks 3042 H7=6.45mm M2.B1.G3=2.45mm 3052 M2.B1.G3=6.45mm H7=2.45mm 28. SIM1: (NANO-SIM Socket), Support nano SIM Card devices. Pin# Signal Name M2B_UIM_VDD...

  • Page 18: Pwr/Hdd Led(Led5)

    GPIO_IN2 F75111_GPIO_26 GPIO_IN3 F75111_GPIO_25 GPIO_IN4 F75111_GPIO_24 GPIO_OUT1 F75111_GPIO_23 GPIO_OUT2 F75111_GPIO_22 GPIO_OUT3 F75111_GPIO_21 GPIO_OUT4 F75111_GPIO_20 30. PWR/HDD LED(LED5) PWR LED: Green LED for Motherboard Standby Power Good status. HDD LED: Yellow LED for M.2 M-Key status. 31. LED1,LED2,LED3,LED4,LED6,LED7,LED_M1,LED_B1 LED1 STATUS. Green LED for Motherboard PSE Power status. LED2 STATUS.

  • Page 19: Debug2(Option)

    system reset. Pin9-10: BUZZER, They are used to connect buzzer. Note: When connecting LEDs and buzzer, pay special attention to the signal polarity. Make sure that the connector pins have a one-to-one correspondence with chassis wiring, or it may cause boot up failure. 34.
  • Page 20 CRT_RED(NC) Ground CRT_GREEN(NC) Ground CRT_BLUE(NC) Ground CRT_H_SYNC CRT_DDCDATA CRT_V_SYNC CRT_DDCCLK USB16 (USB2.0 Signal): Signal Name Pin# Pin# Signal Name 5V_S5 5V_S5 USB1_N USB6_N USB1_P USB6_N Ground Ground PM_PCIE_WAKE- FP_RESET- PCIE1(PCIE X1 Signal): Signal Name Pin# Pin# Signal Name PE5_TX_P0 PE5 _TX_N0 Ground PE5_RX_P0 PLT_RST_BUF2-...

  • Page 21: Jp3(Option)

    UART6(UART Signal): Signal Name Pin# Pin# Signal Name GP67_DCD6- GP27_RXD6 GP32_TXD6 GP16_DTR6- Ground GP47_DSR6- GP50_RTS6- GP33_CTS6- GP15_RI6- 5V_S0 36. JP3(NC): (2.54mm Pitch 1x2 Pin Header),DC24V power input setting. Power Adapter input (DC_IN1) Open DC24V input, Default Short 37. JTAG1(option): (2.0mm Pitch 2x5 Pin Header), Joint Test Action Group port.

  • Page 22: Bios Setup Description

    6 BIOS Setup Description 6.1 Operations after POST Screen After CMOS discharge or BIOS flashing operation,.Press [Delete] key to enter CMOS Setup. After optimizing and exiting CMOS Setup Press F11 to load default values and continue 0085 6.2 BIOS SETUP UTILITY Press [Delete] key to enter BIOS Setup utility during POST, and then a main menu containing system summary information will appear.

  • Page 23: Main Settings

    6.3 Main Settings Aptio Setup - AMI Main Advanced Chipset Security Boot Save & Exit BIOS Information Choose the system default Project Version 7126A005 language Build Date and Time 11/18/2022 09:05:50 Compute Die Information Name ElkhartLake ULX Type Intel Atom(R) Celeron(R) Processor @ 1.80GHz Speed 1800MHz...

  • Page 24: Advanced Settings

    Advanced Settings Aptio Setup - AMI Main Advanced Chipset Security Boot Save & Exit System ACPI Parameters. ►CPU Configuration ►Power & Performance ►Thermal Configuration ►Trusted Computing ►ACPI Settings ►Super IO Configuration ►Hardware Monitor ►Acoustic Management Configuration ►AMI Graphic Output Protocol Policy ►Network Stack Configuration ►NVMe Configuration ►Intel(R) I210 Gigabit Network Connection –...
  • Page 25 CPU Flex Ratio Override: [Disabled] [Enabled] CPU Flex Ratio Settings Hardware Prefetcher: [Disabled] [Enabled] Intel (VNX) Virtualization Technology: [Disabled] [Enabled] PECI: [Disabled] [Enabled] Active Processor Cores: [ALL] BIST: [Disabled] [Enabled] AP threads Idle Manner: [HALT Loop] [MWAIT Loop] [RUN Loop] AES: [Disabled] [Enabled]...
  • Page 26 [Enabled] #AC Split Lock: [Enabled] [Disabled] 6.4.2 Power & Performance Power & Performance CPU – Power Management Control CPU – Power Management Control P0 Fused Max Core Ratio P1 Fused Max Core Ratio P2 Fused Max Core Ratio P3 Fused Max Core Ratio Boot performance mode: [Max Battery] [Max Non-Turbo Performance]...
  • Page 27 Max Turbo Power Limit 4095.875 Min Turbo Power Limit Package TDP Limit 10.0 Power Limit 1 10.0 Power Limit 2 20.0 1-core Turbo Ratio 2- core Turbo Ratio 3- core Turbo Ratio 4- core Turbo Ratio Energy Efficient P-state: [Disabled] [Enabled] Package Power Limit MSR Lock: [Disabled]...
  • Page 28 VccIn VR Domain Disable Fast PKG C State Ramp for VccIn Domain: [FALSE] [TRUE] Slow Slew Rate for VccIn Domain: [Fast/2] [Fast/4] [Fast/8] [Fast/16] VccIn VR Settings VccIn VR Domain VR Config Enable: [Disabled] [Enabled] AC Loadline DC Loadline PS Current Threshold1 PS Current Threshold2 PS Current Threshold3 PS3 Enable:...
  • Page 29 [Enabled] RFI Settings RFI Domain RFI Current Frequency 140.400MHz RFI Frequency RFI Spread Spectrum Platform PL1 Enable: [Disabled] [Enabled] Platform PL1 Power Platform PL1 Time window Platform PL2 Enable: [Disabled] [Enabled] Power Limit 4 Override: [Disabled] [Enabled] C states: [Disabled] [Enabled] Enhanced C-states: [Disabled]...
  • Page 30 C8 Latency Control(MSR 0x633) Time Unit [1024 ns] Latency C9 Latency Control(MSR 0x634) Time Unit [1024 ns] Latency C10 Latency Control(MSR 0x635) Time Unit [1024 ns] Latency Thermal Monitor: [Disabled] [Enabled] Interrupt Redirection Mode Selection: [Fixed Priority] [Round robin] [Hash Vector] [No Change] Timed MWAIT: [Disabled]...
  • Page 31 [200Mhz] [250Mhz]] [300Mhz] [350Mhz] [400Mhz] [450Mhz] [500Mhz] [550Mhz] [600Mhz] [650Mhz] [700Mhz] [750Mhz] [800Mhz] [850Mhz] [900Mhz] [950Mhz] [1000Mhz] [1050Mhz] [1100Mhz] [1150Mhz] [1200Mhz] Disable Turbo GT frequency: [Enabled] [Disabled] 6.4.3 Thermal Configuration Thermal Configuration Enable All Thermal Funcations: [Disabled] [Enabled] CPU Thermal Configuration Cpu Thermal Configuration DTS SMM: [Disabled]...
  • Page 32 [750 ms] [1 sec] [2 sec] [3 sec] [4 sec] [5 sec] [6 sec] [7 sec] [8 sec] [10 sec] [12 sec] [14 sec] [16 sec] [20 sec] [24 sec] [28 sec] [32 sec] [40 sec] [48 sec] [56 sec] [64 sec] [80 sec] [96 sec]...
  • Page 33 PROCHOT Response: [Disabled] [Enabled] PROCHOT Lock: [Disabled] [Enabled] ACPI T-States: [Disabled] [Enabled] Platform Thermal Configuration Platform Thermal Configuration Critical Trip Point: [15 C] [23 C] [31 C] [39 C] [47 C] [55 C] [63 C] [71 C] [79 C] [87 C] [95 C] [100 C] [103 C]...
  • Page 34 Active Trip Point 0 Fan Speed: Active Trip Point 1: [Disabled] [15 C] [23 C] [31 C] [39 C] [47 C] [55 C] [63 C] [71 C] [79 C] [87 C] [95 C] [103 C] [111C] [119 C (POR)] Active Trip Point 1 Fan Speed: Passive Trip Point : [Disabled] [15 C]...
  • Page 35 [Enabled] PCH Temp Read: [Disabled] [Enabled] CPU Energy Read: [Disabled] [Enabled] CPU Temp Read: [Disabled] [Enabled] Alert Enable Lock: [Disabled] [Enabled] CPU Temp CPU Fan Speed DPTF Configuration DPTF Configuration Hardware Health Monitor Hardware Health Monitor Thermal Sensor 1 Temp 0.0 C Thermal Sensor 2 Temp 0.0 C...
  • Page 36 6.4.6 Super IO Configuration Super IO Configuration Super IO Chip IT8786 Serial Port 1 Configuration Serial Port 1 Configuration Serial Port: [Disabled] [Enabled] Device Settings IO=3F8h; IRQ=4; Change Settings: [Auto] [IO=3F8h; IRQ=4] [IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12;] [IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12;] [IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12;] [IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12;] COM1 Config: [RS232 mode] [RS485 mode]...
  • Page 37 Smart Fan Function Fan 1 Setting Fan 1 Setting Smart Fan 1 Mode: [Software Mode] [Automatic Mode] Fan 1 Type: [PWM] [RPM] Tempurature select: [TMPIN1] [TMPIN2] [TMPIN3] Fan off temperature limit: Fan start temperature limit: Fan full speed temperature limit: Fan start PWM: PWM SLOPE SETTING: Temperature:...
  • Page 38 [100 Mbps Half] [100 Mbps Full] Wake On LAN: [Disabled] [Enabled] Blink LEDS UEFI Driver Intel(R) PRO/1000 9.1.12 PCI-E Adapter PBA 000300-000 Device Name Intel(R) I210 Gigabit Network Connection Chip Type Intel i210 PCI Device ID 1533 PCI Address 01:00:00 Link Status [Disconnected] MAC Address...
  • Page 39 MAC Address 7C:CB:E2:E4:7F:5D Virtual MAC Address 00:00:00:00:00:00 6.4.14 Intel(R) I210 Gigabit Network Connection – 7C:CB:E2:E4:7F:5E NIC Configuration Link Speed: [Auto Negotiated] [10 Mbps Half] [10 Mbps Full] [100 Mbps Half] [100 Mbps Full] Wake On LAN: [Disabled] [Enabled] Blink LEDS UEFI Driver Intel(R) PRO/1000 9.1.12 PCI-E...

  • Page 40: Chipset Settings

    Chipset Settings Aptio Setup - AMI Main Advanced Chipset Security Boot Save & Exit ►System Agent (SA) Configuration System Agent (SA) ►PCH-IO Configuration Parameters →←: Select Screen ↑↓ : Select Item Enter: Select +/- : Charge Opt. F1 : General Help F2: Previous Values F3:Optimized Defaults F4:Save and Exit...
  • Page 41 [Enabled] SelfRefresh IdleTimer: Throttler CKEMin Defeature: [Enabled] [Disabled] Throttler CKKEMin Timer: For LPDDR Only: Throttler CKEMin Defeature: [Enabled] [Disabled] For LPDDR Only: Throttler CKEMin Timer: 64 Dram Power Meter Dram Power Meter Use user provided power weights, Sacle factor, and channel power Floor values: [Disabled] [Enabled]...
  • Page 42 Memory Thermal Reporting Extern Therm Status: [Disabled] [Enabled] Closed Loop Therm Manage: [Disabled] [Enabled] Open Loop Therm Manage: [Disabled] [Enabled] Thermal Threshold Settings Warm Threshold Ch0 Dimm0 Warm Threshold Ch0 Dimm1 Hot Threshold Ch0 Dimm0 Hot Threshold Ch0 Dimm1 Warm Threshold Ch1 Dimm0 Warm Threshold Ch1 Dimm1 Hot Threshold Ch1 Dimm0 Hot Threshold Ch1 Dimm1...
  • Page 43 RAPL PL 1 Power RAPL PL 1 WindowX RAPL PL 1 WindowY RAPL PL 2 enable: [Disabled] [Enabled] RAPL PL 2 Power RAPL PL 2 WindowX RAPL PL 2 WindowY Memory Thermal Management: [Disabled] [Enabled] Memory Training Algorithms: Early Command Training: [Disabled] [Enabled] SenseAmp Offset Training:...
  • Page 44 [Enabled] Read Timing Centering 1D: [Disabled] [Enabled] Dimm ODT Trainning* : [Disabled] [Enabled] Max RTT_WR: [ODT Off] [120 0hms] DIMM RON Training*: [Disabled] [Enabled] Write Drive Strength/Equalization 2D*: [Disabled] [Enabled] Write Slew Rate Training*: [Disabled] [Enabled] Read ODT Training*: [Disabled] [Enabled] Read Equalization Training*: [Disabled]...
  • Page 45 Round Trip Latency: [Disabled] [Enabled] Turn Around Timing Training: [Disabled] [Enabled] Rank Margin Tool: [Disabled] [Enabled] Rank Margin Tool Per Bit: [Disabled] [Enabled] Margin Check Limit: [Disabled] [L1] [L2] [Both] Margin Limit Check L2: Memory Test: [Disabled] [Enabled] DIMM SPD Alias Test: [Disabled] [Enabled] Receive Enable Centering 1D:...
  • Page 46 [Disabled] [Enabled] Read Voltage Centering 1D: [Disabled] [Enabled] Write TC0 Comp Training: [Disabled] [Enabled] Clock TC0 Comp Training: [Disabled] [Enabled] Dimm ODT CA Training: [Disabled] [Enabled] Write TC0 DqsTraining: [Disabled] [Enabled] Duty Cycle Correction: [Disabled] [Enabled] DQ DFE Training: [Disabled] [Enabled] Sense Amplifier Correction Training: [Disabled]...
  • Page 47 [Enabled] Safe Mode Support: [Disabled] [Enabled] Maximum Memory Frequency: [Auto] [1067] [1200] [1333] [1400] [1600] [1800] [1867] [2000] [2133] [2200] [2400] [2600] [2667] [2800] [2933] [3000] [3200] [3467] [3600] [3733] [4000] [4200] [4267] HOB Buffer Size: [Auto] [1B] [1KB] [Max (assuming 63KB total HOB size)] Max TOLUD: [Dynamic] [1 GB]...
  • Page 48 [Fixed Mid] [Fixed High] [Enabled] DDR Speed Control: [Auto] [Manual] Retrain on Fast Fail: [Disabled] [Enabled] DDR4_1DPC: [Disabled] [Enabled on DIMM0 only] [Enabled on DIMM1 only] [Enabled] Enable RH Prevention: [Disabled] [Enabled] REFRESH_PANIC_WM: REFRESH_HP_WM: Exit On Failure (MRC): [Disabled] [Enabled] Enable/Disable IED (Intel Enhanced Debug): [Enabled]...
  • Page 49 [Auto] [No Power Down] [APD] [PPD-DLLoff] Page Close Idle Timeout: [Enabled] [Disabled] Memory Scrambler: [Disabled] [Enabled] Force ColdReset: [Enabled] [Disabled] Channel 0 DIMM Control: [Enable both DIMMs] [Disable DIMM0] [Disable DIMM1] [Disable both DIMMs] Channel 1 DIMM Control: [Enable both DIMMs] [Disable DIMM0] [Disable DIMM1] [Disable both DIMMs]...
  • Page 50 [Disabled] [Enabled] Training Tracing: [Disabled] [Enabled] Lpddr Mem WL Set: [Set A] [Set B] BDAT Memory Test Type [Rank Margin Tool Rank] Rank Margin Tool Loop Count: Low Supply for LPDDR4 Data: [Disabled] [Enabled] Low Supply for LPDDR4 Clock/Command/Control: [Disabled] [Enabled] Memory Test on Warm Boot: [Disabled]...
  • Page 51 [PCIE 14] [PCIE 15] [PCIE 16] [PCIE 17] [PCIE 18] [PCIE 19] Internal Graphics: [Auto] [Disabled] [Enabled] GTT Size: [2 MB] [4 MB] [8 MB] Aperture Size: [128 MB] [256 MB] [512 MB] [1024 MB] [2048 MB] PSMI SUPPORT: [Disabled] [Enabled] DVMT- Pre-Allocated: [0M]...
  • Page 52 [128M] [256M] [MAX] DISM Size: [0GB] [1GB] [2GB] [3GB] [4GB] [5GB] [6GB] [7GB] Intel Graphics Pei Display Peim: [Enabled] [Disabled] VDD Enable: [Disabled] [Enabled] Configure GT for use: [Enabled] [Disabled] PAVP Enable: [Enabled] [Disabled] Cdynmax Clamping Enable: [Enabled] [Disabled] Cd Clock Frequency: [172.8 Mhz] [307.2 Mhz] [556.8 Mhz]...
  • Page 53 IUER Slate Enable: [Disabled] [Enabled] IUER Dock Enable: [Disabled] [Enabled] VT-d: [Disabled] [Enabled] 6.5.2 PCH-IO Configuration PCH-IO Configuration PCI Express Configuration PCI Express Configuration DMI Link ASPM Control: [Disabled] [L0s] [L1] [L0sL1] [Auto] PCIE Port assigned to LAN Disabled Port8xh Decode: [Disabled] [Enabled] Peer Memory write Enable:...
  • Page 54 [Built - in] [Slot] ASPM: [Disabled] [L0s] [L1] [L0sL1] [Auto] L1 Substates: [Disabled] [L1.1] [L1.1 & L1.2] ACS: [Disabled] [Enabled] PTM: [Disabled] [Enabled] DPC: [Disabled] [Enabled] EDPC: [Disabled] [Enabled] URR: [Disabled] [Enabled] FER: [Disabled] [Enabled] NFER: [Disabled] [Enabled] CER: [Disabled] [Enabled] SEFE: [Disabled]...
  • Page 55 [Disabled] [Enabled] Hot Plug: [Disabled] [Enabled] Advanced Error Reporting: [Disabled] [Enabled] PCIe Speed: [Auto] [Gen1] [Gen2] [Gen3] Transmitter Half Swing: [Disabled] [Enabled] Detect Timeout: Extra Bus Reserved: Reserved Memory: Reserved I/O: PCH PCIe LTR Configuration LTR: [Disabled] [Enabled] Snoop Latency Override: [Disabled] [Manual] [Auto]...
  • Page 56 Prefetchable Memory Alignment: PCIe Express Root Port 2 PCIe EQ override: [Disabled] [Enabled] Connection Type: [Built - in] [Slot] ASPM: [Disabled] [L0s] [L1] [L0sL1] [Auto] L1 Substates: [Disabled] [L1.1] [L1.1 & L1.2] ACS: [Disabled] [Enabled] PTM: [Disabled] [Enabled] DPC: [Disabled] [Enabled] EDPC: [Disabled]...
  • Page 57 SENFE: [Disabled] [Enabled] SECE: [Disabled] [Enabled] PME SCI: [Disabled] [Enabled] Hot Plug: [Disabled] [Enabled] Advanced Error Reporting: [Disabled] [Enabled] PCIe Speed: [Auto] [Gen1] [Gen2] [Gen3] Transmitter Half Swing: [Disabled] [Enabled] Detect Timeout: Extra Bus Reserved: Reserved Memory: Reserved I/O: PCH PCIe LTR Configuration LTR: [Disabled] [Enabled]...
  • Page 58 Extra options Detect Non-Compliance Device: [Disabled] [Enabled] Prefetchable Memory: Reserved Memory Alignment: Prefetchable Memory Alignment: PCIe Express Root Port 3 PCIe EQ override: [Disabled] [Enabled] Connection Type: [Built - in] [Slot] ASPM: [Disabled] [L0s] [L1] [L0sL1] [Auto] L1 Substates: [Disabled] [L1.1] [L1.1 &...
  • Page 59 [Enabled] CER: [Disabled] [Enabled] SEFE: [Disabled] [Enabled] SENFE: [Disabled] [Enabled] SECE: [Disabled] [Enabled] PME SCI: [Disabled] [Enabled] Hot Plug: [Disabled] [Enabled] Advanced Error Reporting: [Disabled] [Enabled] PCIe Speed: [Auto] [Gen1] [Gen2] [Gen3] Transmitter Half Swing: [Disabled] [Enabled] Detect Timeout: Extra Bus Reserved: Reserved Memory: Reserved I/O: PCH PCIe LTR Configuration...
  • Page 60 [Auto] Force LTR Override: [Disabled] [Enabled] LTR Lock: [Disabled] [Enabled] Extra options Detect Non-Compliance Device: [Disabled] [Enabled] Prefetchable Memory: Reserved Memory Alignment: Prefetchable Memory Alignment: PCI Express Root Port 4 Lane configured as USB/SATA/UFS PCI Express Root Port 5 PCI Express Root Port 5: [Disabled] [Enabled] Connection Type:...
  • Page 61 TC2: [VC0] [VC1] TC3: [VC0] [VC1] TC4: [VC0] [VC1] TC5: [VC0] [VC1] TC6: [VC0] [VC1] TC7: [VC0] [VC1] PTM: [Disabled] [Enabled] DPC: [Disabled] [Enabled] EDPC: [Disabled] [Enabled] URR: [Disabled] [Enabled] FER: [Disabled] [Enabled] NFER: [Disabled] [Enabled] CER: [Disabled] [Enabled] SEFE: [Disabled] [Enabled] SENFE:...
  • Page 62 SECE: [Disabled] [Enabled] PME SCI: [Disabled] [Enabled] Hot Plug: [Disabled] [Enabled] Advanced Error Reporting: [Disabled] [Enabled] PCIe Speed: [Auto] [Gen1] [Gen2] [Gen3] Transmitter Half Swing: [Disabled] [Enabled] Detect Timeout: Extra Bus Reserved: Reserved Memory: Reserved I/O: PCH PCIe LTR Configuration LTR: [Disabled] [Enabled]...
  • Page 63 [Enabled] Prefetchable Memory: Reserved Memory Alignment: Prefetchable Memory Alignment: PCI Express Root Port 6 Lane configured as USB/SATA/UFS PCI Express Root Port 7 PCI Express Root Port 7: [Disabled] [Enabled] Connection Type: [Built-in] [Slot] ASPM: [Disabled] [L0s] [L1] [L0sL1] [Auto] L1 Substates: [Disabled] [L1.1]...
  • Page 64 [VC0] [VC1] TC6: [VC0] [VC1] TC7: [VC0] [VC1] PTM: [Disabled] [Enabled] DPC: [Disabled] [Enabled] EDPC: [Disabled] [Enabled] URR: [Disabled] [Enabled] FER: [Disabled] [Enabled] NFER: [Disabled] [Enabled] CER: [Disabled] [Enabled] SEFE: [Disabled] [Enabled] SENFE: [Disabled] [Enabled] SECE: [Disabled] [Enabled] PME SCI: [Disabled] [Enabled] Hot Plug:...
  • Page 65 [Disabled] [Enabled] PCIe Speed: [Auto] [Gen1] [Gen2] [Gen3] Transmitter Half Swing: [Disabled] [Enabled] Detect Timeout: Extra Bus Reserved: Reserved Memory: Reserved I/O: PCH PCIe LTR Configuration LTR: [Disabled] [Enabled] Snoop Latency Override: [Disabled] [Manual] [Auto] Non Snoop Latency Override: [Disabled] [Manual] [Auto] Force LTR Override:...
  • Page 66 [Disabled] ClkReq for Clock0: [Platform-POR] [Disabled] Clock1 assignment: [Platform-POR] [Enabled] [Disabled] ClkReq for Clock1: [Platform-POR] [Disabled] Clock2 assignment: [Platform-POR] [Enabled] [Disabled] ClkReq for Clock2: [Platform-POR] [Disabled] Clock3 assignment: [Platform-POR] [Enabled] [Disabled] ClkReq for Clock3: [Platform-POR] [Disabled] Clock4 assignment: [Platform-POR] [Enabled] [Disabled] ClkReq for Clock4: [Platform-POR]...
  • Page 67 SATA Mode Selection: AHCI SATA Ports Multiplier: [Enabled] [Disabled] SATA Test Mode: [Enabled] [Disabled] Software Feature Mask Configuration Software Feature Mask Configuration HDD Unlock: [Disabled] [Enabled] LED Locate: [Disabled] [Enabled] Aggressive LPM Support: [Disabled] [Enabled] Serial ATA Port 0 Empty Software Preserve unknown Port 0:...
  • Page 68 [Enabled] SATA Port 0 RxPolarity: [Disabled] [Enabled] DITO Configuration: [Disabled] [Enabled] DITO Value DM Value Serial ATA Port 1 Empty Software Preserve unknown Port 1: [Disabled] [Enabled] Hot Plug: [Disabled] [Enabled] Configured as eSATA Hot Plug supported External: [Disabled] [Enabled] Spin Up Device: [Disabled] [Enabled]...
  • Page 69 Port 2: [Disabled] [Enabled] Hot Plug: [Disabled] [Enabled] Configured as eSATA Hot Plug supported External: [Disabled] [Enabled] Spin Up Device: [Disabled] [Enabled] SATA Device Type: [Hard Disk Drive] [Solid State Drive] Topology: [Unknown] [ISATA] [Direct Connect] [Flex] [M2] SATA Port 2 DevSlp: [Disabled] [Enabled] SATA Port 2 RxPolarity:...
  • Page 70 [GEN1] [GEN2] USB PDO Programming: [Disabled] [Enabled] USB Overcurrent: [Disabled] [Enabled] USB Internal Pullup resistor: [Disabled] [Enabled] USB Overcurrent Lock: [Disabled] [Enabled] USB Port Disable Override: [Disabled] [Select Per-Pin] USB Device/HOST Mode Override: [Disabled] [Select Per-Pin] USB UCSI ACPI device: [Disabled] [Enabled] SCS Configuration...

  • Page 71: Security Settings

    Security Settings Aptio Setup - AMI Main Advanced Chipset Security Boot Save & Exit Password Description Set Administrator Password If ONLY the Administrator’s password is set, then this only limits access to Setup and is only asked for when entering Setup. If ONLY the User’s password is set, then this Is a power on password and must be entered to Is a power on password and must be entered to...

  • Page 72: Boot Settings

    Boot Settings Aptio Setup - AMI Main Advanced Chipset Security Boot Save & Exit Boot Configuration Number of seconds toWait for Setup Prompt Timeout Setup Activation key. Bootup NumLock State [Off] 65535(0xFFFF)means Indef Quiet Boot [Enabled] inite waiting. Boot Option Priorities Fast Boot [Disabled] →←: Select Screen...

  • Page 73: Save & Exit Settings

    Save & Exit Settings Aptio Setup - AMI Main Advanced Chipset Boot Security Save & Exit Save options Exit system setup after Save Changes and Exit Saving the changes. Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Changes Discard Changes →←: Select Screen...
  • Page 74 Discard Changes Discard Changes done so far to any of the setup options? [Yes] [No] Restore Defaults Restore /Load Defaults values for all the setup options? [Yes] [No] Save as user Defaults Save the changes done so far as User Defaults? [Yes] [No] Restore user Defaults...

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