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Wilder Technologies PCIe Gen-5 U.2 User Manual

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PCIe Gen-5 U.2 Test Adapters User Manual
PCIe Gen-5 U.2
Test Adapters
User Manual
P a g e
| 1
©2024 Wilder Technologies, LLC
Document No. 910-0078-000 Rev. A

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Summary of Contents for Wilder Technologies PCIe Gen-5 U.2

  • Page 1 PCIe Gen-5 U.2 Test Adapters User Manual PCIe Gen-5 U.2 Test Adapters User Manual P a g e ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A...
  • Page 2 PCIe Gen-5 U.2 Accessories ......................4 PCIe Gen-5 U.2 Optional Accessories ..................5 Product Inspection .......................... 6 The PCIe Gen-5 U.2 Test Adapters and Handling Precautions ............7 General Test Adapters, Cable, and Connector ................8 Handling and Storage ........................8 Visual Inspection .........................
  • Page 3 PCIe Gen-5 U.2 Test Adapters User Manual Introduction This user’s guide documents the PCIe Gen-5 U.2 Test Adapters. The Test Adapters shown in Figure 1, tests PCIe Gen-5 U.2 hosts and devices against the PCIe Specification. The model numbers for the PCIe Gen-5 U.2 Test Adapters are as follows: Table 1.
  • Page 4 Wilder CMTS Interface Cable, 12” Length (305mm) 2.92mm Female to SMP Female, 9” Length (229mm), (REFCLK) Figure 2. The PCIe Gen-5 U.2 included accessories (NOT modeled to scale) P a g e ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A...
  • Page 5 PCIe Gen-5 U.2 Test Adapters User Manual PCIe Gen-5 U.2 Optional Accessories There are numerous Huber+Suhner PCIe Gen-5 accessories, such as adapters or cable assemblies, available for purchase from Richardson RFPD. The table below indicates the Huber+Suhner part numbers for the optional accessories.
  • Page 6 Always use a static-safe workstation when performing tests, as explained in the “Electrostatic Discharge Information” section. Product Inspection Upon receiving the PCIe Gen-5 U.2 Test Adapters from Wilder Technologies, perform the following product inspection: • Inspect the outer shipping container, foam-lined instrument case, and product for damage.
  • Page 7 PCIe Gen-5 U.2 Test Adapters User Manual The PCIe Gen-5 U.2 Test Adapters and Handling Precautions The PCIe Gen-5 U.2 Test Adapters require careful handling to avoid damage. Improper handling techniques, or using too small of a cable bend radius, can damage the coaxial cable connections.
  • Page 8 PCIe Gen-5 U.2 Test Adapters User Manual General Test Adapters, Cable, and Connector Observing simple precautions can ensure accurate and reliable measurements. Handling and Storage Before each use of the PCIEG5-U2-TPA test fixtures, ensure that all connectors are clean. Handle all cables carefully and store the test fixtures in the foam-lined instrument case when not in use, if possible.
  • Page 9 PCIe Gen-5 U.2 Test Adapters User Manual Electrostatic Discharge Information Protection against electrostatic discharge (ESD) is essential while connecting, inspecting, or cleaning the PCIEG5-U2-TPA test adapters and connectors attached to a static-sensitive circuit (such as those found in test set).
  • Page 10 Note: The PCIe Gen-5 CEM Variable ISI board (PCIe-VAR-ISI) is required for achieving total channel loss of TX test setup as well as system RX and device RX calibrations. Other accessories required for validation can be purchased from Richardson RFPD (refer to the PCIe Gen-5 U.2 Optional Accessories section).
  • Page 11 PCIe Gen-5 U.2 Test Adapters User Manual Figure 4. CMTS Frequency (100 MHz) USB Mini-B connector to provide power to CMTS board. Figure 5. CMTS Board USB Mini-B Connector (J7) P a g e | 11 ©2024 Wilder Technologies, LLC...
  • Page 12 PCIe Gen-5 U.2 Test Adapters User Manual Two MMPX connectors to output compliance mode toggle signal. These signals should be routed to the PER0 MMPX differential connectors of the CLB or CBB that the users DUT is connected to. Figure 6. CMTS Differential Output SMP Connectors (J6 and J5) CMTS push button.
  • Page 13 PCIe Gen-5 U.2 Test Adapters User Manual The CMTS automation header shown below can be used as an alternative to the CMTS push button to generates the compliance mode toggle signal. This header can be connected to a user interface (such as a standard GPIO) to control the compliance mode toggle signal.
  • Page 14 PCIe Gen-5 U.2 Test Adapters User Manual CBB Test Fixture Features • ATX Power Connector and Power Switch o The U.2 CBB uses a 24 pin ATX power connector. In addition, the on-board power switch enables power to be delivered to the CBB and DUT from the power supply when the switch is in the “ON”...
  • Page 15 PCIe Gen-5 U.2 Test Adapters User Manual • REFCLK/SSC o The U.2 CBB can provide a REFCLK with no SSC, or two SSC settings of 0.25% downspread or 0.5% downspread. This selection is made using the REFCLK SSC selection switch. With the switch placed in the middle position, the U.2 CBB will provide a 100 MHz REFCLK with no SSC.
  • Page 16 PCIe Gen-5 U.2 Test Adapters User Manual • Dual port enable switch Figure 22. CBB Dual Port Enable Switch (S1) o The U.2 CBB features a DUALPORTEN# switch to enable Dual Port Mode. When this switch is in the off position, dual port is not enabled. When this switch is in the on position, dual port is enabled.
  • Page 17 PCIe Gen-5 U.2 Test Adapters User Manual Figure 14. Automatic PERST Signal Delay (100 ms) Additionally, the PERST push buttons can be used to manually trigger a 100 ms PERST signal to reset the DUT. Figure 15. Manual PERST Signal (100 ms)
  • Page 18 PCIe Gen-5 U.2 Test Adapters User Manual • Lane characterization o Lane characterization traces are included on both U.2 CLB and CBB fixtures. These characterization lanes include a short trace and long trace used to determine the loss per inch of the fixture being characterized. This is done by taking a through measurement of the short trace and a through measurement of the long trace.
  • Page 19 PCIe Gen-5 U.2 Test Adapters User Manual o In addition to the short and long traces, the 2x through channel and de-embed channels can be used to characterize the specific traces on the CBB or CLB. The de-embed channel is a replica of the 3” TX and RX traces on the CBB plus half of the 2X through.
  • Page 20 PCIe Gen-5 U.2 Test Adapters User Manual CLB Test Fixture Features • Lane characterization o Similarly to the CBB, the CLB also has a 2X through trace, short trace, and long trace. However, the short and long trace also serve as the de-embed traces for the RX traces (long trace) and TX traces (short trace).
  • Page 21 PCIe Gen-5 U.2 Test Adapters User Manual • REFCLK SMP Connectors o The CLB has two differential SMP connectors for probing the REFCLK. The first set of differential SMP connectors (J18 and J19) are for REFCLKA and the second set of differential SMP connectors (J20 and J21) are for REFCLKB.
  • Page 22 PCIe Gen-5 U.2 Test Adapters User Manual TX Testing User Models Figure 21. Total Test Channel Loss for Gen-5 Example Figure 22. Device TX Test Setup Example Physical Links Under Test Wilder CMTS Interface Cable PCIe U.2 PCIe U.2 CLB...
  • Page 23 PCIe Gen-5 U.2 Test Adapters User Manual RX Testing User Models Figure 24. Device RX Calibration Example MMPX MMPX Cable 2.92 MMPX Adapter S PN: 85108590) Physical Links Under S PN: 840 1648) ariable ISI Test RX Lane (Channel to use determined PCIe U.2...
  • Page 24 PCIe Gen-5 U.2 Test Adapters User Manual MMPX MMPX 2.92 MMPX Cable ( S PN: Adapter ( S PN: Physical Links Under ariable ISI 85108590) 840 1648) Test RX Lane (Channel to use determined PCIe U.2 during PCIe U.2 CLB...
  • Page 25 Header Pins 28 Female MMPX Connectors 4 Male SMP Connectors (REFCLK) PCIe Gen-5 U.2 Plug Connector Figure 28. The PCIe Gen-5 U.2 Compliance Load Board (CLB) P a g e | 25 ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A...
  • Page 26 PERST Signal Reset Buttons 2 5-Position Low- 24-Position, 600V, 13A Speed Access Pins ATX Power Connector Figure 29. The PCIe Gen-5 U.2 Compliance Base Board (CBB) P a g e | 26 ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A...
  • Page 27 PCIe Gen-5 U.2 Test Adapters User Manual USB Mini-B Receptacle Connector 2 Female MMPX Connectors (CMTS Signals) CMTS Signal Button Automated CMTS Header Pins Figure 30. The PCIe Gen-5 Compliance Mode Toggle Signal (CMTS) Fixture P a g e | 27 ©2024 Wilder Technologies, LLC...
  • Page 28 PCIe Gen-5 U.2 Test Adapters User Manual Table 4. PCIe Gen-5 U.2 Receptacle (CBB) Pin Assignments Device DUT Pin Description Connector Pin Number Destination P5, P6, P12, S1, S4, S7, S8, S11, S14, S16, S19, S22, S25, S28, Ground E9, E12, E15, E19, E22...
  • Page 29 PCIe Gen-5 U.2 Test Adapters User Manual Table 5. PCIe Gen-5 U.2 Plug (CLB) Pin Assignments System DUT Pin Description Connector Pin Number Destination P5, P6, P12, S1, S4, S7, S8, S11, S14, S16, S19, Ground S22, S25, S28, E9, E12, E15, E19, E22...
  • Page 30 PCIe Gen-5 U.2 Test Adapters User Manual Electrical Specifications NOTE: All specifications in this manual are subject to change. Table 6. Electrical Specifications SPECIFICATION TYPICAL NOTES Differential Impedance All Differential Pairs, CBB and CLB, excluding 85 ± 5% (ohms), 100 ps Rise Time PCIe U.2 connector.
  • Page 31 PCIe Gen-5 U.2 Test Adapters User Manual Typical High-Speed Serial Characteristics The high-speed serial measurements of the PCIe Gen-5 U.2 Test Adapters use a 4-port (50 Ω) VNA calibrated from 50 MHz to 40 GHz with 800 points. The measurements are in the form of S-parameters.
  • Page 32 PCIe Gen-5 U.2 Test Adapters User Manual Figure 32. CLB (PCIEG5-U2-TPA-CLB) characterization without renormalization or gating Figure 33. CBB (PCIEG5-U2-TPA-CBB) characterization with renormalization and gating P a g e | 32 ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A...
  • Page 33 PCIe Gen-5 U.2 Test Adapters User Manual Figure 34. CBB (PCIEG5-U2-TPA-CBB) characterization without renormalization or gating Figure 35. CLB and CBB (PCIEG5-U2-TPA-CLBCBB) mated insertion and return loss with renormalization and gating P a g e | 33 ©2024 Wilder Technologies, LLC...
  • Page 34 PCIe Gen-5 U.2 Test Adapters User Manual Figure 36. CLB and CBB (PCIEG5-U2-TPA-CLBCBB) mated insertion and return loss without renormalization or gating Figure 37. CLB and CBB (PCIEG5-U2-TPA-CLBCBB) mated conversion loss P a g e | 34 ©2024 Wilder Technologies, LLC...
  • Page 35 PCIe Gen-5 U.2 Test Adapters User Manual Figure 38. CLB and CBB (PCIEG5-U2-TPA-CLBCBB) mated FEXT Figure 39. CLB and CBB (PCIEG5-U2-TPA-CLBCBB) mated NEXT P a g e | 35 ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A...
  • Page 36 European Union Directive 2002/96/EC on waste electrical and electronic equipment ("WEEE Directive"). As a service to our customers, Wilder Technologies is also available for managing the proper recycling and/or disposal of all Wilder Technologies products that have reached the end of their useful life.
  • Page 37 PCIe Peripheral Component Interconnect Express PCIEG5-U2-TPA PCIe Gen-5 U.2 Test Fixture. A specialized assembly that interfaces to an PCIe U.2 (SFF-8639) Receptacle or Plug and enables access of signals for measurement or stimulation. Formally called Small Form Factor 8639 (SFF-8639)
  • Page 38 TX Testing User Models, 19, 20, 22 The PCIe Gen-5 U.2 CBB, 26 Typical High-Speed Serial Characteristics, 31 The PCIe Gen-5 U.2 CLB, 25 USB, 37 The PCIe Gen-5 U.2 Test Adapter Set, 3 User Models, 10 Glossary, 37 Visual Inspection, 8 Handling and Storage, 8...
  • Page 40 Visit our website at www.wilder-tech.com Wilder Technologies, LLC 11201 NE 9 Vancouver WA, 98684 Phone: 360-859-3041 Fax: 360-859-3105 www.wilder-tech.com ©2024 Wilder Technologies, LLC Document No. 910-0078-000 Rev. A Document Created: 2/20/2024.

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