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Lauterbach C7000 Manual

Debugger and trace
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C7000 Debugger and Trace
Release 09.2024
MANUAL

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Summary of Contents for Lauterbach C7000

  • Page 1 C7000 Debugger and Trace Release 09.2024 MANUAL...
  • Page 2  ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... TI DSPs ............................. C7000 Debugger and Trace ....................History ..........................Introduction ........................Brief Overview of Documents for New Users Demo and Start-up Scripts Converter from GEL to PRACTICE ..................
  • Page 3 Controlling the Trace Capture Trace Breakpoints Command reference: TRC ....................Trace control (TRC) TRC.CLEAR Clear trace settings TRC.CLOCK Set core clock frequency for timing measurements TRC.DataTrace Define broadcast of load/store address tracing TRC.OFF Switch TRC off 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 4 Change the default ID for a TRC trace source TRC.TracePriority Define priority of TRC messages TRC.state Display TRC setup Target Adaption ......................... Probe Cables Interface Standards JTAG, Serial Wire Debug, cJTAG Connector Type and Pinout Debug Cable CombiProbe Preprocessor FAQ ............................. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 5 C7000 Debugger and Trace Version 05-Oct-2024 History 29-Mar-2024 New command SYStem.Option.MACHINESPACES. 18-Mar-2024 New command SYStem.Option.ICFLUSH. 28-Apr-2023 New command SETUP.DIS. 07-Apr-2023 Removed command SYStem.Option.PWRCHECK. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 6 (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.
  • Page 7 Code Composer Studio’s usefulness. The converter allows you to convert GEL language into PRACTICE scripts (*.cmm), which can be used directly in TRACE32. For more detailed information on that converter please refer to “Converter from GEL to PRACTICE” (converter_gel.pdf). 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 8 Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 9 Data Value breakpoint: Number of on-chip data breakpoints that can be used to stop the program when a specific data value is written to an address or when a specific data value is read from an address. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 10 On-chip Instruction Read/Write Data Value Core breakpoints breakpoints breakpoint breakpoints C71x up to 4 single — 1 single address address or range as bit mask 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 11 See DAP. APB, APB2 See DAP. AXI, AXI2 See DAP. Access to C7000 extended configuration registers Data Memory DAP, DAP2, Memory access via bus masters, so named Memory Access Ports (MEM- AHB, AHB2, AP), provided by a Debug Access Port (DAP).
  • Page 12 Access Class Description Intermediate address. Available on devices having Virtualization Extension. Non-Secure Mode Program Memory Supervisor Memory (privileged access) Root Mode (Hypervisor) User Memory Virtual Memory (memory on the debug system) Secure Mode 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 13 Level Test Access Port. The debugger might need to control it in order to reconfigure the JTAG chain or to control power, clock, reset, and security of different chip components. For descriptions of the commands on the MultiTap tab, see MultiTap. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 14 Format: SYStem.CONFIG <parameter> SYStem.MultiCore <parameter> (deprecated) <parameter>: CJTAGFLAGS <flags> (C7000 only) (DebugPort) CONNECTOR [MIPI34 | MIPI20T] (C7000 only) CORE <core> <chip> CoreNumber <number> DEBUGPORT [DebugCable0 | DebugCableA | DebugCableB] DEBUGPORTTYPE [JTAG | SWD | CJTAG] Slave [ON | OFF] SWDP [ON | OFF] (C7000 only) SWDPIdleHigh [ON | OFF] SWDPTargetSel <value>...
  • Page 15 AXIAPn.ACEEnable [ON | OFF] AXIAPn.Base <address> AXIAPn.CacheFlags <value> AXIAPn.HPROT [<value> | <name>] AXIAPn.Port <port> AXIAPn.RESet AXIAPn.view AXIAPn.XtorName <name> DEBUGAPn.Port <port> DEBUGAPn.RESet DEBUGAPn.view DEBUGAPn.XtorName <name> JTAGAPn.Base <address> JTAGAPn.Port <port> JTAGAPn.CorePort <port> JTAGAPn.RESet JTAGAPn.view JTAGAPn.XtorName <name> 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 16 MEMORYAPn.view MEMORYAPn.XtorName <name> <parameter>: ADTF.Base <address> ADTF.RESet COmponents ADTF.Type [NONE | ADTF | ADTF2 | GEM] ADTF.view AET.Base <address> (C5000, C6000, C7000 only) AET.RESet (C5000, C6000, C7000 only) AET.view (C5000, C6000, C7000 only) <parameter>: CMI.Base <address> (COmponents CMI.RESet cont.) CMI.TraceID <id>...
  • Page 17 TBR.Name <string> TBR.NoFlush [ON | OFF] TBR.RESet TBR.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL- STOP | FULLCTI] TBR.view TPIU.ATBSource <source> TPIU.Base <address> TPIU.Name <string> TPIU.RESet TPIU.Type [CoreSight | Generic] TPIU.view 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 18 <parameter>: TRACEPORT.Name (Components TRACEPORT.RESet cont.) TRACEPORT.TraceSource TRACEPORT.Type TRACEPORT.view TRC.Base <address> (C7000 only) TRC.RESet (C7000 only) TRC.view (C7000 only) <parameter>: COREBASE <address> (Deprecated) CTIBASE <address> DEBUGBASE <address> ETBBASE <address> ETBFUNNELBASE <address> ETFBASE <address> ETMBASE <address> <parameter>: FUNNEL2BASE <address> FUNNELBASE <address> (Deprecated cont.) HTMBASE <address>...
  • Page 19 This is a common description of the SYStem.CONFIG command group for the TI C2000, C5000, C6000 and C7000 DSPs. Each debugger will provide only a subset of these commands. Some commands need a certain CPU type selection (SYStem.CPU <type>) to become active and it might additionally depend on further settings.
  • Page 20 But sometimes it is a must to tell the debugger that these cores share resources on the same <chip>. Whereby the “chip” does not need to be identical with the device on your target board: debugger#1: <core>=1 <chip>=1 debugger#2: <core>=2 <chip>=1 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 21 JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). The other debuggers need to have the setting Slave ON. Default: OFF. Default: ON if CORE=... >1 in the configuration file (e.g. config.t32). 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 22 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 23 TDO signal. See possible TAP types and example below. Default: 0. NOTE: If you are not sure about your settings concerning IRPRE, IRPOST, DRPRE, and DRPOST, you can try to detect the settings automatically with the SYStem.DETECT.DaisyChain command. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 24 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 25 ARM11 TAP ETB TAP OfNoInterest TAP DAP TAP IR: 5bit IR: 4bit IR: 7bit IR: 4bit SYStem.CONFIG IRPRE 15. SYStem.CONFIG DRPRE SYStem.CONFIG DAPIRPOST 16. SYStem.CONFIG DAPDRPOST SYStem.CONFIG ETBIRPOST SYStem.CONFIG ETBDRPOST SYStem.CONFIG ETBIRPRE SYStem.CONFIG ETBDRPRE 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 26 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 27 TAP in the JTAG chain. E.g. ARM11 TAP if you intend to debug an ARM11. Used if MULTITAP=Icepickx. ETBTAP <tap> Specifies the TAP number which needs to be activated to get the ETB TAP in the JTAG chain. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 28 Number of a Non-JTAG Control Register (NJCR) which shall be used by the debugger. Used if MULTITAP=Icepickx. SLAVETAP <tap> Specifies the TAP number to get the Icepick of the sub-system in the JTAG scan chain. Used if MULTITAP=IcepickXY (two Icepicks). 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 29 “Port” or “Base” (with “DP:” access) in case XtorName remains empty. Example 1: SoC-400 SoC-400 ROM table Memory Access Port CoreSight (MEM-AP) Component Debug ROM table Memory Port Access Port (DP) (MEM-AP) CoreSight Component JTAG Access Port (JTAG-AP) 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 30 The secure access bit HPROT[1] is not controlled by this option, but via the access class prefixes “Z” and “N” as well as “L” and “O” if the Access Port supports Realm Management Extension. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 31 Description DeviceSYStem =0x30: Domain=0x3, Cache=0x0 NonCacheableSYStem =0x32: Domain=0x3, Cache=0x2 ReadAllocateNonShareable =0x06: Domain=0x0, Cache=0x6 ReadAllocateInnerShareable =0x16: Domain=0x1, Cache=0x6 ReadAllocateOuterShareable =0x26: Domain=0x2, Cache=0x6 WriteAllocateNonShareable =0x0A: Domain=0x0, Cache=0xA WriteAllocateInnerShareable =0x1A: Domain=0x1, Cache=0xA WriteAllocateOuterShareable =0x2A: Domain=0x2, Cache=0xA 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 32 Undo the configuration for this access port. This does not cause a physical reset for the access port on the chip..view Opens a window showing the current configuration of the access port. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 33 AP access port number (0-255) of a SoC-400 system where MEMORYACCESSPORT system memory can be accessed even during runtime (typically <port> (deprecated) an AHB). Used for “E:” access class while running, assuming “SYStem.MemAccess DAP”. Default: <port>=0. SoC-600 Specific Commands 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 34 Example: SYStem.CONFIG.JTAGAP1.Base DP:0x80005000 Meaning: The control register block of the JTAG access ports starts at address 0x80005000. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 35 If you press the button with the three dots you get the corresponding command in the command line where you can view and maybe copy it into a script file. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 36 SYStem.CONFIG.COREDEBUG.Base 0x80010000 0x80012000 SYStem.CONFIG.BMC.Base 0x80011000 0x80013000 SYStem.CONFIG.ETM.Base 0x8001c000 0x8001d000 SYStem.CONFIG.STM1.Base EAHB:0x20008000 SYStem.CONFIG.STM1.Type ARM SYStem.CONFIG.STM1.Mode STPv2 SYStem.CONFIG.FUNNEL1.Base 0x80004000 SYStem.CONFIG.FUNNEL2.Base 0x80005000 SYStem.CONFIG.TPIU.Base 0x80003000 SYStem.CONFIG.FUNNEL1.ATBSource ETM.0 0 ETM.1 1 SYStem.CONFIG.FUNNEL2.ATBSource FUNNEL1 0 STM1 7 SYStem.CONFIG.TPIU.ATBSource FUNNEL2 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 37 HTM on port 1 and from STM on port 7. In an SMP (Symmetric MultiProcessing) debug session where you used a list of base addresses to specify one component per core you need to indicate which component in the list is meant: 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 38 ETM, ETR a list of base addresses to specify one component per core. Example assuming four cores: SYStem.CONFIG COREDEBUG.Base 0x80001000 0x80003000 0x80005000 0x80007000 For a list of possible components including a short description Components and Available Commands. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 39 ID (ETM.TraceID <id>). The default setting is typically fine because the debugger uses different default trace IDs for different components. For a list of possible components including a short description Components and Available Commands. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 40 It is possible that different funnels have the same address for their control register block. This assumes they are on different buses and for different cores. In this case it is needed to give the funnel different names to differentiate them. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 41 See the description of the commands above. Please note that there is a common description for ..ATBSource, ..Base, , ..RESet, ..TraceID. ADTF.Base <address> ADTF.RESet ADTF.Type [None | ADTF | ADTF2 | GEM] 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 42 REPlicatorB can be used from other ATB sinks to connect to output A or B to the Replicator. OCP.Base <address> OCP.RESet OCP.TraceID <id> OCP.Type <type> Open Core Protocol watchpoint unit (OCP) - Texas Instruments Trace source module delivering bus trace information to a system trace module. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 43 Trace source delivering system trace information e.g. sent by software in printf() style. TPIU.ATBSource <source> TPIU.Base <address> TPIU.RESet TPIU.Type [CoreSight | Generic] Trace Port Interface Unit (TPIU) - ARM CoreSight module Trace sink sending the trace off-chip on a parallel trace port (chip pins). 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 44 RAM which accesses shall be traced. The trace packages include only relative addresses to PERBASE and RAMBASE. For a list of possible components including a short description Components and Available Commands. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 45 QV1: This mode is not yet used. TIOCPTYPE <type> Specifies the type of the OCP module from Texas Instruments (TI). view Opens a window showing most of the SYStem.CONFIG settings and allows to modify them. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 46 FUNNEL1.ATBSource ETM <port> (1) ETMTPIUFUNNELPORT <port> FUNNEL3.ATBSource ETM <port> (1) FILLDRZERO [ON | OFF] CHIPDRPRE 0 CHIPDRPOST 0 CHIPDRLENGTH <bits_of_complete_dr_path> CHIPDRPATTERN.Alternate 0 FUNNEL2BASE <address> FUNNEL2.Base <address> FUNNELBASE <address> FUNNEL1.Base <address> HSMBASE <address> HSM.Base <address> 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 47 TIOCPTYPE <type> OCP.Type <type> TIPMIBASE <address> PMI.Base <address> TISCBASE <address> SC.Base <address> TISTMBASE <address> STM1.Base <address> STM1.Mode STP STM1.Type TI TPIUBASE <address> TPIU.Base <address> TPIUFUNNELBASE <address> FUNNEL3.Base <address> TRACEETBFUNNELPORT <port> FUNNEL4.ATBSource ADTF <port> (1) 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 48 CPU registers can be read. Executing this command will force the CPU into a halted state where all CPU and ECR registers can be read. Warning: Performing “Go” in post-mortem state results in undefined behavior. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 49 10 MHz. This limit can be changed by adding the frequency parameter. A limitation is required that the JTAG clock speed can not become higher than the physical interface can manage. Example: SYStem.JtagClock RTCK 20MHz 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 50 They define the TAP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 51 SYStem.ENTERPostMortem this command allows to unblock memory accesses which are currently blocked by the memory system. If a subsequent memory access leads to a blocking state, the command has to be used again. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 52 Resets the target via the reset line, initializes the debug port (JTAG, SWD, cJTAG), and starts the program execution. For a reset, the reset line has to be connected to the debug connector. Program execution can, for example, be stopped by the Break command. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 53 Data.dump. Display all addresses as 32-bit values. 64-bit addresses are truncated. Display all addresses as 64-bit values. AUTO Number of displayed digits depends on address size. NARROW 32-bit display with extendible address field. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 54 This option configures the value used for the Cache and Domain bits in the Control Status Word (CSW[27:24]->Cache, CSW[14:13]->Domain) of an AXI Access Port of a DAP , when using the AXI: memory class. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 55 Bug fix for derivatives which do not return the correct pattern on a DAP (Arm CoreSight Debug Access Port) instruction register (IR) scan. When activated, the returned pattern will not be checked by the debugger. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 56 Switching procedure as it is required on SWJ-DP without a dormant state. The device is in JTAG mode after power-up. LuminaryJtagToSwd Switching procedure as it is required on devices from LuminaryMicro. The device is in JTAG mode after power-up. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 57 SYStem.Option.DUALPORT OFF and use the access class prefix E or the format option %E for the specific windows. SYStem.Option.EnReset Allow the debugger to drive nRESET (nSRST) SYStem.state window> EnReset] Format: SYStem.Option.EnReset [ON | OFF] Default: ON. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 58 If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 59 SYStem.Option.INTDIS Disable all interrupts Format: SYStem.Option.INTDIS [ON | OFF] Default: OFF. If this option is ON, all interrupts on the Arm core are disabled. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 60 To keep the debug interface active, it is recommended that SYStem.Option.DAPDBGPWRUPREQ is set to AlwaysON. SYStem.Option.DAPSYSPWRUPREQ Force system power in DAP Format: SYStem.Option.DAPSYSPWRUPREQ [AlwaysON | ON | OFF] Default: ON. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 61 CPU may leave the halted state to service the interrupt. The CPU then continues execution until all real- time interrupts have completed. SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping Format: SYStem.Option.IMASKHLL [ON | OFF] Default: OFF. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 62 Individual symbol sets can be loaded for each virtual machine. SYStem.Option.PWRDWN Allow power-down mode Format: SYStem.Option.PWRDWN [ON | OFF] Default: OFF. If this option is OFF, the debugger forces the chip to keep clock and keep power on OMAPxxxx devices. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 63 If possible (nRESET is open collector), this command asserts the nRESET line on the debug connector. This will reset the target including the CPU but not the debug port. The function only works when the system is in SYStem.Mode.Up. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 64 ; set a marker Alpha to the entry ; of the function sieve Break.Set V.END(sieve)-1 /Beta ; set a marker Beta to the exit ; of the function sieve BMC.<counter>.ATOB ON ; advise <counter> to count only ; in AB-range 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 65 For a description of the generic arguments, see SETUP.DIS “General <other_constants> Commands Reference Guide S” (general_ref_s.pdf). LowerCase Default. Sets the mnemonics to lower case. UpperCase Sets the mnemonics to upper case. This format is closer to the TI disassembler. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 66 Break.Set 0x1000--0x17ff /Write ; 1000--17ff Break.Set 0x1001--0x17ff /Write ; gives an error message TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 67 CPU may be not powerful enough to cover the whole structure. If the option TrOnchip.VarCONVert is set to ON, the breakpoint will automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error message is generated. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 68 Tracing The processor trace for C7000 is based on the ARM Coresight architecture. The trace can either be stored in trace buffers on the chip (e.g. ETB) or sent out through an external trace port (TPIU). For further information about Coresight component configuration please refer to “Setup of the Debugger for a...
  • Page 69 Command reference: TRC Trace control (TRC) The TRC command group implements the trace specific functions for the C7000 debugger. For configuration, use the TRACE32 command line, a PRACTICE script (*.cmm), or the TRC.state window. The following TRACE32 commands are available to configure the C7x trace.
  • Page 70 AsyncTimeStamp), this setting is used to calculate the elapsed clock cycles from the elapsed time in seconds. • For timing modes which combine timestamps with cycle count information, this setting is not required. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 71 ■ ReadAddress ■ WriteAddress ■ ■ Address ■ ReadData ■ WriteData ■ ■ Data ■ ■ Read ■ ■ Write ■ ■ ■ ■ TRC.OFF Switch TRC off Format: TRC.OFF Disables TRC functionality. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 72 Stall processor to prevent FIFO overflow Format: TRC.STALL [ON | OFF] Allows the TRC to stall the processor to prevent an output FIFO overflow. If enabled, the trace will be no longer real time. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 73 Defines which timing information is included in the trace stream. External The timestamps are generated in the debug hardware (default) No timestamp information is included in the trace AsyncTimeStamps The timestamps are generated by the TRC unit 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 74 ATB input port. A priority value of 0 defines the hightest priority and 7 the lowest. The command TRC.TracePriority allows to change the default priority of an ATB input port. 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 75 Example: For information about ON, see TRC.ON. Exceptions: • The Trace button opens the main trace control window (Trace.state). • The TPIU button opens the TPIU.state window. • The List button opens the main trace list window (Trace.List). 1989-2024 © Lauterbach C7000 Debugger and Trace...
  • Page 76 Pro, Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace or Power Debug II). Connector Type and Pinout Debug Cable Adaptation for ARM Debug Cable: See https://www.lauterbach.com/adarmdbg.html. For details on logical functionality, physical connector, alternative connectors, electrical characteristics, timing behavior and printing circuit design hints refer to “Arm Debug and Trace Interface Specification”...
  • Page 77 SYStem.CONFIG DEBUGPORT [DebugCableA | DebugCableB]. The CombiProbe can detect the location of the cable if only one is connected. Preprocessor Adaptation for ARM ETM Preprocessor Mictor: See https://www.lauterbach.com/adetmmictor.html. Adaptation for ARM ETM Preprocessor MIPI-60: See https://www.lauterbach.com/adetmmipi60.html Please refer to https://support.lauterbach.com/kb.