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Ricoh R2061 Series Manual
Ricoh R2061 Series Manual

Ricoh R2061 Series Manual

3 wire interface real-time clock ics with battery backup switch-over function

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3 wire interface Real-Time Clock ICs with Battery Backup switch-over Function
OUTLINE
The R2061 is a CMOS real-time clock IC connected to the CPU by three signal lines, CE, SCLK, and SIO, and
configured to perform serial transmission of time and calendar data to the CPU. Further, battery backup
switchover circuit and a voltage detector. The periodic interrupt circuit is configured to generate interrupt signals
with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate
interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the
oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.4μA at 3V). The
oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; The
supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply
voltage monitoring threshold settings. The oscillation adjustment circuit is intended to adjust time counts with
high precision by correcting deviations in the oscillation frequency of the quartz crystal unit. Battery backup
switchover function is the automatic switchover circuit between a main power supply and a backup battery of
primary or secondary battery. Switchover is executed by monitoring the voltage of a main power supply,
therefore the voltage of a backup battery voltage is not relevant. Since the package for these ICs is SSOP16
(5.0x6.4x1.25: R2061Sxx) and FFP12 (2.0x2.0x1.0: R2061Kxx), high density mounting of ICs on boards is
possible.
FEATURES
• Minimum Timekeeping supply voltage Typ. 0.75V (Max. 1.00V); VDD pin
• Low power consumption
• Built-in Backup switchover circuit (can be used for a primary battery, a secondary battery, or an electric
double layer capacitor)
• Three signal lines (CE, SCLK, and SIO) required for connection to the CPU.
• (Maximum clock frequency of 1MHz (with V
• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months,
days, and weeks) (in BCD format)
• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1
month) to the CPU and provided with an interrupt flag and an interrupt halt
• 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and
minute alarm settings)
• Built-in voltage detector with delay
• With Power-on flag to prove that the power supply starts from 0V
• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
• Automatic identification of leap years up to the year 2099
• Selectable 12-hour and 24-hour mode settings
• Built-in oscillation stabilization capacitors (CG and CD)
• High precision oscillation adjustment circuit
• CMOS process
• Package SSOP16 (5.0mm x 6.4mm x 1.25mm : R2061Sxx), FFP12 (2.0mm x 2.0mm x 1.0mm : R2061Kxx
R2061 SERIES
Typ. 0.4μA (Max. 1.0μA) at V
= 3V) )
CC
NO.EA-112-110310
=3V
DD
·····
1

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Summary of Contents for Ricoh R2061 Series

  • Page 1 R2061 SERIES 3 wire interface Real-Time Clock ICs with Battery Backup switch-over Function NO.EA-112-110310 OUTLINE The R2061 is a CMOS real-time clock IC connected to the CPU by three signal lines, CE, SCLK, and SIO, and configured to perform serial transmission of time and calendar data to the CPU. Further, battery backup switchover circuit and a voltage detector.
  • Page 2 R2061 series PIN CONFIGURATION R2061Kxx(FFP12) R2061Sxx(SSOP16) VDCC SCLK OSCIN OSCOUT INTR TOP VIEW TOP VIEW BLOCK DIAGRAM CPU power supply BATTERY VOLTAGE VOLTAGE DETECTOR MONITOR VDCC DELAY REAL OSCIN TIME CLOCK SCLK OSCOUT INTR VOLTAGE REFERENCE...
  • Page 3 R2061 series SELECTION GUIDE In the R2061xxx Series, output voltage and options can be designated. Part Number is designated as follows: R2061K01-E2 ←Part Number ↑↑ ↑ R2061abb-cc Code Description Designation of the package. K: FFP12 S: SSOP16 Serial number of Voltage detector setting etc.
  • Page 4 R2061 series PIN DESCRIPTION Symbol Item Description Chip enable The CE pin is used for interfacing with the CPU. Should be held high to Input allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5 volts regardless of supply voltage.
  • Page 5 DET1 *2) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2061 series incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary. *3) Quartz crystal unit: CL=6-8pF, R1=30KΩ...
  • Page 6 R2061 series DC ELECTRICAL CHARACTERISTICS • R2061K01 (Unless otherwise specified: V =0V, V =3.0V, V =2.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C) Symbol Item Pin Name Conditions Min. Typ. Max. Unit “H” Input Voltage 1 CE, SCLK 0.8xV...
  • Page 7 R2061 series • R2061S02 (Unless otherwise specified: V =0V,V =3.0V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C) Symbol Item Pin Name Conditions Min. Typ. Max. Unit “H” Input Voltage 1 CE, SCLK 0.8xV “H” Input Voltage 2 0.8xV...
  • Page 8 R2061 series • R2061K03 (Unless otherwise specified: V =0V, V =3.0V, V =3.3V, 0.1uF between VDD and VSS, CIN and VSS, Topt=-40 to +85°C) Symbol Item Pin Name Conditions Min. Typ. Max. Unit “H” Input Voltage 1 CE, SCLK 0.8x “H”...
  • Page 9 R2061 series AC ELECTRICAL CHARACTERISTICS Unless otherwise specified: V =0V,Topt=-40 to +85°C Input and Output Conditions: V =0.8×V =0.2×V =0.8×V =0.2×V ,CL=50pF ≥1.7V *1) Item Condi- Unit -bol Tions Min. Typ. Max. CE Set-up Time CE Hold Time μs CE Recovery Time...
  • Page 10 R2061 series PACKAGE DIMENSIONS • R2061Kxx 1PIN INDEX 0.05 0.35 2PIN INDEX 0.25 1.0Max 0.35 0.2±0.15 (BOTTOM VIEW) 0.17±0.1 0.27±0.15 2.0±0.1 unit: mm...
  • Page 11 R2061 series • R2061Sxx 0 to 10° 5.0±0.3 +0.1 0.15 -0.05 0.65 0.225typ 0.10 +0.1 0.22 -0.05 0.15 unit: mm TAPING SPECIFICATION The R2061 Series have one designated taping direction. The product designation for the taping components is "R2061S/Kxx-E2".
  • Page 12 • Battery Backup Switchover Function The R2061 Series have two power supply input, or VCC and VSB. With monitoring VCC pin input voltage, which voltage between the two is supplied to the internal power supply is decided. Refer to the next table to see the state of the backup battery and internal power supply’s state of the IC by each condition.
  • Page 13 R2061 series • Clock and Calendar Function The R2061 reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4.
  • Page 14 R2061 series The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring.
  • Page 15 R2061 series Address Mapping Address Register Name D a t a A3A2A1A0 0 0 0 0 Second Counter 0 0 0 1 Minute Counter 0 0 1 0 Hour Counter P/ A 0 0 1 1 Day-of-week Counter 0 1 0 0...
  • Page 16 R2061 series Register Settings • Control Register 1 (ADDRESS Eh) WALE DALE SCRA TEST (For Writing) 12 /24 TCH2 WALE DALE SCRA TEST (For Reading) 12 /24 TCH2 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.
  • Page 17 R2061 series (4) TEST Test Bit TEST Description Normal operation mode. (Default) Test mode. The TEST bit is used only for testing in the factory and should normally be set to 0. (5) CT2,CT1, and CT0 Periodic Interrupt Selection Bits...
  • Page 18 R2061 series CTFG Bit IN T R Pin Setting CTFG bit to 0 Setting CTFG bit to 0 (Increment of (Increment of (Increment of second counter) second counter) second counter) *1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or 60sec.
  • Page 19 R2061 series • Control Register 2 (Address Fh) VDSL VDET SCRA CTFG WAFG DAFG (For Writing) TCH1 VDSL VDET SCRA CTFG WAFG DAFG (For Reading) TCH1 Indefinite Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.
  • Page 20 R2061 series (5) SCRATCH1 Scratch Bit 1 SCRATCH1 Description (Default) The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1 bit will be set to 0 when the PON bit is set to 1 in the Control Register 2.
  • Page 21 R2061 series • Time Counter (Address 0-2h) Second Counter (Address 0h) (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) Minute Counter (Address 1h) (For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite...
  • Page 22 R2061 series • Day-of-week Counter (Address 3h) (For Writing) (For Reading) Indefinite Indefinite Indefinite Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts.
  • Page 23 R2061 series The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, …, 92, and 96 in leap years) and are carried to the 19 /20 digits in reversion from 99 to 00. The 19 /20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.
  • Page 24 R2061 series • Alarm_W Registers (Address 8-Ah) Alarm_W Minute Register (Address 8h) WM40 WM20 WM10 (For Writing) WM40 WM20 WM10 (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) Alarm_W Hour Register (Address 9h) WH20 WH10 (For Writing)
  • Page 25 R2061 series Example of Alarm Time Setting Alarm Day-of-week 12-hour mode 24-hour mode Preset alarm time Sun. Mon. Tue. Wed. Th. Fri. Sat. min. min. min. min. WW0 WW1 WW2 WW3 WW4 WW5 WW6 00:00 a.m. on all days 01:30 a.m. on all days 11:59 a.m.
  • Page 26 R2061 series Interfacing with the CPU • DATA TRANSFER FORMATS (1) Timing Between CE Pin Transition and Data Input / Output The R2061 adopts a 3-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input/Output) pins to receive and send data to and from the CPU.
  • Page 27 R2061 series (2) Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to specify in the Address Pointer a head address with which data transfer is to be commenced from the host.
  • Page 28 R2061 series (2) Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the transfer format register.
  • Page 29 R2061 series (2) Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register.
  • Page 30 R2061 series • Considerations in Reading and Writing Time Data under special condition Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits.
  • Page 31 R2061 series Good Example Any address other than addresses 0h to 6h permits of immediate reading or writing without Time span of 31μs or more requiring a time span of 31 μs. DATA DATA DATA DATA Address Pointer Reading from...
  • Page 32 R2061 series Configuration of Oscillation Circuit and Correction of Time Count Deviations • Configuration of Oscillation Circuit Typical externally-equipped element X’tal : 32.768kHz OSCIN (R1=30kΩ typ) 32kHz Oscillator (CL=6pF to 8pF) Circuit Standard values of internal elements OSCOUT CG,CD 10pF typ The oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the VSS pin...
  • Page 33 R2061 series • Measurement of Oscillation Frequency OSCIN 32768Hz OSCOUT Frequency IN T R Counter * 1) The R2061 is configured to generate 1Hz clock pulses for output from the INTR pin by setting (00XX0011) at address Eh. * 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit.
  • Page 34 R2061 series depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ±20, and ±50ppm depending on the degree of their oscillation frequency variations. * 2) Basically, Model R2061 is configured to cause frequency variations on the order of ±5 to ±10ppm at 25°C.
  • Page 35 R2061 series • Oscillation Adjustment Circuit The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation Adjustment Register is set to 0, R2061 varies number of 1-second clock pulses once per 20 seconds.
  • Page 36 R2061 series (3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss) When DEV=0: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency × 3.051 × 10 ≈ (Oscillation Frequency – Target Frequency) × 10...
  • Page 37 2. Access to R2061 at random, or synchronized with external clock that has no relation to R2061, or synchronized with periodic interrupt in pulse mode. 3. Access to R2061 more than 2 times per each second on average. For more details, please contact to Ricoh. • How to evaluate the clock gain or loss The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds or 60 seconds.
  • Page 38 R2061 series Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring • PON, , and VDET The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses.
  • Page 39 R2061 series Threshold voltage (2.1V or 1.35V) 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag ( XST ) VDD supply voltage monitor flag (VDET) VDET←0 VDET←0 VDET←0 Internal initialization Internal initialization XST ←1 XST ←1 XST ←1 period (1 to 2 sec.) period (1 to 2 sec.)
  • Page 40 R2061 series • Voltage Monitoring Circuit R2061 incorporates two kinds of voltage monitoring function. These are shown in the table below. VCC Voltage Monitoring VCC Voltage Monitoring Circuit Circuit (VDET) Purpose CPU reset output Back-up battery checker Monitoring supply voltage...
  • Page 41 R2061 series The VCC supply voltage monitor circuit operates always. When VCC rising over +V , SW1 turns on, and SW2 DET1 turns off. And t after rising VCC, VDCC outputs OFF(H). But when oscillation is halt, VCC outputs DELAY OFF(H) t after oscillation starting.
  • Page 42 R2061 series Alarm and Periodic Interrupt The R2061 incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the INTR pin as described below. (1) Alarm Interrupt Circuit...
  • Page 43 R2061 series • Alarm Interrupt The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0.
  • Page 44 R2061 series • Periodic Interrupt Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%.
  • Page 45 R2061 series CTFG Bit IN TR Pin Setting CTFG bit to 0 Setting CTFG bit to 0 (Increment of (Increment of (Increment of second counter) second counter) second counter) *1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: Pulse Mode: The “L”...
  • Page 46 R2061 series Typical Applications • Typical Power Circuit Configurations The case of back-up by The case of back-up by The case of back-up by capacitor or secondary battery primary battery capacitor or secondary battery (Charging voltage is equal to CPU...
  • Page 47 R2061 series • Connection of CIN pin Please connect capacitor over 0.1μF between CIN and VSS pin. • Connection of INTR VDCC The INTR and VDCC pins follow the N-channel open drain output logic and contains no protective diode on the power supply side.
  • Page 48 R2061 series Typical Characteristics • Time keeping current (I ) vs. Supply voltage (V (Topt=25°C) Test Circuit OSCIN OSCOUT INTR VDCC 0.1μF SCLK 0.1μF • Stand-by current (I ) vs. Supply voltage (V (Topt=25°C) Test circuit OSCIN OSCOUT INTR VDCC 0.1μF...
  • Page 49 R2061 series • Stand-by current (I ) vs. Operating Temperature (Topt) =3V) Test circuit OSCIN OSCOUT INTR VDCC 0.1μF SCLK 0.1μF Operating temperature (Celsius) • CPU access current vs. SCLK clock frequency (kHz) (Topt=25°C) 1000 SCL clock frequency (KHz) •...
  • Page 50 R2061 series • Frequency deviation (Δf/f0) vs. Supply voltage (V (Topt=25°C) V =3V as standard Test circuit OSCIN OSCOUT INTR Frequency VDCC counter 0.1μF SCLK 0.1μF VCC/VSB(v) • Frequency deviation (Δf/f0) vs. CGOUT (Topt=25°C, V =3V)CGOUT=0pF as standard Test circuit...
  • Page 51 R2061 series • VCC-VDD(V ) vs. Output load current (I DDOUT1 OUT1 (Topt=25°C) Test circuit OSCIN -0.1 OSCOUT INTR -0.2 VDCC -0.3 =2.5V -0.4 =2.0V 0.1μF -0.5 SCLK 0.1μF Output load current IOUT1(mA) • VSB-VDD(V ) vs. Output load current (I...
  • Page 52 R2061 series Typical Software-based Operations • Initialization at Power-on Start Power-on PON=1? VDET=0? Set Oscillation Adjustment Register and Control Register 1 and 2, etc. Warning Back-up Battery Run-down *1) After power-on from 0 volt, the process of internal initialization require a time span on 1sec, so that access should be done after VDCC turning to OFF(H).
  • Page 53 R2061 series • Reading Time and Calendar Data (1) Ordinary Process of Reading Time and Calendar Data *1) When reading to clock and calendar counters, do not insert CE=L until all times from second to year have been read to CE←H...
  • Page 54 R2061 series (3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading.
  • Page 55 R2061 series • Interrupt Process (1) Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. Generate Interrupt to CPU *2) This step is intended to set the CTFG bit to 0...
  • Page 56 R2061 series (2) Alarm Interrupt WALE or DALE ← 0 *1) This step is intended to once disable the alarm Set Alarm Min., Hr., and Day-of-week Registers interrupt circuit by setting the WALE or DALE bits to 0 in anticipation of the coincidental occurrence...
  • Page 57 ■Ricoh awarded ISO 14001 certification. ■Ricoh presented with the Japan Management Quality Award for 1999. The Ricoh Group was awarded ISO 14001 certification, which is an international standard for Ricoh continually strives to promote customer satisfaction, and shares the achievements environmental management systems, at both its domestic and overseas production facilities.

This manual is also suitable for:

R2061k01-e2R2061k03-e2R2061s02-e2