AT&T Bell System 1A Manual page 24

$ECTION
-252~ 129~
100
seconds allowed for the scan period, if a EOS signal
has not been received during the scan period, an
EOS failure signal is transmitted to the channel
status indication logic (Fig. 13). At the end of
the completed scan cycle, an alarm indicator reset
signal is transmitted to the channel status indication
logic. These signals are used by the channel status
indication logic to provide visual indication of EOS
failt~re. The alarm remains until manually cleared.
3.43
To obtain data from each channel as it is
addressed, an interrogate signal must be
transmitted. This signal originates in the scan
cycle control logic from which it is transmitted to
the data set.
3.44
The scan cycle control logic resets the group
counter when an EOS signal (Fig. 15) is
received. If no EOS signal is received, the scan
cycle control logic resets the group counter at the
beginning of the next 6-second scan period.
3.45
The status of the group counter represents
the number of the group for which data is
being received. Undecoded group data is supplied
to the memory address gates. During scan cycles
(AM is true), the group data determines five bits
of the memory address. The group counter is reset
at the EOS period. Thus, the first data received
from a newly addressed remote scanner channel is
assumed to be from the first group of lines
associated with that channel. During the scan
period, the group counter is advanced each time
that an EOG signal is received along with the line
status data. This allows groups of arbitrary sizes.
Clocking of the group counter is implemented by
the memory execute and group advance control
logic. This logic enables the memory for one scan
digit cycle each time that a new data character is
received, after each time that a new data character
is received, and after time has been allowed for
the new character data to reach a steady state.
The memory execute signal activates the memory
for this cycle. At the end of this cycle, if the
latest received character included the EOG signal,
then the group counter is advanced.
3.46
When data is to be transferred from memory
to the output register, the memory execute
signal term is also required to activate the off-line
memory during print digit cycles. In this case
the store term (Fig. 12, sheet 2) and the KDC
term received from the print control logic (Fig. 12,
sheet 1) enable the generation of the memory
Page 24
execute term. The store term designates the print
bit time during which data is transferred into the
output register. The KDC term designates coincidence
between the print digit status and the status of
the scan digit counter (which provides the digit
memory address bits in the print and scan modes).
3.47
The memory read enable term (Fig. 14, sheet
2) is generated during the M digit cycle
when a transfer of data from the memory to the
output register (via the adder register) is being
accomplished. This term is used in generating
the strobe term that transfers data from the adder
register into the output register.
DECODER AND ADDER LOGIC
3.48
At the start of each P cycle, the adder
register is reset by bit and process timing
terms (Fig. 15) from the scan cycle control logic
(Fig. 14, sheet 2). The first data received by the
adder register after it is reset is from the memory.
This appears on the data outline from the memory
control logic and is applied to appropriate stages
of the register under the control of bit and process
timing terms from the scan control logic (Fig. 14,
sheet 2).
3.49
The second source of data for the adder
register is the carry flip-flop (Fig. 15); If
the carry flip-flop is set, a clock input pulse is
gated to the adder register via transfer gates under
the control of bit and process timing terms. At
the time that the carry bit is clocked into the adder
register, it is also applied to the carry flip-flop via
carry reset gates (Fig. 15) which senses the status
of the adder register. If the adder register is
holding a 9 and receives a carry input, then a new
carry must be generated at this time. Thus, under
this condition, the resetting of the carry flip-flop
is inhibited. Otherwise, the carry flip-flop is reset
at the time that the carry bit is clocked into the
adder register.
3.50
The third source of data for the adder
register are the decoders which receive data
from the 14 loop closure inputs from the data set
via line filters. During scanning mode cycles when
this data is being received, it is applied as the
clock input to the adder register via transfer gates
that are controlled by digit, bit, and process timing
terms (Fig. 14, sheet 1). The digit terms limit
the transfer to the least significant digit period
since higher-order digit periods are used to
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