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Intel 8253 Manual

Intel 8253 Manual

Programmable interval timer

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Page 12 Version 4 of the ARM archi- tecture. It provides a fourfold increase in performance over the ARM7 Thumb cores. Intel now produces and develops StrongARM, which is available as the stan- dard SA-110 processor and as part of custom logic products.
Page 13 ARM processors (continued) flush-all and flush-single-entry functions, and the instruc- Special on-chip peripherals: The ARM7 Thumb and ARM9 tion TLB supports only the flush-all function. Thumb processor cores have integrated EmbeddedICE logic, Power management: All the ARM processor cores and allowing you to debug the core via a JTAG interface.
Page 14 SMMs to reduce chip power dissipation. Integrated versions includes DOS and windowed OSs and a variety of real-time of the 386, including Intel’s 386EX, have idle and power- OSs from small, royalty-free microkernels to feature-rich down modes: Idle discontinues CPU processing but keeps graphical-user-interface RTOSs.
Page 15 Most of the tool support for the 486 is tive and implements a write-through policy: Writes to cache the same as that for the 386. AMD, Intel, and National offer pass through to memory, which raises memory bandwidth. evaluation kits for each of their 486 processors. For example, The 486’s bus and cache implement a bus-snooping protocol...
Page 16 Fujitsu SPARClite Fujitsu based its MB8683x, or SPARClite, family on V8E spec, SPARC International’s (www.sparc.com) embed- CLOCK-GENERATOR INTEGER UNIT ded specification. The fami- CLOCK ly features a 32-bit ALU and uses a load/store architec- DATA ture with a register stack of BUS-INTERFACE ADDR 136 32-bit registers.
Page 17 Hitachi SuperH Series The SuperH Series comprises the SH-1, SH-2, SH-3, and SH-4 have the errant task corrupt other tasks or RTOS environ- series of RISC mPs, mCs, and ASIC cores. The SH-1, -2, and -3 ments. employ a fetch, decode, execute, memory-access, and write- Power management: Sleep mode discontinues CPU pro- back-to-register pipeline.
Page 18 hyperstone E1-32X The hyperstone E1-32X combines RISC and DSP technology in one core. The E1-32X has a load/store architec- ture built around a register set that includes 64 general-purpose local and LOAD X-DECODE 22 global registers. Local registers are 64 LOCAL, DECODE 22 GLOBAL Y-DECODE...
Page 19 IBM/Motorola PowerPC Serving as a base for a family of RISC chips, the PowerPC level parity checking. A locked cache typically supplies data derives its core architecture from the performance-opti- on a hit, but cache lines are not replaced on a miss. The 750 mized-with-enhanced-RISC (POWER) architecture.
Page 20 IBM/Motorola PowerPC IBM/Motorola PowerPC (continued) (continued) The 604e and 750 have separate memory-management diction. However, the architecture supports out-of-order exe- troller supports external bus masters. You can use software with external memories, other CPUs, and peripherals. The units (MMUs) for instructions and data. The MMUs support cution and in-order retirement, similar to other PowerPC programming to tune the timing for the interface control sig- SIU for the MPC505 and MPC509 differs from the one in the...
Page 21 EPROM. It supports both PC and Unix host envi- struction decoder, which decodes as many as four instruc- Intel based the i960Rx series I/O processors on the i960 Jx The standard R3000 memory-management unit includes a ronments. LSI offers a number of tools, including the Mini- tions per cycle.
Page 22 Mitsubishi M32Rx/D Motorola ColdFire (continued) The Mitsubishi M32Rx/D contains a 32-bit RISC CPU; as the four-times clock at 50%. The generated clock then feeds higher. For starters, the V3 core much as 4 Mbytes of on-chip DRAM, which Mitsubishi calls into a digital phase shifter to reduce the phase difference includes multiple clock domains “eRAM”;...
Page 23 Motorola MCore MCore uses a four-stage pipeline to execute two-thirds of its processor can take in an asynchronous interrupt and get to Although MCore has limited tool support, the tools that are Motorola also offers the MCore V1 evaluation system (EVS) 95 basic instructions in one clock.
Page 24 Motorola 680x0 Motorola built the 680x0 archi- tecture around 16 general regis- INTEGER UNIT ters with a 68000-compatible, orthogonal instruction set. The INSTRUCTION-FETCH CONTROLLER 680x0 has more registers than the original 68000. Motorola added INSTRUCTION INSTRUCTION GENERATE CACHE BRANCH the control registers to control the INSTRUCTION CACHE INSTRUCTION...
Page 25 Motorola 683xx For most of the 683xx family, Motorola combined a stripped- CPU32+) and as many as 12 programmable chip-selection down 68020 core with a 16-bit (32-bit for CPU32+) on-chip lines. The single-chip Integration Module II allows users to InterModule Bus, which links the CPU with a device’s com- select 32-kHz or 4-MHz clock crystals.
Page 26 NEC V800 Siemens Tricore NEC’s V800 Series mCs are available as cores The Siemens Tricore architecture represents the industry’s bit-reversed indexing for FFTs. You must align the start of the and standard products. All core versions trend toward a blurring of the distinction between micro- circular buffer to a multiple of the data size, which the contain the same peripherals as those in controllers and DSPs (see “Microprocessor and DSP tech-...
Page 27 Pentium, comes in a single-edge-contact car- The processor dispatches mops from anywhere or in any order tridge with a 512-kbyte L2 cache. This year, Intel introduced within the reservation station. its Celeron and Pentium II Xeon processors. Celeron, which...
Page 28 Each BTB entry integrates the target address with history feeds the instruction-decode stage. The instruction decoder BYTE QUEUE and operation bits. Intel claims that a correctly predicted issues as many as two complex x86 instructions per cycle. branch takes one pipeline cycle and doesn’t cause a pipeline During decoding, the decoder examines the resource require- bubble.
Page 29 Sun microSPARC Sun built the microSPARC processors around a large, multiported register INST [31:0] file that divides into a small set of PLL CLOCK DPC [31:2] global registers for holding global GENERATOR INTEGER UNIT FP_DOUT [63:0] variables and sets of overlapping reg- ister windows.
Page 30 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make...
Page 31: Table Of Contents
Intel387 SX Math CoProcessor CONTENTS CONTENTS PAGE PAGE 1 0 PIN ASSIGNMENT 4 0 HARDWARE SYSTEM INTERFACE 1 1 Pin Description Table 4 1 Signal Description 2 0 FUNCTIONAL DESCRIPTION 4 1 1 Intel386 CPU Clock 2 2 1 Feature List (CPUCLK2) 2 2 Math CoProcessor Architecture 4 1 2 Intel387 Math CoProcessor...
Page 32 CONTENTS CONTENTS PAGE PAGE 4 4 Bus Cycles 7 0 ELECTRICAL 4 4 1 Intel387 SX Math CHARACTERISTICS CoProcessor Addressing 7 1 Absolute Maximum Ratings 4 4 2 CPU Math CoProcessor 7 2 D C Characteristics Synchronization 7 3 A C Characteristics 4 4 3 Synchronous Asynchronous Modes 8 0 Intel387 SX MATH COPROCESSOR...
Page 33 Output Signals CoProcessor Block Figure 7-4 Input and I O Signals Diagram Figure 7-5 RESET Signal Figure 3-1 Intel 386 SX CPU and Figure 7-6 Float from STEN Intel387 Math CoProcessor Register Set Figure 7-7 Other Parameters Figure 3-2 Status Word...
Page 34 Intel387 SX MATH COPROCESSOR include V and V planes for power distribution 1 0 PIN ASSIGNMENT and all V and V pins must be connected to the appropriate plane The Intel387 SX Math CoProcessor pinout as viewed from the top side of the component is shown NOTE in Figure 1-1 V and V...
Page 35: 1 Pin Description Table
Intel387 SX MATH COPROCESSOR 1 1 Pin Description Table The following table lists a brief description of each pin on the Intel387 SX Math CoProcessor For a more complete description refer to Section 4 1 Sig- nal Description The following definitions are used in these descriptions The signal is active LOW Input Signal...
Page 36: 0 Functional Description
Intel387 SX MATH COPROCESSOR Expands Intel386 SX CPU data types to include 2 0 FUNCTIONAL DESCRIPTION 32-bit 64-bit and 80-bit Floating Point 32-bit and 64-bit Integers and 18 Digit BCD Operands The Intel387 SX Math CoProcessor is designed to support the Intel386 SX Microprocessor and effec- Directly extends the Intel386 SX CPU Instruction tively extend the CPU architecture by providing fast Set to trigonometric logarithmic exponential...
Page 37: 3 Power Management
Dynamic Mode is when the device is executing an ware emulation methods with reduced resolution instruction Using Intel’s CHMOS IV technology the and accuracy The performance of the Intel387 SX Intel387 SX Math CoProcessor draws considerably...
Page 38: 0 Programming Interface
Intel387 SX MATH COPROCESSOR Integer Transfers 3 0 PROGRAMMING INTERFACE FILD Load (convert from) Integer (word short The Intel387 SX Math CoProcessor effectively ex- long) tends to an Intel386 Microprocessor system addi- FIST Store (convert to) Integer (word short) tional instructions registers data types and inter- FISTP Store (convert to) Integer and pop (word rupts specifically designed to facilitate high-speed short long)
Page 39: 1 3 Comparison Instructions
Intel387 SX MATH COPROCESSOR Other Operations 3 1 4 TRANSCENDENTAL INSTRUCTIONS FSQRT Square Root This group of the Intel387 operations includes trigo- FSCALE Scale nometric inverse trigonometric logarithmic and ex- FPREM Partial Remainder ponential functions The transcendental operate on the top one or two stack elements and they return FPREM1 IEEE standard partial remainder their results to the stack The trigonometric opera-...
Page 40: 1 6 Processor Instructions
Intel387 SX MATH COPROCESSOR FRSTOR Restore State 3 1 6 PROCESSOR INSTRUCTIONS (ADMINISTRATIVE) FINCSTP Increment Stack pointer FDECSTP Decrement Stack pointer FINIT Initialize Math CoProcessor FFREE Free Register FLDCW Load Control Word FNOP No Operation FSTCW Store Control Word FWAIT Report Math CoProcessor Error FLDCW Load Status Word...
Page 41: 2 1 Status Word (Sw) Register
Intel387 SX MATH COPROCESSOR Bit 7 is the error summary (ES) status bit This bit is 3 2 1 STATUS WORD (SW) REGISTER set if any unmasked exception bit is set it is clear The 16-bit status word (in the status register) shown otherwise If this bit is set the ERROR signal is in Figure 3-2 reflects the overall state of the Math...
Page 42: Table 3-1 Condition Code Interpretation
Intel387 SX MATH COPROCESSOR Table 3-1 Condition Code Interpretation Instruction C0 (S) C3 (Z) C1 (A) C2 (C) FPREM FPREM1 Three least significant bits Reduction (see Table 3-2) of quotient complete incomplete or O U FCOM FCOMP FCOMPP FTST Result of comparison Operand is not Zero FUCOM FUCOMP...
Page 43: Table 3-2 Condition Code Interpretation After Fprem And Fprem1 Instructions
Intel387 SX MATH COPROCESSOR Table 3-2 Condition Code Interpretation after FPREM and FPREM1 Instructions Condition Code Interpretation after FPREM and FPREM1 Incomplete Reduction further interation required for complete reduction Q MOD8 Complete Reduction C0 C3 C1 contain three least significant bits of quotient Table 3-3 Condition Code Resulting from Comparison Order Operand...
Page 44: 2 2 Control Word (Cw) Register
Intel387 SX MATH COPROCESSOR The precision control (PC) field (bits 9 – 8) can be 3 2 2 CONTROL WORD (CW) REGISTER used to set the Math CoProcessor internal oper- The Math CoProcessor provides the programmer ating precision of the significand at less than the with several processing options that are selected by default of 64 bits (extended precision) This can loading a control word from memory into the control...
Page 45: 2 3 Data Register
Intel387 SX MATH COPROCESSOR pal function of the tag word is to optimize the Math 3 2 3 DATA REGISTER CoProcessor’s performance and stack handling by Intel387 SX Math CoProcessor data register set making it possible to distinguish between empty and consists of eight registers (R0–...
Page 46: Figure 2-1 Intel387 Sx Math
Intel387 SX MATH COPROCESSOR 32-BIT PROTECTED MODE FORMAT RESERVED CONTROL WORD RESERVED STATUS WORD RESERVED TAG WORD IP OFFSET 00000 OPCODE CS SELECTOR 10 0 DATA OPERAND OFFSET RESERVED OPERAND SELECTOR Figure 3-5 Instruction and Data Pointer Image in Memory 32-Bit Protected-Mode Format 16-BIT PROTECTED MODE FORMAT CONTROL WORD STATUS WORD...
Page 47: 3 Data Types
Intel387 SX MATH COPROCESSOR 16-BIT REAL-ADDRESS MODE AND VIRTUAL 8086 MODE FORMAT CONTROL WORD STATUS WORD TAG WORD INSTRUCTION POINTER 15 0 IP19 16 OPCODE 10 0 OPERAND POINTER 15 0 DP 19 16 0 0 0 0 0 0 0 0 0 0 0 Figure 3-8 Instruction and Data Pointer Image in Memory 16-Bit Real-Mode Format 3 3 Data Types 3 4 Interrupt Description...
Page 48: Table 3-6 Intel387 Sx Math Coprocessor Data Type Representation In Memory
Intel387 SX MATH COPROCESSOR Table 3-6 Intel387 SX Math CoProcessor Data Type Representation in Memory 240225 –23 NOTES Sign bit (0 positive 1 negative) Decimal digit (two per byte) Bits have no significance Math CoProcessor ignores when loading zeros when storing Position of implicit binary point Integer bit of significand stored in temporary real implicit in single and double precision 6 Exponent Bias (normalized values)
Page 49: Table 3-7 Cpu Interrupt Vectors
Intel387 SX MATH COPROCESSOR Table 3-7 CPU Interrupt Vectors Reserved for Math CoProcessor Interrupt Cause of Interrupt Number An ESC instruction was encountered when EM or TS of CPU control register zero (CR0) was set EM 1 indicates that software emulation of the instruction is required When TS is set either an ESC or WAIT instruction causes interrupt 7 This indicates that the current Math CoProcessor context may not belong to the current task In a protected-mode system an operand of a coprocessor instruction wrapped around an...
Page 50: Sx Math Coprocessor
WAIT) after RESET The FNINIT is not strictly re- the assembler and compilers for high-level lan- quired for the Intel386 software but Intel recom- guages All Intel386 Microprocessor development mends its use to help ensure upware compatibility...
Page 51: 1 Signal Description
Intel387 SX MATH COPROCESSOR also clocks the data interface and control unit and 4 1 Signal Description the floating point unit of the Math CoProcessor This pin requires CMOS-level input The signal on this pin In the following signal descriptions the Intel387 SX is divided by two to produce the internal clock signal Math CoProcessor pins are grouped by function as shown by Table 4-1 Table 4-1 lists every pin by its...
Page 52: Clock 2 (Numclk2)
Intel387 SX MATH COPROCESSOR 4 1 3 CLOCKING MODE (CKM) 4 1 5 PROCESSOR REQUEST (PEREQ) This pin is strapping option When it is strapped to When active this pin signals to the CPU that the (HIGH) the Math CoProcessor operates in syn- Math CoProcessor is ready for data transfer to from chronous mode when strapped to V (LOW) the...
Page 53: 1 11 Bus Ready Input (Ready )
Intel387 SX MATH COPROCESSOR 4 1 11 BUS READY INPUT (READY ) 4 1 14 MATH COPROCESSOR SELECT 1 (NPS1 ) This input indicates to the Math CoProcessor when a CPU bus cycle is to be terminated It is used by the When active (along with STEN and NPS2) in the first bus control logic to trace bus activities Bus cycles period of a CPU bus cycle this signal indicates that...
Page 54: 2 System Configuration
Intel387 SX MATH COPROCESSOR The CPU and Math CoProcessor share the same 4 2 System Configuration reset signals They may also share the same clock input however for greatest performance The Intel387 SX Math CoProcessor is designed to an external oscillator may be needed interface with the Intel386 SX Microprocessor as shown by Figure 4-1 A dedicated communication The corresponding Busy...
Page 55: 3 Math Coprocessor Architecture
Intel387 SX MATH COPROCESSOR FIFO or the instruction decoder The instruction de- 4 3 Math CoProcessor Architecture coder decodes the ESC instructions sent to it by the CPU and generates controls that direct the data flow As shown in Figure 2-1 Block Diagram the Intel387 in the FIFO It also triggers the microinstruction se- SX Math CoProcessor is internally divided into four quencer that controls execution of each instruction...
Page 56: 4 1 Intel387 Sx Math Coprocessor Addressing
Intel387 SX MATH COPROCESSOR value has already been written or read by the Math 4 4 1 INTEL387 SX MATH COPROCESSOR CoProcessor before the CPU reads or changes the ADDRESSING value The NPS1 NPS2 and CMD0 signals allow the Math CoProcessor to identify which bus cycles are Once it has started to execute a numerics instruction intended for the Math CoProcessor The Math Co- and has transferred and operands from the CPU the...
Page 57: 1 Non-Pipelined Bus Cycles
Intel387 SX MATH COPROCESSOR During this first CLK period the Math CoProcessor READYO output of the Math CoProcessor indi- also examines the W R input signal to determine cates when a Math CoProcessor bus cycle may be whether the cycle is a read or a write cycle and ex- terminated if no extra wait states are required For all amines the CMD0 input to determine whether an...
Page 58: 1 2 Read Cycle
Intel387 SX MATH COPROCESSOR 240225 – 8 Cycles 1 2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads Cycles 3 4 represent part of the operand transfer cycle for a store operation Cycles 1 2 could repeat here or T states for various non-operand transfer cycles and overhead...
Page 59: 3 Mixed Bus Cycles
Intel387 SX MATH COPROCESSOR during the transitions to or from that state the only because READY is asserted before the earliest difference between a pipelined and a non-pipelined possible assertion of ADS for the next cycle ) cycle is the manner of changing from one state to another The exact activities during each state are Figure 5-4 shows pipelined write and read cycles detailed in the previous section ‘‘Non-pipelined Bus...
Page 60: Figure 5-4 Pipelined Cycles With Wait States
Intel387 SX MATH COPROCESSOR 240225 –10 NOTE 1 Cycles between operand write to the Math CoProcessor and storing result Figure 5-4 Pipelined Cycles with Wait States...
Page 61: 4 Busy And Pereq Timing Relationship
Intel387 SX MATH COPROCESSOR tion upon completion of the instruction PEREQ is 5 4 BUSY and PEREQ Timing activated within this interval If ERROR is ever as- Relationship serted it would be asserted at least six CPUCLK2 periods after the deactivation of PEREQ and would Figure 5-5 shows the activation of BUSY at the be deasserted at least six CPUCLK2 periods before...
Page 62: 0 Package Specifications
7 0 ELECTRICAL CHARACTERISTICS The following specifications represent the targets of the design effort They are subject to change without notice Contact your Intel representative to get the most up-to-date values 7 1 Absolute Maximum Ratings NOTICE This is a production data sheet The specifi-...
Page 63: 2 D C Characteristics
Intel387 SX MATH COPROCESSOR 7 2 D C Characteristics Table 7-1 D C Specifications T 0 C to 100 C V Symbol Parameter Units Test Conditions Input LO Voltage (Note 1) Input HI Voltage (Note 1) CPUCLK2 and NUMCLK2 Input LO Voltage CPUCLK2 and NUMCLK2 Input HI Voltage Output LO Voltage...
Page 64: 3 A C Characteristics
Intel387 SX MATH COPROCESSOR 7 3 A C Characteristics Table 7-2a Timing Requirements of the Bus Interface Unit 0 C to 100 C V 10% (All measurements made at 1 5V unless otherwise specified) 16 MHz – 33 MHz 25 MHz Test Refer to Symbol...
Page 65: Table 7-2B Timing Requirements Of The Execution Unit
Intel387 SX MATH COPROCESSOR Table 7-2b Timing Requirements of the Execution Unit (Asynchronous Mode CKM 16 MHz – 33 MHz 25 MHz Test Refer to Symbol Parameter Conditions Figure (ns) (ns) (ns) (ns) NUMCLK2 Period 2 0V NUMCLK2 High Time 6 25 2 0V NUMCLK2...
Page 66: Figure 7-1A Typical Output Valid Delay Vs Load Capacitance At Max Operating Temperature
Intel387 SX MATH COPROCESSOR 240225 –12 NOTE Typical part under worst-case conditions Figure 7-1a Typical Output Valid Delay vs Load Capacitance at Max Operating Temperature 240225– 13 240225 –14 NOTE Typical part under worst-case conditions Figure 7-1b Typical Output Slew Time vs Load Capacitance at Max Operating Temperature 240225 –15 Figure 7-1c Maximum I vs Frequency...
Page 67: Figure 7-2 Cpuclk2 Numclk2
Intel387 SX MATH COPROCESSOR 240225 –16 Figure 7-2 CPUCLK2 NUMCLK2 Waveform and Measurement Points for Input Output 240225 –17 Figure 7-3 Output Signals...
Page 68: Figure 7-4 Input And I O Signals
Intel387 SX MATH COPROCESSOR 240225 –18 Figure 7-4 Input and I O Signals 240225 –19 NOTE The second internal processor phase following RESET high to low transition is PH2 Figure 7-5 RESET Signal...
Page 69: Figure 7-6 Float From Sten
Intel387 SX MATH COPROCESSOR 240225 – 20 Figure 7-6 Float from STEN 240225 –21 In NUMCLK2’s or last operand NOTE 1 Memory read (operand) cycle is not shown Figure 7-7 Other Parameters...
Page 70: 0 Intel387 Sx Math Coprocessor Instruction Set
Intel387 SX MATH COPROCESSOR grammer’s Reference Manual for the CPU) SIB 8 0 INTEL387 SX MATH (Scale Index Base) byte and DISP (displacement) COPROCESSOR INSTRUCTION are optionally present in instructions that have MOD and R M fields Their presence depends on the val- ues of MOD and R M as for instructions of the CPU Instructions for the Intel387 SX Math CoProcessor assume one of the five forms shown in Table 8-1 In...
Page 71 Intel387 SX MATH COPROCESSOR Encoding Clock Count Range Instruction Optional 32-Bit 32-Bit 64-Bit 16-Bit Byte 0 Byte 1 Bytes 2 – 6 Real Integer Real Integer DATA TRANSFER Load Integer real memory to ST(0) ESC MF 1 MOD 000 R M SIB DISP 11 –20 28 –44...
Page 72 Intel387 SX MATH COPROCESSOR Encoding Clock Count Range Instruction Optional 32-Bit 32-Bit 64-Bit 16-Bit Byte 0 Byte 1 Bytes 2 – 6 Real Integer Real Integer ARITHMETIC FADD Integer real memory to ST(0) ESC MF 0 MOD 000 R M SIB DISP 14 –31 36 –58...
Page 73 Intel387 SX MATH COPROCESSOR Encoding Clock Count Range Instruction Optional 32-Bit 32-Bit 64-Bit 16-Bit Byte 0 Byte 1 Bytes 2 – 6 Real Integer Real Integer CONSTANTS FLDZ Load 0 0 to ST(0) ESC 001 1110 1110 10 –17 FLD1 Load 1 0 to ST(0) ESC 001...
Page 74: Appendix Aintel387 Sx Math Coprocessor Compatibility
Intel387 SX MATH COPROCESSOR APPENDIX A INTEL387 SX MATH COPROCESSOR COMPATIBILITY A 1 8087 80287 Compatibility This section summarizes the differences between the Intel387 SX Math CoProcessor and the 80287 Math CoProcessor Any migration from the 8087 directly to the Intel387 SX Math CoProcessor must also take into account the differences between the 8087 and the 80287 Math CoProcessor as listed in Appendix B Many changes have been designed into the Intel387 SX Math CoProcessor to directly support the IEEE standard in hardware These changes result in increased performance by eliminating the need for software...
Page 75: A 1 2 Exceptions
Intel387 SX MATH COPROCESSOR A 1 2 EXCEPTIONS A number of differences exist due to changes in the IEEE standard and to functional improvements to the architecture of the Intel387 SX Math CoProcessor 1 When the overflow or underflow exception is masked the Intel387 SX Math CoProcessor differs from the 80287 in rounding when overflow or underflow occurs The Intel387 SX Math CoProcessor produces results that are consistent with the rounding mode 2 When the underflow exception is masked the Intel387 SX Math CoProcessor sets its underflow flag only if...
Page 76: Appendix B Compatibility
Intel387 SX MATH COPROCESSOR APPENDIX B COMPATIBILITY BETWEEN THE 80287 AND 8087 MATH COPROCESSOR The 80286 80287 operating in Real Address mode will execute 8086 8087 programs without major modifica- tion However because of differences in the handling of numeric exceptions by the 80287 Math CoProcessor and the 8087 Math CoProcessor exception handling routines may need to be changed This appendix summa- rizes the differences between the 80287 Math CoProcessor and the 8087 Math CoProcessor and provides details showing how 8087 8087 programs can be ported to the 80286 80287...
Page 77: Math Coprocessor
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make...
Page 78 80C187 Figure 1 80C187 Block Diagram...
Page 79: Programming Interface
80C187 80C187 Data Registers SIGN EXPONENT SIGNIFICAND CONTROL REGISTER INSTRUCTION POINTER STATUS REGISTER DATA POINTER TAG WORD Figure 2 Register Set CPU automatically controls the 80C187 whenever a FUNCTIONAL DESCRIPTION numerics instruction is executed All physical memo- ry and virtual memory of the CPU are available for The 80C187 Math Coprocessor provides arithmetic storage of the instructions and operands of pro- instructions for a variety of numeric data types It...
Page 80: Register Set
80C187 Numeric Operands Register Set A typical NPX instruction accepts one or two oper- Figure 2 shows the 80C187 register set When an ands and produces one (or sometimes two) results 80C187 is present in a system programmers may In two-operand instructions one operand is the con- use these registers in addition to the registers nor- tents of an NPX register while the other may be a mally available on the CPU...
Page 81: Figure 3-2 Status Word
80C187 The 80C187 register set can be accessed either as Bit 15 the B-bit (busy bit) is included for 8087 com- a stack with instructions operating on the top one or patibility only It always has the same value as the two stack elements or as individually addressable ES bit (bit 7 of the status word) it does not indicate registers The TOP field in the status word identifies...
Page 82 80C187 270640 –3 ES is set if any unmasked exception bit is set cleared otherwise See Table 2 for interpretation of condition code TOP values Register 0 is Top of Stack Register 1 is Top of Stack Register 7 is Top of Stack For definitions of exceptions refer to the section entitled ‘‘Exception Handling’’...
Page 83 80C187 CONTROL WORD The NPX provides several processing options that are selected by loading a control word from memory into the control register Figure 5 shows the format and encoding of fields in the control word Table 2 Condition Code Interpretation Instruction C0(S) C3(Z)
Page 84 80C187 The low-order byte of this control word configures as the unbiased round to nearest even mode exception masking Bits 5 – 0 of the control word specified in the IEEE standard Rounding control contain individual masks for each of the six excep- affects only those instructions that perform tions that the 80C187 recognizes rounding at the end of the operation (and thus...
Page 85: Exception Handling
80C187 Table 5 Condition Code Defining Operand Class Value at TOP Unsupported Unsupported Normal Infinity Normal Infinity Empty Empty Denormal Denormal rupt The CPU return address pushed onto the stack INSTRUCTION AND DATA POINTERS of the exception handler points to an ESC instruction Because the NPX operates in parallel with the CPU (including prefixes) This instruction can be restarted any exceptions detected by the NPX may be report-...
Page 86 80C187 270640 –4 Precision Control Rounding Control 24 Bits (Single Precision) Round to Nearest or Even (Reserved) Round Down (toward 53 Bits (Double Precision) Round Up (toward 64 Bits (Extended Precision) Chop (Truncate toward Zero) The ‘‘infinity control’’ bit is not meaningful to the 80C187 To maintain compatibility with the 8087 this bit can be programmed however regardless of its value the 80C187 treats infinity in the affine sense ( Figure 5 Control Word CONTROL WORD...
Page 87: General Differences
FNINIT instruction (i e an FINIT without a essor Extension preceding WAIT) after RESET The FNINIT is not strictly required for 80C187 software but Intel The 80C187 differs from the 8087 with respect to recommends its use to help ensure upward compati-...
Page 88 80C187 80C186 automatically tests the BUSY line from the 2 The 80C187 Numeric Processor Extension sig- 80C187 Numeric Processor Extension to ensure that nals exceptions through a dedicated ERROR line the 80C187 Numeric Processor Extension has com- to the CPU The 80C187 error signal does not pleted its previous instruction before executing the pass through an interrupt controller (the 8087 INT next ESC instruction No explicit WAIT instructions...
Page 89 80C187 and exception When loading a signalling NaN (ST(0) and ST(1) contain the scaled and scaling FLD single double precision signals an invalid- operands respectively) operand exception FSCALE (0 % ) generates the invalid opera- 16 The 80C187 only generates quiet NaNs (as on tion exception the 8087) however the 80C187 distinguishes FSCALE (finite...
Page 90: Hardware Interface
80C187 HARDWARE INTERFACE In the following description of hardware interface an overbar above a signal name indicates that the ac- tive or asserted state occurs when the signal is at a low voltage When no overbar is present above the signal name the signal is asserted when at the high voltage level Signal Description...
Page 91 80C187 Table 8 PLCC Pin Cross-Reference Pin Name CERDIP Package PLCC Package BUSY CMD0 CMD1 ERROR No Connect 6 11 23 33 40 NPRD NPS1 NPS2 NPWR PEREQ RESET 3 9 13 37 40 1 3 10 15 42 1 4 10 30 36 38 2 4 12 34 41 43 Table 9 Output Pin Status during Reset System Reset (RESET)
Page 92: Processor Architecture
80C187 PEREQ is deactivated after the first three transfers data transfer involving the 80C187 occurs unless the and subsequently after every four transfers This sig- device is selected by these lines nal always goes inactive before BUSY goes inactive Command Selects (CMD0 and CMD1) Busy Status (BUSY) These pins along with the select pins allow the CPU When active this pin signals to the CPU that the...
Page 93: Floating-Point Unit
80C187 Table 10 Bus Cycles Definition NPS1 NPS2 CMD0 CMD1 NPRD NPWR Bus Cycle Type 80C187 Not Selected 80C187 Not Selected Opcode Write to 80C187 CW or SW Read from 80C187 Read Data from 80C187 Write Data to 80C187 Write Exception Pointers Reserved Read Opcode Status Reserved...
Page 94: Bus Operation
80C187 CPU NPX SYNCHRONIZATION OPCODE INTERPRETATION The pins BUSY PEREQ and ERROR are used for The CPU and the NPX use a bus protocol that various aspects of synchronization between the adapts to the numerics opcode being executed CPU and the NPX Only the NPX directly interprets the opcode Some of the results of this interpretation are relevant to the BUSY is used to synchronize instruction transfer...
Page 95: System Configuration
80C187 input signals to determine whether the cycle is a The 80C186 pin MCS3 NPS is connected to read or a write cycle and examines the CMD0 and NPS1 NPS2 is connected to V Note that if the CMD1 inputs to determine whether an opcode oper- 80C186 CPU’s DEN signal is used to gate exter- and or control status register transfer is to occur nal data buffers it must be combined with the...
Page 96 80C187 For exception handling compatible with the 80186 System Configuration for 80186 82188 8087 the 80C186 can be wired to recognize 80187-Compatible Exception Trapping exceptions through an external interrupt pin as Fig- ure 10 shows (Refer to the 80C186 Data Sheet for When the 80C187 ERROR output signal is connect- an explanation of the 80C186’s signals ) With this ed directly to the 80C186 ERROR input floating-...
Page 97: Electrical Data
80C187 ELECTRICAL DATA NOTICE This is a production data sheet The specifi- cations are subject to change without notice WARNING Stressing the device beyond the ‘‘Absolute Absolute Maximum Ratings Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the Case Temperature Under Bias (T 0 C to 85 C...
Page 98 80C187 AC Characteristics 0 C to 85 C V All timings are measured at 1 5V unless otherwise specified 12 5 MHz 16 MHz Test Symbol Parameter Conditions (ns) (ns) (ns) (ns) (t6) Data Setup to NPWR dvwh (t7) Data Hold from NPWR whdx (t8) NPRD Active Time...
Page 99: Clock Timings
80C187 Timing Responses All timings are measured at 1 5V unless otherwise specified 12 5 MHz 16 MHz Test Symbol Parameter Conditions (ns) (ns) (ns) (ns) (t27) NPRD Inactive to Data Float Note 2 rhqz (t28) NPRD Active to Data Valid Note 3 rlqv (t29)
Page 100 80C187 AC DRIVE AND MEASUREMENT AC SETUP HOLD AND DELAY TIME POINTS CLK INPUT MEASUREMENTS GENERAL 270640–9 270640 –10 AC TEST LOADING ON OUTPUTS 270640 –11 DATA TRANSFER TIMING (INITIATED BY CPU) 270640 –12...
Page 101 80C187 DATA CHANNEL TIMING (INITIATED BY 80C187) 270640 –13 ERROR OUTPUT TIMING 270640 –14 CLK RESET TIMING (CKM 270640 –15...
Page 102 80C187 CLK NPRD NPWR TIMING (CKM 270640 –16 CLK RESET TIMING (CKM 270640 –17 RESET must meet timing shown to guarantee known phase of internal divide by 2 circuits NOTE RESET NPWR NPRD inputs are asynchronous to CLK Timing requirements are given for testing purposes only to assure recognition at a specific CLK edge CLK NPRD NPWR TIMING (CKM 270640 –...
Page 103 80C187 DISP (displacement) is optionally present in instruc- 80C187 EXTENSIONS TO THE CPU’s tions that have MOD and R M fields Its presence INSTRUCTION SET depends on the values of MOD and R M as for in- structions of the CPU Instructions for the 80C187 assume one of the five forms shown in Table 12 In all cases instructions The instruction summaries that follow assume that...
Page 104 80C187 80C187 Extensions to the 80C186 Instruction Set Encoding Clock Count Range Instruction Byte Byte Optional 32-Bit 32-Bit 64-Bit 16-Bit Bytes 2 –3 Real Integer Real Integer DATA TRANSFER Load Integer real memory to ST(0) ESC MF 1 MOD 000 R M DISP 65 –72 67 –71...
Page 105 80C187 80C187 Extensions to the 80C186 Instruction Set (Continued) Encoding Clock Count Range Instruction Byte Byte Optional 32-Bit 32-Bit 64-Bit 16-Bit Bytes 2 –3 Real Integer Real Integer CONSTANTS (Continued) FLDL2E Load log (e) into ST(0) ESC 001 1110 1010 FLDLG2 Load log (2) into ST(0)
Page 106 80C187 80C187 Extensions to the 80C186 Instruction Set (Continued) Encoding Instruction Clock Count Range Byte Byte Optional Bytes 2 –3 TRANSCENDENTAL FCOS Cosine of ST(0) ESC 001 1111 1111 125 –774 FPTAN Partial tangent of ST(0) ESC 001 1111 0010 193 –499 FPATAN Partial arctangent...
Page 107: Integrated Circuits
INTEGRATED CIRCUITS 80C31/80C32 80C51 8-bit microcontroller family 128/256 byte RAM ROMless low voltage (2.7 V–5.5 V), low power, high speed (33 MHz) Product specification 2000 Aug 07 IC28 Data Handbook hilips Semiconductors...
Page 108: Selection Table
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) DESCRIPTION FEATURES The Philips 80C31/32 is a high-performance static 80C51 design 8051 Central Processing Unit fabricated with Philips high-density CMOS technology with operation –...
Page 109 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) 80C51/87C51 AND 80C31 ORDERING INFORMATION TEMPERATURE RANGE C VOLTAGE FREQ. DRAWING ROMless AND PACKAGE RANGE (MHz) NUMBER P80C31SBPN P80C31SBPN 0 to +70 Plastic Dual In line Package 0 to +70, Plastic Dual In-line Package...
Page 110: Block Diagram
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) BLOCK DIAGRAM P0.0–P0.7 P2.0–P2.7 PORT 0 PORT 2 DRIVERS DRIVERS RAM ADDR PORT 0 PORT 2 ROM/EPROM REGISTER LATCH LATCH STACK...
Page 111: Pin Configurations
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) LOGIC SYMBOL PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS XTAL1 ADDRESS AND DATA BUS XTAL2 T2EX EA/V PSEN Function Function Function ALE/PROG...
Page 112: Pin Descriptions
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) PIN DESCRIPTIONS PIN NUMBER MNEMONIC TYPE NAME AND FUNCTION Ground: 0 V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30...
Page 113 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Table 1. 8XC51/80C31 Special Function Registers DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET SYMBOL DESCRIPTION ADDRESS VALUE ACC* Accumulator...
Page 114: Oscillator Characteristics
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) OSCILLATOR CHARACTERISTICS For the 80C31 or 80C32, either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all XTAL1 and XTAL2 are the input and output, respectively, of an the SFRs but does not change the on-chip RAM.
Page 115 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Programmable Clock-Out TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in A 50% duty cycle clock can be programmed to come out on P1.0.
Page 116 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) (MSB) (LSB) EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 Symbol Position Name and Significance T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1.
Page 117 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable — — — — — — T2OE DCEN Symbol...
Page 118 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) (DOWN COUNTING RELOAD VALUE) TOGGLE EXF2 C/T2 = 0 OVERFLOW INTERRUPT C/T2 = 1 T2 PIN CONTROL COUNT DIRECTION 1 = UP 0 = DOWN...
Page 119 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Baud Rate Generator Mode under these conditions, a read or write of TH2 or TL2 may not be accurate.
Page 120 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Table 5. Timer 2 as a Timer T2CON MODE MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate...
Page 121 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) and 1 and exclude Slave 2 use address 1110 0100, since it is Upon reset SADDR (SFR address 0A9H) and SADEN (SFR necessary to make bit 2 = 1 to exclude slave 2.
Page 122 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) START DATA BYTE ONLY IN STOP MODE 2, 3 SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SCON SM0 / FE...
Page 123 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Interrupt Priority Structure An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal The 80C31 and 80C32 have a 6-source four-level interrupt or higher level priority is being serviced, the new interrupt will wait structure.
Page 124: Symbol Function
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) IP (0B8H) — — Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority SYMBOL FUNCTION IP.7...
Page 125 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Reduced EMI Mode Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC The AO bit (AUXR.0) in the AUXR register when set disables the DPTR instruction without affecting the WOPD or LPEP bits.
Page 126: Ac Electrical Characteristics
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) 1, 2, 3 ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 Storage temperature range –65 to +150 Voltage on EA pin to V...
Page 127: Dc Electrical Characteristics
Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) DC ELECTRICAL CHARACTERISTICS = 0 C to +70 C or –40 C to +85 C, V = 2.7 V to 5.5 V, V = 0 V (16 MHz devices) LIMITS TEST...
Page 128 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) DC ELECTRICAL CHARACTERISTICS = 0 C to +70 C or –40 C to +85 C, 33 MHz devices; 5 V 10%; V = 0 V LIMITS TEST...
Page 129 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) AC ELECTRICAL CHARACTERISTICS 1, 2, 3 = 0 C to +70 C or –40 C to +85 C, V = +2.7 V to +5.5 V, V = 0 V 16 MHz CLOCK...
Page 130 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) AC ELECTRICAL CHARACTERISTICS 1, 2, 3 = 0 C to +70 C or –40 C to +85 C, V = 5 V 10%, V = 0 V VARIABLE CLOCK...
Page 131 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always P – PSEN ‘t’...
Page 132 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) WHLH PSEN WLWH LLWL LLAX WHQX AVLL QVWX QVWH A0–A7 PORT 0 DATA OUT A0–A7 FROM PCL INSTR IN FROM RI OR DPL AVWL PORT 2...
Page 133 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) –0.5 +0.1V LOAD –0.1V TIMING 0.2V +0.9 REFERENCE LOAD POINTS 0.2V –0.1 –0.1V +0.1V LOAD 0.45V NOTE: NOTE: AC inputs during testing are driven at V –0.5 for a logic ‘1’...
Page 134 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) (NC) XTAL2 (NC) XTAL2 CLOCK SIGNAL XTAL1 CLOCK SIGNAL XTAL1 SU00719 SU00720 Figure 22. I Test Condition, Active Mode Figure 23.
Page 135 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 2000 Aug 07...
Page 136 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 2000 Aug 07...
Page 137 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 2000 Aug 07...
Page 138 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C31/80C32 128/256 byte RAM ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice.
Page 139: Programmable Interval Timer
Status Read-Back Command Standard Temperature Range The Intel 8254 is a counter timer device designed to solve the common timing control problems in microcom- puter system design It provides three independent 16-bit counters each capable of handling clock inputs up...
Page 140: Data Bus Buffer
General Real time clock Event-counter The 8254 is a programmable interval timer counter designed for use with Intel microcomputer systems Digital one-shot It is a general purpose multi-timing element that can Programmable rate generator be treated as an array of I O ports in the system...
Page 141: Control Word Register
8254 231164 – 3 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC COUNTER 0 COUNTER 1 COUNTER 2 The Read Write Logic accepts inputs from the sys- These three functional blocks are identical in opera- tem bus and generates control signals for the other tion so only a single Counter will be described The functional blocks of the 8254 A...
Page 142 8254 231164 –4 Figure 4 Block Diagram Showing Control Word Register and Counter Functions 231164 –5 Figure 5 Internal Block Diagram of a Counter...
Page 143: System Interface
8-bit internal bus Note that the CE itself select method Or it can be connected to the output cannot be read whenever you read the count it is of a decoder such as an Intel 8205 for larger sys- the OL that is being read tems...
Page 144 Read Write least significant byte first then most significant byte NOTE Don’t care bits (X) should be 0 to insure compatibility with future Intel products Figure 7 Control Word Format By contrast initial counts are written into the Coun- Since the Control Word Register and the three...
Page 145: Counter Latch Command
The second method uses the ‘‘Counter Latch Com- Don’t care bits (X) should be 0 to insure compatibility mand’’ Like a Control Word this command is written with future Intel products to the Control Word Register which is selected when A...
Page 146: Read-Back Command
8254 The selected Counter’s output latch (OL) latches the A0 A1 1 WR count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed) 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0 The count is then unlatched automatically and the OL returns to ‘‘following’’...
Page 147 8254 NULL COUNT bit D6 indicates when the last count COUNT and STATUS bits D5 D4 0 This is func- written to the counter register (CR) has been loaded tionally the same as issuing two separate read-back into the counting element (CE) The exact time this commands at once and the above discussions ap- happens depends on the Mode of the counter and is ply here also Specifically if multiple count and or...
Page 148: Mode 0 Interrupt On Terminal Count
8254 OUT will then go high and remain high until the CLK Mode Definitions pulse after the next trigger The following are defined for use in describing the After writing the Control Word and initial count the operation of the 8254 Counter is armed A trigger results in loading the CLK Pulse a rising edge then a falling edge in...
Page 149 8254 231164 –7 NOTE The following conventions apply to all mode timing diagrams 1 Counters are programmed for binary (not BCD) counting and for reading writing least significant byte (LSB) only 2 The counter is always selected (CS always low) 3 CW stands for ‘‘Control Word’’...
Page 150 8254 231164 –8 Figure 16 Mode 1 initial count has expired OUT goes low for the re- After writing a Control Word and initial count the mainder of the count Mode 3 is periodic the se- Counter will be loaded on the next CLK pulse This quence above is repeated indefinitely An initial allows the Counter to be synchronized by software count of N results in a square wave with a period of...
Page 151 8254 231164 –9 NOTE A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 new count Otherwise the new count will be loaded Odd counts OUT is initially high The initial count at the end of the current half-cycle minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeed- Mode 3 is implemented as follows...
Page 152 8254 231164 –10 NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3...
Page 153: Mode 4 Software Triggered Strobe
8254 initial count of N OUT does not strobe low until N MODE 4 SOFTWARE TRIGGERED STROBE 1 CLK pulses after the initial count is written OUT will be initially high When the initial count ex- pires OUT will go low for one CLK pulse and then If a new count is written during counting it will be go high again The counting sequence is ‘‘triggered’’...
Page 154: Mode 5 Hardware Triggered Strobe
8254 A trigger results in the Counter being loaded with the MODE 5 HARDWARE TRIGGERED STROBE initial count on the next CLK pulse The counting (RETRIGGERABLE) sequence is retriggerable OUT will not strobe low OUT will initially be high Counting is triggered by a for N 1 CLK pulses after any trigger GATE has rising edge of GATE When the initial count has ex-...
Page 155 8254 Operation Common to All Modes Signal Status Or Going Rising High Modes PROGRAMMING Disables Enables When a Control Word is written to a Counter all Counting Counting Control Logic is immediately reset and OUT goes to 1) Initiates a known initial state no CLK pulses are required for Counting this 2) Resets Output...
Page 156: Read Cycle
8254 ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi- cations are subject to change without notice Ambient Temperature Under Bias 0 C to 70 C WARNING Stressing the device beyond the ‘‘Absolute Storage Temperature 65 C to 150 C Maximum Ratings’’...
Page 157: Write Cycle
8254 A C CHARACTERISTICS 0 C to 70 C V 10% GND 0V (Continued) WRITE CYCLE 8254 8254-2 Symbol Parameter Unit Address Stable Before WR CS Stable Before WR Address Hold Time After WR WR Pulse Width Data Setup Time Before WR Data Hold Time After WR Command Recovery Time CLOCK AND GATE...
Page 158 8254 WAVEFORMS WRITE 231164 –13 READ 231164 –14...
Page 159 8254 WAVEFORMS (Continued) RECOVERY 231164 –15 CLOCK AND GATE 231164 –16 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 231164– 17 A C Testing Inputs are driven at 2 4V for a Logic ‘‘1’’ and 0 45V for a Logic ‘‘0 ’’...
Page 160: Frequency
16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one-shot and in many other applications The 82C54 is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption...
Page 161: Functional Description
The 82C54 is a programmable interval timer counter the 82C54 are designed for use with Intel microcomputer systems It is a general purpose multi-timing element that can Real time clock be treated as an array of I O ports in the system...
Page 162: Block Diagram
82C54 Block Diagram CONTROL WORD REGISTER The Control Word Register (see Figure 4) is selected DATA BUS BUFFER by the Read Write Logic when A 11 If the CPU then does a write operation to the 82C54 the This 3-state bi-directional 8-bit buffer is used to in- data is stored in the Control Word Register and is terface the 82C54 to the system bus (see Figure 3) interpreted as a Control Word used to define the...
Page 163 Back command ) select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys- The actual counter is labelled CE (for ‘‘Counting Ele- tems ment’’) It is a 16-bit presettable synchronous down...
Page 164: Operational Description
Binary Coded Decimal (BCD) Counter (4 Decades) Read Write most significant byte only Read Write least significant byte first then most significant byte NOTE Don’t care bits (X) should be 0 to insure compatibility with future Intel products Figure 7 Control Word Format...
Page 165: Write Operations
82C54 struction sequence is required Any programming Write Operations sequence that follows the conventions above is ac- ceptable The programming procedure for the 82C54 is very flexible Only two conventions need to be remem- A new initial count may be written to a Counter at bered any time without affecting the Counter’s pro- 1) For each Counter the Control Word must be...
Page 166 Don’t care bits (X) should be 0 to insure compatibility ting their corresponding bits D3 D2 D1 with future Intel products Figure 9 Counter Latching Command Format A0 A1 The selected Counter’s output latch (OL) latches the...
Page 167 82C54 count all but the first are ignored i e the count which will be read is the count at the time the first THIS ACTION CAUSES read-back command was issued A Write to the control Null count word register The read-back command may also be used to latch B Write to the count Null count...
Page 168: Mode Definitions
82C54 GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT Write into Counter 0 Write into Counter 1 After the Control Word and initial count are written to a Counter the initial count will be loaded on the next Write into Counter 2 CLK pulse This CLK pulse does not decrement the Write Control Word...
Page 169 82C54 If an initial count is written while GATE 0 it will MODE 1 HARDWARE RETRIGGERABLE still be loaded on the next CLK pulse When GATE ONE-SHOT goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has OUT will be initially high OUT will go low on the CLK already been done pulse following a trigger to begin the one-shot pulse...
Page 170 82C54 Writing a new count while counting does not affect MODE 2 RATE GENERATOR the current counting sequence If a trigger is re- This Mode functions like a divide-by-N counter It is ceived after writing a new count but before the end typicially used to generate a Real Time Clock inter- of the current period the Counter will be loaded with rupt OUT will initially be high When the initial count...
Page 171 82C54 OUT will be high for (N 1) 2 counts and low for 1) Writing the first byte has no effect on counting 1) 2 counts 2) Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be ‘‘retriggered’’...
Page 172 82C54 After writing the Control Word and initial count the Signal counter will not be loaded until the CLK pulse after a Status Or Going Rising High trigger This CLK pulse does not decrement the Modes count so for an initial count of N OUT does not Disables Enables strobe low until N...
Page 173 82C54 high logic level does not have to be maintained until Operation Common to All Modes the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge- and level-sensi- Programming tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed When a Control Word is written to a Counter all immediately following WR of a new count value...
Page 174: Absolute Maximum Ratings
82C54 ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sheet The specifi- cations are subject to change without notice Ambient Temperature Under Bias 0 C to 70 C WARNING Stressing the device beyond the ‘‘Absolute Storage Temperature 65 to 150 C Maximum Ratings’’...
Page 175 82C54 A C CHARACTERISTICS (Continued) WRITE CYCLE 82C54-2 Symbol Parameter Units Address Stable Before WR CS Stable Before WR Address Hold Time After WR WR Pulse Width Data Setup Time Before WR Data Hold Time After WR Command Recovery Time CLOCK AND GATE 82C54-2 Symbol...
Page 176 82C54 WAVEFORMS WRITE 231244 –14 READ 231244 –15 RECOVERY 231244–16...
Page 177: Revision Summary
82C54 CLOCK AND GATE 231244 –17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT 231244 –18 231244 –19 A C Testing Inputs are driven at 2 4V for a logic ‘‘1’’ and 0 45V 150 pF for a logic ‘‘0 ’’...
Page 178 Interval Timer manufactured using an advanced 2 micron • Compatible with NMOS 8254 CMOS process. - Enhanced Version of NMOS 8253 The 82C54 has three independently programmable and • Three Independent 16-Bit Counters functional 16-bit counters, each capable of handling clock •...
Page 179: Ordering Information
82C54 Ordering Information PART NUMBERS TEMPERATURE 8MHz 10MHz 12MHz RANGE PACKAGE PKG. NO. CP82C54 CP82C54-10 CP82C54-12 C to +70 24 Lead PDIP E24.6 IP82C54 IP82C54-10 IP82C54-12 C to +85 24 Lead PDIP E24.6 CS82C54 CS82C54-10 CS82C54-12 C to +70 28 Lead PLCC N28.45 IS82C54 IS82C54-10...
Page 180: Functional Description
82C54 Pin Description (Continued) DIP PIN SYMBOL NUMBER TYPE DEFINITION CLK 2 CLOCK 2: Clock input of Counter 2. A0, A1 19 - 20 ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. SELECTS Counter 0 Counter 1...
Page 181: Diagram
82C54 Control Word Register The Control Word Register (Figure 2) is selected by the INTERNAL BUS Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 82C54, the data is stored in the Con- CONTROL STATUS trol Word Register and is interpreted as a Control Word used...
Page 182: Figure 3-3 Control Word
82C54 Operational Description SC - Select Counter General After power-up, the state of the 82C54 is undeﬁned. The Select Counter 0 Mode, count value, and output of all Counters are undeﬁned. Select Counter 1 How each Counter operates is determined when it is pro- Select Counter 2 grammed.
Page 183 82C54 Possible Programming Sequence explained later. The second is a simple read operation of the (Continued) Counter, which is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected Counter must be inhibited by using either the GATE input or external LSB of Count - Counter 1 logic.
Page 184 82C54 1. Read least signiﬁcant byte. The read-back command may also be used to latch status information of selected counter(s) by setting STATUS bit D4 2. Write new least signiﬁcant byte. = 0. Status must be latched to be read; status of a counter is 3.
Page 185 82C54 Both count and status of the selected counter(s) may be If a new count is written to the Counter it will be loaded on latched simultaneously by setting both COUNT and STATUS the next CLK pulse and counting will continue from the new bits D5, D4 = 0.
Page 186 82C54 Mode 1: Hardware Retriggerable One-Shot Mode 2: Rate Generator OUT will be initially high. OUT will go low on the CLK pulse This Mode functions like a divide-by-N counter. It is typically following a trigger to begin the one-shot pulse, and will remain used to generate a Real Time Clock Interrupt.
Page 187 82C54 Mode 3: Square Wave Mode Mode 3 is Implemented as Follows: Mode 3 is typically used for Baud rate generation. Mode 3 is EVEN COUNTS: OUT is initially high. The initial count is similar to Mode 2 except for the duty cycle of OUT. OUT will loaded on one CLK pulse and then is decremented by two initially be high.
Page 188 82C54 CW = 18 LSB = 3 CW = 1A LSB = 3 GATE GATE CW = 18 LSB = 3 CW = 1A LSB = 3 GATE GATE CW = 18 LSB = 3 LSB = 2 CW = 1A LSB = 3 LSB = 5 GATE GATE...
Page 189: Max Count
82C54 Counter New counts are loaded and Counters are decremented on MODE MIN COUNT MAX COUNT the falling edge of CLK. The largest possible initial count is 0; this is equivalent to 2 for binary counting and 10 for BCD counting. The counter does not stop when it reaches zero.
Page 190 82C54 Absolute Maximum Ratings Thermal Information θ θ Supply Voltage ........+8.0V Thermal Resistance (Typical) C/W) C/W)
Page 191 82C54 = +5.0V ± 10%, T AC Electrical Speciﬁcations C to +70 C (C82C54, C82C54-10, C82C54-12) = -40 C to +85 C (I82C54, I82C54-10, I82C54-12) = -55 C to +125 C (M82C54, M82C54-10, M82C54-12) 82C54 82C54-10 82C54-12 TEST SYMBOL PARAMETER UNITS CONDITIONS READ CYCLE...
Page 192: Timing Waveforms
82C54 Timing Waveforms A0 - A1 tWA (11) (10) VALID DATA BUS (13) (14) (12) FIGURE 17. WRITE A0 - A1 tAR (1) tRA (3) DATA BUS VALID FIGURE 18. READ (8) (15) RD, WR FIGURE 19. RECOVERY COUNT (SEE NOTE) MODE (23) tWC (28)
Page 193 82C54 Burn-In Circuits MD 82C54 CERDIP MR 82C54 CLCC VCC Q2 Q1 OPEN Q3 VCC OPEN VCC/2 OPEN VCC/2 Q6 GND VCC/2 OPEN NOTES: = 5.5V ± 0.5V 8. R4 = 1.8kΩ ±5% 1. V 9. R5 = 1.2kΩ ±5% 2.
Page 194 82C54 Die Characteristics ± 0.75k Å Å DIE DIMENSIONS: Thickness: Metal 1: 8k ± 1.0k Å Å 129mils x 155mils x 19mils Metal 2: 12k (3270µm x 3940µm x 483µm) GLASSIVATION: METALLIZATION: Type: Nitrox ± 3.0k Å Å Type: Si-Al-Cu Thickness: 10k Metallization Mask Layout 82C54...
Page 195 Data Converters •The Real World is Analog • ADC are necessary to convert the real world signals (analog) into the digital form for easy processing Digital Processing (Computer, DSP...) Real World: Real World: Antenna, microphone, Speaker, screen, sensor... motor control... Analog and Mixed Signal Center, TAMU...
Page 196: Basic Concepts
Basic Concepts • The goal of an ADC is to determine the output digital word corresponding to an analog input signal. • The basic internal structures of ADC rely heavily on DACs structures. • ADCs can be seen as low speed (serial type), medium speed, high-speed and high- performance.
Page 197 Fundamentals • Traditional Data Converters at Nyquist Rate (fs>2fm) – A/D Converter Details: Digital Low Pass S&H Quantizer Filter Encoder Binary Number 10001000111... X(f) Quant. noise Analog and Mixed Signal Center, TAMU...
Page 198 Fundamentals • Traditional Data converters at Nyquist Rate (fs>2fm) – D/A Converter: Nyquist Rate y(t) LPF + S&H Droop correction (Ideal) Binary Number Y(f) 10001000111... • Droop correction means inverse Sinc • The S/H is a “deglitching” circuit and could be eliminated for small glitches Analog and Mixed Signal Center, TAMU...
Page 199 Fundamentals • A/D: Sampled Signal Spectrum: Anti-alias filter Quant. “noise” σ σ 1 . 7 6 + 1 . 7 6 + ∗ 6 . 0 2 ∗ 6 . 0 2 DR = 1.5 (K-1) δ σ σ δ δ K: # Quantizer levels n: Equivalent # Bits Analog and Mixed Signal Center, TAMU...
Page 200 Sampling • The process of converting to digital can not be instantaneous • The input has to be stabilized while a conversion is performed. Sampled Analog Analog Input Sampler Conversion The ADC will convert each these analog values to the Delay corresponding digital value one after the other...
Page 201 REAL SAMPLING Input Waveform Sampling Function Sampled Output f(t) h(t) g(t) Square Wave f(t) Period T Τ Fourier Analysis − F(f) Input Spectra Sampling Spectra Output Spectra F(f) H(f) G(f) − Envelope has the form      ...
Page 202 Since real Data Converters have a number of non-idealities we need to use a Performance Metrics to evaluate and compare them. In what follows we will attempt to define it. The number of bits of the digital code is finite: for n-bit we have 2 codes and each code represents a given quantization level.
Page 203 Definitions • Differential Nonlinearity: Deviation in the width of a certain code from the value of 1LSB. • Integral Non-Linearity: Deviation in the midpoint of the code from the best straight line in LSBs.
Page 204 THE IDEAL TRANSFER FUNCTION (ADC) Digital Output Ideal Straight Line Conversion Code Code Range of Digital Output Analog Input Code Values Center 4.5 • 5.5 3.5 • 4.5 2.5 • 3.5 1.5 • 2.5 0.5 • 1.5 Step Width (1 LSB) 0 •...
Page 205 Ideal Transfer Characteristic Output Code Best Straight Line 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8...
Page 206 Ideal Transfer Characteristic Output Code Best Straight Line 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8...
Page 207 Ideal Transfer Characteristic Output Code Best Straight Line 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8...
Page 208 Unipolar Quantization Error Output Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 Input 0000 Error 1LSB Input...
Page 209 Bipolar Quantization Error Output Code 1111 1110 • Bipolar Error 1101 1100 • Offset Error 1011 1010 (Minor 1001 Importance 1000 0111 0110 0101 0100 0011 0010 0001 Input 0000 Error 1 LSB 1/2 LSB Input -1/2 LSB...
Page 210: Input Output
Unipolar vs. Bipolar • Quantization Noise Power: Unipolar Error ( ) [LSB] ε • RMS Value of Quantization Noise Power: LSB/1.73 Input [LSB] • More Than Half an LSB error.
Page 211 Unipolar vs. Bipolar • Quantization Noise Power: Bipolar Error ( ) [LSB] ε • RMS Value of Quantization Noise Power: -3/2 -1/2 LSB/3.46 Input [LSB] -1/2 • Approximately One Third of an LSB. Reference: Spectra of Quantized Signals, W.R.Bennett, BSTJ, July 1948.
Page 212 QUANTIZATION EFFECTS Digital Code Error at the jth step: − The mean square error over the step is: ∫ − - q 1/2 + q 1/2 Assuming equal steps, the total error is: (Mean square quantization noise) + 1/2 Quantization Error Error E - 1/2...
Page 213 QUANTIZATION EFFECTS Considering a sine wave input F(t) of amplitude A so that ∫ which has a mean square value of F (t), where which is the signal power. Therefore the signal to noise ratio SNR is given by  ...
Page 214: Signal To Noise Ratio (Snr)
Signal to Noise Ratio (SNR) ω • V =A Sin( T) ; A = V • Signal Power: = (V / 2.8) • Noise Power: = LSB • SNR = (1.5)2 1.8 + 6.02 N [dB] • Example: SNR(10bit) = 62dB...
Page 215 APERTURE ERROR Sampling Pulse The aperture error comes from the fact that there is a delay between the clock signal and the effective holding time. Aperture cos2 Uncertainty ⇒ Aperture Error Hold < Sample Analog and Mixed-Signal Center (ESS)
Page 216 Nyquist Rate • According to signal processing theory, the sampling process generates images of the input signal around the sampling frequency • It can be seen that if the input frequency is higher than half the sampling frequency, there will be corruption of the information by the image.
Page 217 Oversampling • As we have seen earlier, the SNR of a typical ADC is: 6.02n 1.76dB • If the sampling rate is increased, we get the following SNR: 6.02n+1.76dB+10log(OSR) where OSR stands for “oversampling ratio”. Signal of interrest Images Frequency (KHz) Input Sampling Frequency...
Page 218 Signal to Noise + Distortion Ratio (SNDR) SNDR [dB] 1.8+6.02N Input Magnitude 1LSB Analog and Mixed Signal Center, TAMU...
Page 219 Signal to Noise + Distortion Ratio (SNDR) SNDR [dB] 1.8+6.02N Input Magnitude 1LSB Analog and Mixed Signal Center, TAMU...
Page 220 Performance Evaluation of ADCs Analog and Mixed Signal Center, TAMU...
Page 221: Offset Errors
Offset Errors Actual Diagram Input Ramp Ideal Diagram Ideal Actual Diagram Diagram Actual Offset Error Offset Point (+1 1/4 LSB) +1/2 LSB Analog Output Value Nominal Digital Input Code Actual Nominal Offset Point Offset Point Offset Point Offset Error (+1 1/4 LSB) VLSI Analog Microelectronics (ESS)
Page 222 Gain Errors Measured Best Fit Gain Straight Line Input Ramp Ideal Diagram Measured Measured Gain Data Ideal Best Fit Diagram Straight Line Actual Diagram Analog Output Value Digital Input Code VLSI Analog Microelectronics (ESS)
Page 223 Absolute Accuracy (Total) Error Digital Analog Output Output Error Value (LSB) 0…111 0…110 0…101 0…100 Total Error At Step 0…101 (-1 1/4 LSB) 0…011 Total Error At Step 0…011 0…010 (1 1/4 LSB) Total Error 0…001 At Step 0…001 (1/2 LSB) 0…000 0…000 0…100...
Page 224 Integral Nonlinearity (INL) Error The integral non-linearity depicts a possible distortion of the input-output transfer characteristic and leads to harmonic distortion. Ideal Transition Actual Transition At Transition At Step 011/100 011 (1/2 LSB) (-1/2 LSB) End-Point Lin. Error End-Point Lin. Error At Step At Transition 001 (1/4 LSB)
Page 225 Differential Nonlinearity (DNL) Digital Output Analog Output Code Value (LSB) 0…110 1 LSB 0…101 Differential 0…100 Linearity Error (-1/4 LSB) Differential 0…011 Linearity Error (1/2 LSB) 1 LSB 1 LSB 0…010 Differential Differential Linearity 0…001 1 LSB Linearity Error Error (+1/4 LSB) (-1/2 LSB) 0…000 0…000...
Page 226 Numerical Examples [1] Example 1. A 100-mV sinusoidal signal is applied to an ideal 12-bit A/D converter for which = 5 V. Find the SNR of the digitized output signal.           ...
Page 227 Example Consider a 3-bit D/A converter in which V = 4 V, with the following measured voltage values: { 0.011 : 0.507 : 1.002 : 1.501 : 1.996 : 2.495 : 2.996 : 3.491 } 1. Find the offset and gain errors in units of LSBs. 2.
Page 228 Example 3 [Johns & Martin] A full-scale sinusoidal waveform is applied to a 12-bit A/D converter, and the output is digitally analyzed. If the fundamental has a normalized power of 1 W µ W, what is the effective number of bits for while the remaining power is 0.5 the converter? Solution...
Page 229 Measure Static Performance The first step is to find each transition point; • The real transition is not instantaneous. The transition point is half way between 2 consecutive codes • Once all the transition points are recorded, the static parameters can be computed by a set of equations •...
Page 230 Method 1:manual measurement • Increase the analog input to the ADC slowly until we can make the digital output 1 LSB more,from 11010 to 11011 • write down the correspond analog input value V1 • decrease the analog input to the ADC slowly until we can make the digital output return to the 11010 •...
Page 231 Method 2:The Servo Method • The Servo method is an automated technique to easily find the transition points • for example,we need the transition point between 11010 and 11011.We should set search value register as 11010 • close the loop;when the circuit is stable,use a DC voltmeter to measure the analog value at the output of the integrator.It is the transition point between 11010 and 11011 Search Value...
Page 232 Method 3:The Linear Ramp Histogram • The histogram is best suited for automated testing of ADCs in the industry • A linear ramp is sent to the ADC under test and the output codes are sampled and recorded • The input ramp must be very slow, such that we get at least 16 samples per output code •...
Page 233 Method 3:The linear Ramp Histogram (continued) digital output code • Record the samples per ADC samples missing code digital code • use the recorded values to compute the transition point transition point one by input analog voltage...
Page 234 Calculate static parameters from transition points • Use TP as the symbol of the transition point,and assume TP[i] is the transition point between code i-1 and code I   • Offset = TP[1]-0.5 FSR is the full scale input range; N is ADC resolution ...
Page 235 Dynamic Performance Measurement • The most typical dynamic performance measurement consists of looking for distortion in the frequency domain • This is done by sending a pure sinusoidal input and looking at the output Distortion or noise Perfect Under Test Conceptual Dynamic Test Setup...
Page 236 Real Measurement of Dynamic Performance • There is no such thing as a perfect DAC… • To improve the precision and simplify the post-processing, all the spectrum analysis is done in digital form and in software. Computer Under Test Acquisition Board (Like National Instruments)
Page 237 Other Dynamic Measurements • All the timing and control signals (i.e. Convert, Data_Ready, Read, Data, …) must be tested at full speed to ensure their functionality, digital output code • The output from a sinewave Sparkling input can also be observed in time-domain to make sure there is no sparkling (sudden out-of-range samples).
Page 238 An illustrative example/comparison: A/D Conversion : Practical Techniques • Serial Conversion: • Parallel Conversion: Dual Slope Flash • Quantized Feedforward: • Successive Pipelined Approximation • Quantized Feedback: Delta-Sigma...
Page 239 Speed vs. Resolution Resolution[bits] >20 Conversions/sec...
Page 240 Throughput Rate Comparison of ADCs Resolution[bits] Flash, 2 Step Flash, Pipelined Order ∆ − Σ Serial (Dual Slope) 1000 10000 Clock Cycles/Output...
Page 241 An A/D Conversion Classification Multiplexing Parallel Series- Serial Coarse- Counting Parallel Fine Time Interweave Flash Subranging Non-Algorithmic Coarse-Fine Pulse Width Successive Ramp Pipeline Stacking Subranging with Approximation Comparison Flash Folding Amps Charge Dual Slopes Redistribution Constant Neural Ripple Slope Variable Ref. Network Serial Ripple Algorithmic Iterative...
Page 242 Coarse List of A/D Converter Architectures Low-to-Medium Speed Medium Speed High-Speed High-Accuracy Medium Accuracy Low-to-Medium Accuracy Integrating Successive Approximation Flash Oversampling Algorithmic Two-Step Interpolating Folding Pipelined Time-Interleaved VLSI Analog Microelectronics (ESS)
Page 243 References [1] D.A. Johns and K. Martin, Analog Integrated Circuit Design, Chapters 11 and 12, John Wiley & Sons, Inc., New York 1997,. [2] A.B. Grebene. Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons, Inc., New York 1984. [3] B.
Page 244 [8] Texas Instruments Application Report,” Understanding Data Converters”, SLAA013, July 1995. [9] J.C. Candy, and G. C. Temes, Editors. “Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation” IEEE Press, New York 1992. [10] J. E. Franca and Y. Tsividis, Editors, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing”, Chapters 9 and 10,Prentice Hall, Englewood Cliffs,1994 [11] S.
Page 245 November 1999 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters General Description n Differential analog voltage inputs n Logic inputs and outputs meet both MOS and TTL The ADC0801, ADC0802, ADC0803, ADC0804 and voltage level specifications ADC0805 are CMOS 8-bit successive approximation A/D n Works with 2.5V (LM336) voltage reference converters that...
Page 246: Typical Applications
Typical Applications DS005671-1 8080 Interface DS005671-31 Error Specification (Includes Full-Scale, Zero Error, and Non-Linearity) /2 = 2.500 V /2 = No Connection Part Full- Number Scale (No Adjustments) (No Adjustments) Adjusted ± ADC0801 ⁄ ± ADC0802 ⁄ ± ADC0803 ⁄ ±...
Page 247: Ac Electrical Characteristics
Absolute Maximum Ratings (Notes 1, 2) Infrared (15 seconds) 220˚C Storage Temperature Range −65˚C to +150˚C If Military/Aerospace specified devices are required, = 25˚C Package Dissipation at T 875 mW please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Susceptibility (Note 10) 800V Supply Voltage (V...
Page 248: Power Supply
AC Electrical Characteristics (Continued) ≤T ≤T = 5 V The following specifications apply for V and T unless otherwise specified. Symbol Parameter Conditions Units TRI-STATE Output Capacitance (Data Buffers) CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] = 5.25 V Logical “1”...
Page 249: Typical Performance Characteristics
AC Electrical Characteristics (Continued) Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1).
Page 250: Timing Diagrams
TRI-STATE Test Circuits and Waveforms = 10 pF DS005671-48 DS005671-47 = 20 ns = 10 pF DS005671-50 = 20 ns DS005671-49 Timing Diagrams (All timing is measured from the 50% voltage points) DS005671-51 www.national.com...
Page 251 Timing Diagrams (All timing is measured from the 50% voltage points) (Continued) Output Enable and Reset with INTR DS005671-52 Note: Read strobe must occur 8 clock periods (8/f ) after assertion of interrupt to guarantee reset of INTR . Typical Applications 6800 Interface Ratiometeric with Full-Scale Adjust DS005671-53...
Page 252 Typical Applications (Continued) Absolute with a 2.500V Reference Absolute with a 5V Reference DS005671-56 DS005671-55 *For low power, see also LM385–2.5 Zero-Shift and Span Adjust: 2V ≤ V ≤ 5V Span Adjust: 0V ≤ V ≤ 3V DS005671-58 DS005671-57 www.national.com...
Page 253 Typical Applications (Continued) Directly Converting a Low-Level Signal A µP Interfaced Comparator DS005671-60 For: > (−) Output = FF For: < (−) Output = 00 DS005671-59 /2 = 256 mV 1 mV Resolution with µP Controlled Range DS005671-61 /2 = 128 mV 1 LSB = 1 mV ≤V ≤(V...
Page 254 Typical Applications (Continued) Digitizing a Current Flow DS005671-62 Self-Clocking Multiple A/Ds External Clocking DS005671-64 ≤1460 kHz 100 kHz≤f DS005671-63 * Use a large R value to reduce loading at CLK R output. www.national.com...
Page 255 Typical Applications (Continued) Self-Clocking in Free-Running Mode µP Interface for Free-Running A/D DS005671-65 *After power-up, a momentary grounding of the WR input is needed to guarantee operation. DS005671-66 Operating with “Automotive” Ratiometric Transducers Ratiometric with V /2 Forced DS005671-68 DS005671-67 (−) = 0.15 V ≤V ≤85% of V...
Page 256 Typical Applications (Continued) ± Handling 10V Analog Inputs Low-Cost, µP Interfaced, Temperature-to-Digital Converter DS005671-70 DS005671-71 *Beckman Instruments # 694-3-R10K resistor array µP Interfaced Temperature-to-Digital Converter DS005671-72 ≤+128˚C *Circuit values shown are for 0˚C≤T Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage. www.national.com...
Page 257 Typical Applications (Continued) ± Handling 5V Analog Inputs Read-Only Interface DS005671-34 DS005671-33 *Beckman Instruments # 694-3-R10K resistor array µP Interfaced Comparator with Hysteresis Protecting the Input DS005671-9 Diodes are 1N914 DS005671-35 www.national.com...
Page 258 Typical Applications (Continued) Analog Self-Test for a System DS005671-36 A Low-Cost, 3-Decade Logarithmic Converter DS005671-37 *LM389 transistors A, B, C, D = LM324A quad op amp www.national.com...
Page 259 Typical Applications (Continued) 3-Decade Logarithmic A/D Converter DS005671-73 Noise Filtering the Analog Input Multiplexing Differential Inputs DS005671-74 DS005671-75 = 20 Hz Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order, low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Output Buffers with A/D Data Enabled Increasing Bus Drive and/or Reducing Time on Bus...
Page 260: Functional Description
Typical Applications (Continued) Sampling an AC Input Signal DS005671-78 > Note 11: Oversample whenever possible [keep fs 2f(−60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter. Note 12: Consider the amplitude errors which are introduced within the passband of the filter. 70% Power Savings by Clock Gating DS005671-79 (Complete shutdown takes ≈...
Page 261 Functional Description Next to each transfer function is shown the corresponding (Continued) error plot. Many people may be more familiar with error plots Figure 2 shows a worst case error plot for the ADC0801. All than transfer functions. The analog input voltage to the A/D center-valued inputs are guaranteed to produce the correct is provided by either a linear ramp or by the discrete output output codes and the adjacent risers are guaranteed to be...
Page 262 Functional Description (Continued) Transfer Function Error Plot DS005671-85 DS005671-86 FIGURE 3. Clarifying the Error Specs of an A/D Converter Accuracy = ± ⁄ A functional diagram of the A/D converter is shown in Figure 2.0 FUNCTIONAL DESCRIPTION 4 . All of the package pinouts are shown and the major logic The ADC0801 series contains a circuit equivalent of the control paths are drawn in heavier weight lines.
Page 263 Functional Description (Continued) DS005671-13 Note 13: CS shown twice for clarity. Note 14: SAR = Successive Approximation Register. FIGURE 4. Block Diagram After the “1” is clocked through the 8-bit shift register (which which causes the input to the D-type latch, LATCH 1, to go completes the SAR search) it appears as the input to the low.
Page 264 Functional Description (Continued) 2.2 Analog Differential Voltage Inputs and Common-Mode Rejection This A/D has additional applications flexibility due to the ana- log differential voltage input. The V (−) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction).
Page 265 Functional Description (Continued) Notice that the reference voltage for the IC is either ⁄ of the voltage applied to the V supply pin, or is equal to the volt- 100Ω series resistor can be used to isolate this age that is externally forced at the V /2 pin.
Page 266 Functional Description (Continued) DS005671-87 a) Analog Input Signal Example DS005671-88 /2 ≤ 1 V Add if V with LM358 to draw 3 mA to ground. b) Accommodating an Analog Input from 0.5V (Digital Out = 00 ) to 3.5V (Digital Out = FF FIGURE 7.
Page 267 Functional Description (low power Schottky such as the DM74LS240 series is rec- (Continued) ommended) or special higher drive current products which are designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended. 2.10 Power Supplies Noise spikes on the V supply line can cause conversion errors as the comparator will respond to this noise.
Page 268 Functional Description For a higher speed test system, or to obtain plotted data, a (Continued) digital-to-analog converter is needed for the test set-up. An accurate 10-bit DAC can serve as the precision voltage source for the A/D. Errors of the A/D under test can be ex- pressed as either analog voltages or differences in 2 digital words.
Page 269 Functional Description (Continued) DS005671-89 FIGURE 10. A/D Tester with Analog Error Output DS005671-90 FIGURE 11. Basic “Digital” A/D Tester TABLE 1. DECODING THE DIGITAL OUTPUT LEDs OUTPUT VOLTAGE FRACTIONAL BINARY VALUE FOR CENTER VALUES BINARY WITH /2 = 2.560 V MS GROUP LS GROUP GROUP...
Page 270 Functional Description (Continued) DS005671-20 Note 16: Pin numbers for the DP8228 system controller, others are INS8080A. Note 17: Pin 23 of the INS8228 must be tied to +12V through a 1 kΩ resistor to generate the RST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program. FIGURE 12.
Page 271 Functional Description (Continued) SAMPLE PROGRAM FOR Figure 12 ADC0801–INS8080A CPU INTERFACE DS005671-99 Note 18: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack. Note 19: All address used were arbitrarily chosen. The standard control bus signals of the 8080 CS, RD and It is important to note that in systems where the A/D con- WR) can be directly wired to the digital control inputs of the verter is 1-of-8 or less I/O mapped devices, no address de-...
Page 272 Functional Description (Continued) DS005671-21 FIGURE 13. INS8048 Interface SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE DS005671-A0 4.2 Interfacing the Z-80 The Z-80 control bus is slightly different from that of the 8080. General RD and WR strobes are provided and sepa- rate memory request, MREQ, and I/O request, IORQ, sig- nals are used which have to be combined with the general- ized strobes to provide the equivalent 8080 signals.
Page 273: General Applications
Functional Description ready memory mapped in the M6800 system and no CS de- (Continued) coding is necessary. Also notice that the A/D output data ing I/O input instructions. For example, MUX channel selec- lines are connected to the microprocessor bus under pro- tion for the A/D can be accomplished with this operating gram control through the PIA and therefore the A/D RD pin mode.
Page 274 Functional Description (Continued) SAMPLE PROGRAM FOR Figure 15 ADC0801-MC6800 CPU INTERFACE DS005671-A1 Note 22: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program. DS005671-25 FIGURE 16. ADC0801–MC6820 PIA Interface www.national.com...
Page 275 Functional Description (Continued) SAMPLE PROGRAM FOR Figure 16 ADC0801–MC6820 PIA INTERFACE DS005671-A2 The following schematic and sample subroutine (DATA IN) CPU, starts all the converters simultaneously and waits for may be used to interface (up to) 8 ADC0801’s directly to the the interrupt signal.
Page 276 Functional Description (Continued) DS005671-26 Note 23: Numbers in parentheses refer to MC6800 CPU pin out. Note 24: Numbers of letters in brackets refer to standard M6800 system common bus code. FIGURE 17. Interfacing Multiple A/Ds in an MC6800 System www.national.com...
Page 277 Functional Description (Continued) SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM DS005671-A3 SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM DS005671-A4 Note 25: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program. For amplification of DC input signals, a major system error is where I is the current through resistor R...
Page 278 Functional Description the ADC0801. It is important that the voltage levels that drive (Continued) the auto-zero resistors be constant. Also, for symmetry, a any output of Port B will source current into node V thus logic swing of 0V to 5V is convenient. To achieve this, a raising the voltage at V and making the output differential CMOS buffer is used for the logic output signals of Port B...
Page 279 Functional Description (Continued) DS005671-92 FIGURE 19. Microprocessor Interface Circuitry for Differential Preamp A flow chart for the zeroing subroutine is shown in Figure 20 . need for the CPU to determine which device requires servic- It must be noted that the ADC0801 series will output an all ing.
Page 280 Functional Description (Continued) DS005671-28 FIGURE 20. Flow Chart for Auto-Zero Routine www.national.com...
Page 281 Functional Description (Continued) DS005671-A5 Note 29: All numerical values are hexadecimal representations. FIGURE 21. Software for Auto-Zeroed Differential A/D 5.3 Multiple A/D Converters in a Z-80 Interrupt Driven • The stack pointer must be dimensioned in the main pro- Mode (Continued) gram as the RST 7 instruction automatically pushes the PC onto the stack and the subroutine uses an additional The following notes apply:...
Page 282 Functional Description (Continued) HEX PORT ADDRESS PERIPHERAL A/D 4 HEX PORT ADDRESS PERIPHERAL A/D 5 MM74C374 8-bit flip-flop A/D 6 A/D 1 A/D 7 A/D 2 This port address also serves as the A/D identifying word in the program. A/D 3 DS005671-29 FIGURE 22.
Page 283 Functional Description (Continued) DS005671-A6 www.national.com...
Page 284: Physical Dimensions
Physical Dimensions inches (millimeters) unless otherwise noted SO Package (M) Order Number ADC0802LCWM or ADC0804LCWM NS Package Number M20B Molded Dual-In-Line Package (N) Order Number ADC0801LCN, ADC0802LCN, ADC0803LCN, ADC0804LCN or ADC0805LCN NS Package Number N20A www.national.com...
Page 285: Life Support Policy
Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2.
Page 286 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 DESCRIPTION PIN CONFIGURATION The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and N PACKAGES capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry.
Page 287: Block Diagram
Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 BLOCK DIAGRAM (–) – AUTO ZERO LADDER AND COMPARATOR DECODER A GND – D7 (MSB) (11) (12) (13) (14) OUTPUT LATCHES (15) (16) (17) D0 (LSB) (18) D GND 8–BIT CLOCK SHIFT REGISTER...
Page 288: Dc Electrical Characteristics
Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 DC ELECTRICAL CHARACTERISTICS = 5.0V, f = 1MHz, T , unless otherwise specified. ADC0803/4 SYMBOL SYMBOL PARAMETER PARAMETER TEST CONDITIONS TEST CONDITIONS UNIT UNIT ADC0803 relative accuracy error (adjusted) Full-Scale adjusted 0.50 ADC0804 relative accuracy error (unadjusted)
Page 289: Ac Electrical Characteristics
Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 AC ELECTRICAL CHARACTERISTICS ADC0803/4 SYMBOL SYMBOL PARAMETER PARAMETER FROM FROM TEST CONDITIONS TEST CONDITIONS UNIT UNIT µs Conversion time =1MHz Clock frequency Clock duty cycle CS=0, f =1MHz Free-running conversion rate 13690 conv/s INTR tied to WR...
Page 290 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 Large values of source resistance where an input bypass capacitor Reference Voltage Span Adjust is not used will not cause errors as the input currents settle out prior Note that the Pin 9 (V /2) voltage is either 1/2 the voltage applied to the comparison time.
Page 291 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 differential mode of the converter. Any offset adjustment should be At higher CPU clock frequencies, time can be extended for I/O done prior to full scale adjustment. reads (and/or writes) by inserting wait states (8880) or using clock-extending circuits (6800, 8035).
Page 292 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 decoder. The RD and WR signals are generated by reading from A Digital Thermostat and writing to a dummy address. Circuit Description Digitizing a Transducer Interface Output The schematic of a Digital Thermostat is shown in Figure 11. The A/D digitizes the output of the LM35, a temperature transducer IC Circuit Description with an output of 10mV per C.
Page 293: Typical Performance Characteristics
Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Current vs Clock Frequency vs Input Current vs Temperature Clock Capacitor Applied Voltage at V REF/2 10.0 = 1MHz 5.0V CS = H = 25 MAX.
Page 294 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1) 20ns DATA OUTPUT DATA OUTPUT 10pF DATA DATA OUTPUT OUTPUT 10pF TIMING DIAGRAMS (All timing is measured from the 50% voltage points) START CONVERSION W(WR)L ”BUSY”...
Page 295 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 (5V) – TO V 0.1µF OFFSET ADJUST DIGITAL CIRCUITS ANALOG OFFSET TO V (–) CIRCUITS ADJUST Figure 2. Offsetting the Zero Scale and Adjusting the Input Range (Span) NOTE: The V /2 voltage is either 1/2 the V voltage or is that which is forced at Pin 9.
Page 296 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 CLK R 2.7k CLK IN INTR 47µF TO (–) 100µF 56pF A GND D GND Figure 5. Connection for Continuous Conversion CLK R 19 CLK IN 4 19 CLK R P1.0 = 1/1.7 R C P1.1...
Page 297 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 4.7k 1.5k LVDT NE5521 1µF 0.47µF 4.7k IN4148 3.3k FULL (–) SCALE ADJUST Figure 10. Digitizing a Transducer Interface Output August 31, 1994...
Page 298 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 RBI 5 NE587 HEF4071 RBO 4 RBI 5 NE587 HEF4071 LOWER RAISE 10µF CLK R SCC80C51 CLK IN 56pF INTR LM35 (–) D GND 10 8 A GND 29 P12 20 GND 2N3906 1N4148...
Page 299 AP-578 APPLICATION NOTE Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors February 1997 Order Number: 243291-002...
Page 300 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Page 301 AP-578 CONTENTS PAGE PAGE 3.2 Software Exception Handling ....16 1.0 INTRODUCTION AND READING GUIDE . 3 3.3 Synchronization Required for Use of FPU Exception Handlers ......17 2.0 MS-DOS* COMPATIBLE HANDLERS AND THEIR ISSUES OVER GENERATIONS ... 5 3.3.1 EXCEPTION SYNCHRONIZATION: WHAT, WHY AND WHEN ....17 2.1 Origin of MS-DOS* Mode: 8088 and 8087 .............
Page 302: Introduction And Reading Guide
On the other hand, there is much additional The use of this dedicated interrupt for the FPU exception handler is referred to as the “ native mode” , and is recommended by Intel. However, for reasons explained in Sections 2.1 and 2.2, the Footnotes...
Page 303: Intel387 Math Coprocessor
8088 or 8086 specific for an FPU error assertion. A software engineer who needs to write an MS- Intel recommended that the FPU INT be routed to DOS compatible FPU exception handler but does the 8088 or 8086 INTR pin through an 8259A...
Page 304: Special Hardware For The 80287 Interface
AP-578 used for the BIOS video software interrupt. So the (exception) handler (accessed through interrupt original IBM PC-AT* design for the 80286 and vector 75H) is guaranteed to execute before any 80287 maintained Vector #16 for the BIOS video, other 80287 instruction can begin (except for and vector 2 was shared between the FPU some special control instructions).The IRQ13 exception and the new parity checking feature.
Page 305: Ferr# & Ignne# With Intel486™ And
This IGNNE# feature is needed to necessary, because the dummy data transfer replicate the capability that was provided on MS- cycles directed to the Intel387 math co processor DOS compatible Intel 80286 and 80287 and the when PEREQ is externally reactivated for the Intel386 processors...
Page 306: Recommended External Hardware To Support Ms-Dos* Compatibility
AP-578 • next FPU or WAIT instruction.) The assertion of The frozen processor waits for an external IGNNE# is intended for use only inside the FPU interrupt, which must be supplied by external exception handler, where it is needed if one wants hardware response FERR#...
Page 307 AP-578 from the FPU. For this purpose the IGNNE# deactivation of FERR# is used to deactivate must be driven low. Typically in the PC IGNNE#. If another circuit is used, the environment an I/O access to Port 0F0H software and circuit together must assure that clears the external FPU exception interrupt IGNNE# is deactivated no later than the exit request (FP_IRQ).
Page 308: Wait" Fpu Instructions Can Get Fpu Interrupt In Window
AP-578 FF #1 Intel486 ™ , Pentium , or ® FF #2 Pentium Pro processor FP_IRQ LEGEND FF #n: Flip Flop #n CLR: Clear or reset Figure 1. Recommended Circuit for MS-DOS* Compatible FPU Exception Handling the FPU exception condition (which de-asserts 2.3.3 “...
Page 309 “ No-Wait” instruction. This process is implementations (including Intel’ s recommended illustrated by Figure 3, which is followed by a circuit). detailed description of the several cases possible. 0F0H Address Decode Figure 2. Behavior of Signals During FPU Exception Handling...
Page 310 AP-578 E x c e p t i o n g e n e r a t i n g F P i n s t r u c t i o n A s s e r t i o n O f F E R R # b y t h e p r o c e s s o r S t a r t o f t h e “N o - W a i t ”...
Page 311 That is, FERR# is asserted as soon as the FPU instruction is being used in the manner for which detects an unmasked exception; there are no cases Intel originally designed “ No-Wait in which error reporting is deferred to the next FPU instructions were intended to be used inside the or WAIT instruction.
Page 312: Recommended Protocol For Ms-Dos ™ And Windows* 95 Compatible Handlers
AP-578 As explained in Section 2.3.3, if a “ No-Wait” #I — Invalid operation instruction is used outside of the FPU exception  Stack fault handler, in the Intel486 and Pentium processors, it  IEEE standard invalid operation may accept an unmasked exception from a previous FPU instruction which happens to fall #Z...
Page 313: Automatic Exception Handling : Using Masked Exceptions
AP-578 Alternatively, a software exception handler can be invoked to handle the exception. When a numeric exception is unmasked and the exception occurs, the FPU stops further execution of the numeric instruction and causes a branch to a software exception handler.
Page 314: Software Exception Handling
80286 or Intel386 processor using the ERROR# status line between the processor and the coprocessor. See If the FPU in or with an Intel family processor Section 2.2 above, and Chapter 23 of the Pentium ®...
Page 315: Synchronization Required For Use Of Fpu Exception Handlers
AP-578 problem with this early hardware, Intel recommends language programmers exception synchronization that FPU exception handlers always access port remains the responsibility of the programmer. It is 0F0H before clearing the error condition from the not uncommon for a programmer to expect that FPU.
Page 316: Proper Exception Synchronization In General
AP-578 Incorrect Error Synchronization: FILD COUNT ; FPU instruction COUNT ; integer instruction alters operand FSQRT ; subsequent FPU instruction -- error ; from previous FPU instruction detected here Proper Error Synchronization: FILD COUNT ; FPU instruction FSQRT ; subsequent FPU instruction -- error from ;...
Page 317 AP-578 handler to be re-entrant, another technique may The first two are very similar; their only substantial also be used. In this technique, the exception flags difference is their choice of instructions to save and are not cleared in the "prologue" and the body of restore the FPU.
Page 318 AP-578 ; RESTORE MODIFIED STATE IMAGE BYTE PTR [EBP-104], 0H FRSTOR [EBP-108] ; DE-ALLOCATE STACK SPACE, RESTORE REGISTERS ESP, EBP ; RETURN TO INTERRUPTED CALCULATION IRETD SAVE_ALL ENDP Example 2. Reduced-Latency Exception Handler SAVE_ENVIRONMENT PROC ; SAVE REGISTERS, ALLOCATE STACK SPACE FOR FPU ENVIRONMENT PUSH EBP, ESP ESP, 28 ;...
Page 319 AP-578 PUSH EBP, ESP ESP, 108 ; ALLOCATES 108 BYTES (32-bit PROTECTED MODE SIZE) ; SAVE STATE, LOAD NEW CONTROL WORD, RESTORE INTERRUPT ENABLE FLAG (IF) FNSAVE [EBP-108] FLDCW LOCAL_CONTROL PUSH [EBP + OFFSET_TO_EFLAGS] ; COPY OLD EFLAGS TO STACK TOP POPFD ;...
Page 320: Need For Preserving The State Of Ignne# Circuit If Use Fpu And Smm
Shared Between Tasks code saves the FPU state using FNSAVE, then the IGNNE# Flip Flop will be cleared (because The Intel Architecture allows speculative deferral of FNSAVE clears the FPU errors and thus de-asserts floating-point state swaps on task switches. This FERR#).
Page 321: Speculatively Deferring Fpu Saves, General Overview
TS. EM means that no floating- point unit is available and that FP instructions must be emulated. Using EM to trap on task switches is not compatible with Intel Architecture MMX™ Technology. If the EM flag is set, MMX instructions raise the invalid opcode exception.
Page 322: Tracking Fpu Ownership
When considering FP exceptions across 3.6.2 TRACKING FPU OWNERSHIP all implementations of the Intel Architecture, and across all FP instructions, an FP exception can be Since the contents of the FPU may not belong to the currently executing thread, the thread identifier...
Page 323 AP-578 DNA Handler Entry <other handler set up code> Current Thread same as FPU Owner? FPU Owner := Kernel FNSAVE to Old Thread’ s FP Save Area <handler final clean-up> (may cause numeric exception) FRSTOR from Current Thread’ s CLTS (clears CR0.TS) FP Save Area Exit DNA Handler <other handler code>...
Page 324: Interrupt Routing From The Kernel
AP-578 It may at first glance seem that there is a possibility Owner is the kernel, the numeric exception handler of FP exceptions being lost because of exceptions simply exits, discarding the exception. The DNA that are discarded during state swaps. This is not handler resumes execution,...
Page 325: Changes With Intel486 ™ , Pentium
8086 or 8088 specific for an FPU error assertion. An unmasked numerical exception causes the But beginning with the Intel 80286 and 80287, FERR# output to be activated even with NE=1, and hardware connections were dedicated to support...
Page 326 FPU exception handling only in the native and the DNA handler for a native mode system can mode. Intel does not recommend using the omit the step of setting the kernel as the FPU MS-DOS compatible FPU mode for systems using owner at the handler’...
Page 327 XA User Guide...
Page 328: Life Support Applications
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Page 329 1 The XA Family - High Performance, Enhanced Architecture 80C51-Compatible 16-Bit CMOS Microcontrollers 1.1 Introduction The role of the microcontroller is becoming increasingly important in the world of electronics as systems which in the past relied on mechanical or simple analog electrical control systems have microcontrollers embedded in them that dramatically improve functionality and reliability, while reducing size and cost.
Page 330: Data Processing
Automotive Electronics - Power train Electronics - Vehicle Control Electronics - Ignition Control - Fuel Injection Control - Anti-lock Braking - Active Suspension Data Processing Industrial Control - Disk Drives - Robotic Control - Laser Printers - Asynchronous Motor Control - Multi-processor Communications - Fuzzy Control - Copiers...
Page 331: Architectural Overview
2 Architectural Overview 2.1 Introduction The Philips XA (eXtended Architecture) has a general purpose register-register architecture to provide the best cost-to-performance trade-off available for a high speed microcontroller using today’s technology. Intended as both an upward compatibility path for 80C51 users who need greater performance or more memory, and as a powerful, general-purpose 16-bit controller, the XA also incorporates support for multi-tasking operating systems and high-level languages such as C, while retaining the comprehensive bit-oriented operations that are the hallmark of the...
Page 332 System Stack Pointer User Stack Pointer Global registers. Banked Registers Figure 2.1 XA register file diagram 2.2.2 Data Memory The XA architecture supports a 16 megabyte data memory space with a full 24-bit address. Some derivative parts may implement fewer address lines for a smaller range. The data space beginning at address 0 is normally on-chip and extends to the limit of the RAM size of a particular XA derivative.
Page 333 Segment 255 (Segment n) Segment 1 Segment 0 64K bytes Figure 2.2 XA data memory segments FFFFh (64K) The entire memory is addressable in the indirect and indirect Off-chip with offset modes data memory The direct addressing mode limit is at 1K (3FFh) The on-chip/off-chip data memory boundary varies On-chip...
Page 334 Direct. The first 1K bytes of data on each segment may be accessed by an address contained within the instruction. Indirect. A complete 24-bit data memory address is formed by an 8-bit segment register concatenated with 16-bits from a pointer register. Indirect with offset.
Page 335: Special Function Registers
chip space always begins at code address 0 and extends to the limit of the on-chip code memory. Above that, code will be fetched from off-chip. Most XA derivatives will support an external bus for off-chip data and code memory, and may also be used in a ROM-less mode, with no code memory used on-chip.
Page 336 because each has a different set of peripheral functions. Many SFR addresses will be unused on any particular XA derivative. The first 64 bytes of on-chip SFR space are bit-addressable. Any CPU or peripheral register that allows bit access will be allocated an address within that range. 2.3 CPU Figure 2.6 shows the XA architecture as a whole.
Page 337: Core Registers
2.3.1 CPU Blocks The XA processor is composed of several functional blocks: Instruction fetch and decode; Execution unit; ALU; Exception controller; Interrupt controller; Register File and core registers; Program memory (ROM or EPROM), Data memory (RAM); SFR and external bus interface; Oscillator;...
Page 338: Execution Unit
The instruction at the head of the queue is decoded into separate functional fields that tell the other CPU blocks what to do when the instruction is executed. These fields are stored in staging registers that hold the information until the next instruction begins executing. Execution Unit The execution unit controls many of the other CPU blocks during instruction execution.
Page 339 When the service routine completes, it returns to the interrupted code by executing the RETI (return from interrupt) instruction. This instruction loads first the PSW and then the Program Counter from the stack, resuming operation at the point of interruption. If more than the PC and PSW are used by the service routine, it is up to that routine to save and restore those registers or other portions of the machine state, normally by using the stack, and often by switching register banks.
Page 340: Debugging Features
System User System Stack User Stack Stack Stack Pointer Pointer in Segment 0 in DS Segment User Mode System Mode Stack Pointer Figure 2.7 XA Stacks segment 0. The user stack resides in the data memory segment identified by the current value of the data segment (DS) register.
Page 341: Task Management
With these two features, a simple monitor debugger routine can allow a user to single step through a program, or to run a program at full speed, stopping only when execution reaches a breakpoint, in either case viewing the CPU state before continuing. 2.4 Task Management Several features of the XA have been included to facilitate multi-tasking.
Page 342: Instruction Set
2.5 Instruction Set The XA instruction set is designed to support common control applications. The instruction encoding is optimized for the most commonly used instructions: register to register or register with indirect arithmetic and logic operations; and short conditional and unconditional branches. These instructions are all encoded as 2 bytes.
Page 343 After Before 1045 1000 ADD R1, [R2] 1004 1004 register file register file 1000 1000 1002 1002 1004 1004 1006 1006 data memory data memory Figure 2.9 Basic Indirect Addressing Syntax, to register After Before 1000 1000 ADD [R2], R1 1004 1004 register file...
Page 344 After Before 1045 1000 ADD R1, [R2+] 1006 1004 register file register file 1000 1000 1002 1002 1004 1004 1006 1006 data memory data memory Figure 2.11 Indirect Addressing with Auto-Increment Since indirect memory references and immediate data values do not implicitly identify the size of the operation to be performed, a few XA instructions must have an operation size explicitly called out.
Page 345: Instruction Set Summary
2.5.2 Instruction Set Summary The following pages give a summary of the XA instruction set. For full details, consult Chapter 6. Basic Arithmetic, Logic, and Data Movement Instructions The most used operations in most programs are likely to be the basic arithmetic and logic instructions, plus the MOV (move data) instruction.
Page 346 Operands Description [R+], #data The source operand is an 8 or 16-bit immediate value, the destination operand is indirect with auto-increment. [R+offset], #data The source operand is an 8 or 16-bit immediate value, the destination operand is indirect with an 8 or 16-bit offset. direct, #data The source operand is an 8 or 16 bit immediate value, the destination operand is a direct address.
Page 347: Other Instructions
Jump, branch, and call instructions Branch to code address (plus or minus 256 byte range). Jump to code address (range depends on specific JMP variation). CALL Call subroutine (range depends on specific CALL variation). Return from subroutine or interrupt. Conditional branches with 15 possible condition variations. JB, JNB Jump if a bit set or not set.
Page 348: External Bus
2.6 External Bus Most XA derivatives have the capability of accessing external code and/or data memory through the use of an external bus. The external bus provides address information to external devices, and initiates code read, data read, or data write strobes. The standard XA external bus is designed to provide flexibility, simplicity of connection, and optimization for external code fetches.
Page 349: Bus Timing
Second, the number of address lines may be configured in order to make optimal use of I/O ports. Since external bus functions are typically shared with I/O ports and/or peripheral I/O functions, it is advantageous to set the number of address lines to only what is needed for a particular application, freeing I/O pins for other uses.
Page 350 data address Address bus address data in to XA Data bus Figure 2.14 Typical External Data Read. data address Address bus address data out from XA Data bus WRL/WRH Figure 2.15 Typical External Data Write. 2.7 Ports Standard I/O ports on the XA have been enhanced to provide better versatility and programmability than was previously available in the 80C51 and most of its derivatives.
Page 351 input output hi-Z Read Write Write Write open drain push-pull Quasi-bidirectional Figure 2.16 XA Port Pins with Driver Option Detail 2.8 Peripherals The XA CPU core is designed to make derivative design fast and easy. Peripheral devices are not part of the core, but are attached by means of a Special Function Register bus, called the SFR bus, which is distinct from the CPU internal buses.
Page 352: Software Compatibility
The XA provides an 80C51 Compatibility Mode, which essentially replicates the 80C51 register architecture for the best possible upward compatibility. In the alternative Native Mode, the XA operates as an optimized 16-bit microcontroller incorporating the best conceptual features of the original 80C51 architecture.
Page 353 • Stack. One area where a functional change could not be avoided is in the use of the processor stack. Due to the fact that the XA supports 16-bit operations in memory, it was necessary to change the direction of stack growth to downward –the standard for 16-bit processors– in order to match stack usage with efficient access of 16-bit variables in memory.
Page 354 3/24/97 2-24 Architectural Overview...
Page 355 3 XA Memory Organization 3.1 Introduction The memory space of XA is configured in a Harvard architecture which means that code and data memory (including sfrs) are organized in separate address spaces. The XA architecture supports 16 Megabytes (24-bit address) of both code and data space. The size and type of memory are specific to an XA derivative.
Page 356 less significant word), and this must have an even number. Thus valid double-register pairs are (R0,R1), (R2,R3), (R4,R5) and (R6, R7). 16 bits derivative-optional general registers (word-accessible only) general registers present in all XA derivatives Figure 3.1 XA Register File Overview As described in section 4.7, there are two stack pointers, one for user mode and another for system mode.
Page 357 PSW.RSn are writable when the XA is operating in system or user mode, and programs running in either mode may explicitly change these bits to make selected banks visible one at a time. More commonly, the interrupt mechanism, as described in Chapter 4, provides automatic implicit register bank switching so interrupt handlers may immediately begin operating in a reserved register context.
Page 358 Bit Access to Registers The XA Registers are all bit addressable. Figure 3.3 shows how bit addresses overlie the basic register file map. In general, absolute bit references as given in this map are unnecessary. XA software development tools provide symbolic access to bits in registers. For example, bit 7 may be designated as “R0.7”...
Page 359: Data Memory
3.3.1 Bytes, Words, and Alignment XA memory is addressed in units of bytes, where each byte consists of 8 bits. A word consists of two bytes, and the word storage order is “Little-Endian”, that is, the less significant byte of word data is located at a lower memory address.
Page 360: Data Memory Addressing
3.4.3 Use and Read/Write Access Data memory is defined as read-write, and is intended to contain read/write data. It is logically impossible to execute instructions from XA Data Memory. It is possible, and a common practice, to add logic to overlap external code and data memory spaces. In this case it is important to understand that the memory spaces are logically separate.
Page 361 64K Segments FFFFh Data Memory (only indirectly addressed) 400h 3FFh (directly and indirectly addressable) Directly addressed data Standard (1Kb per bit-addressable segment) (directly and indirectly addressable) Figure 3.6 Data memory segmentation If R7 (the stack pointer) is used as a normal indirect pointer, the data segment addressed will always be segment 0 in System Mode and the DS segment in User Mode.
Page 362: Indirect Addressing
Bit-level. Bit-level addresses are absolute references to specific bits. Data move instructions and some special purpose instructions also have additional data addressing modes as described in Chapter 6. Indirect Addressing The entire 16 MByte address space is accessible via register-indirect addressing with a segment register, as illustrated by Figure 3.7 (Note that for simplicity, this figure omits showing how the Extra Segment or Data Segment Register is chosen using SSEL.).
Page 363: Direct Addressing
Direct Addressing The ﬁrst 1K of each segment is directly addressable. Address generation for the direct address mode is summarized in Figure 3.10. Segment register DS is always used. Direct data-reference instructions encode a maximum of 10 address bits, which are zero extended to sixteen bits and concatenated with DS to form an absolute 24 bit address.
Page 364 identifies 1 of 8 bits in a byte. byte offset from 20h Figure 3.10 Bit address generation in direct memory space Segment n 1FF 1FE 1FD 1FC 1FB 1FA 1F9 1F8 1F7 1F6 1F5 1F4 1F3 1F2 1F1 1F0 1EF 1EE 1ED 1EC 1EB 1EA 1E9 1E8 1E7 1E6 1E5 1E4 1E3 1E2 1E1 1E0 14F 14E 14D 14C 14B 14A 149 148 147 146 145 144 143 142 141 140 13F 13E 13D 13C 13B 13A 139 138 137 136 135 134 133 132 131 130 12F 12E 12D 12C 12B 12A 129 128 127 126 125 124 123 122 121 120...
Page 365 3.5.2 External and Internal Overlap If External Code Memory is placed by external logic at locations that overlap Internal Code Memory, the Internal Code Memory takes precedence, and the overlapped portion of the External memory will in not be accessed. However, on XA implementations that provide an External Address (EA) hardware input, setting EA low will cause external program memory to be used.
Page 366: Special Function Registers (Sfrs)
3.6 Special Function Registers (SFRs) Special Function Registers (SFRs) provide a means for programs to access CPU control and status registers, peripheral devices, and I/O ports. The SFR mechanism provides a consistent mechanism for accessing standard portions of the XA core, peripheral functions added to the core within each XA derivative, and external devices as implemented in future derivatives.
Page 367 assigned addresses in the range 400h through 43Fh are both byte and bit-addressable. The second half (600h through 7FFh) of the SFR space is reserved for providing access to off-chip SFRs. The off-chip sfr space is provided to allow faster access of off-chip memory mapped I/O devices without having to create a pointer for each access.
Page 368 An SFR address is always contained entirely within an instruction. The SFR address is always encoded in the instruction providing the access, and there is no other way of addressing an SFR. Details of access to external SFRs is determined by derivative implementation. Access to off- chip SFRs is a reserved feature not implemented in the baseline XA.
Page 369 4 CPU Organization This chapter describes the Central Processing Unit (CPU) of the XA Core. The CPU contains all status and control logic for the XA architecture. The XA reset sequence and the system oscillator interface with the CPU, and power control is handled here. The CPU performs interrupt and exception handling.
Page 370: Program Status Word
provides internal and external timing for program and data memory access. This logic supervises loading the Program Counter and storing instructions fetched by the Program Memory Interface into the Instruction Register. The timing and control logic sequences data transfers to and from the Data Memory Interface.
Page 371 Status Flags are affected by each instruction type. Consult reference pages in Chapter 6 for details about how individual instructions affect the PSW Status Flags. PSWL Figure 4.3 PSW CPU status flags C, the Carry Flag, generally reflects the results of arithmetic and logical operations. It contains the carry out of the most significant bit of an arithmetic operation, if any, for the instructions ADD, ADDC, CMP, CJNE, DA, SUB, and SUBB.The carry flag is also used as an intermediate bit for shift and rotate instructions ASL, ASR, LSR, RLC, and RRC.
Page 372 4.2.2 Operating Mode Flags The PSW operating mode flags (Figure 4.4) set several aspects of the XA operating mode. All of the flags in the upper byte of the PSW (PSWH) except the bits RS1 and RS0 may be modified only by code running in system mode.
Page 373: System Configuration Register
For example, executing MOV.b R0L,#81h sets PSW bit N to 1, since the byte value transferred is a twos complement negative number. However, executing MOV.b PSWL, #81h will set PSW bits C and Z and leave bit N cleared, since the value explicitly written to PSW takes precedence.
Page 374 CM chooses between standard “native” mode XA operation and 80C51 compatibility mode. When 80C51 compatibility mode is enabled, two things happen. First, the bottom 32 bytes of data memory in each data segment are replaced by the four banks of R0 through R3 from the register file.
Page 375: Power-Up Reset
Switching into or out of Page 0 mode after the original initialization is not recommended. First, switching into Page 0 mode can only be done by code running on Page 0, since the code address will be truncated to 16-bits as soon as Page 0 mode takes effect. Instructions already in the XA pre-fetch queue would have been fetched prior to Page 0 mode taking effect.
Page 376 XA configuration signals sampled first instruction executed Vmin internal reset sequence reset exception generated Figure 4.6 XA power-up sequence 4.4.3 Internal Reset Sequence The XA internal reset sequence occurs after power-up or any time a sufficiently long reset pulse is applied to the RST input while the XA is operating. This sequence requires a minimum of a 10 microseconds (or 10 clocks, whichever is greater) to complete, and RST must remain low for at least this long.
Page 377 Note that serial port buffers, PCA capture registers, and WatchDog feed registers (if present) are unaffected. Consult the XA derivative data sheet for more information. After the XA internal reset sequence has been completed, the device is quiescent until the RST line goes high.
Page 378 4.4.5 The Reset Exception Interrupt Immediately after the RST line goes high, the CPU generates a Reset Exception Interrupt. As a result, the initial PSW and address of the first instruction (the “start-up code”) is fetched from the reset vector in code memory at location 0. Here’s an example in generalized assembler format of the setup for the Reset Exception: code_seg ;...
Page 379: Startup Code
4.4.6 Startup Code Philips recommends that the first instruction of start-up code set the value of the System Configuration Register (SCR), described in section 4.3, to reflect the system architecture. The next recommended step is explicitly initializing the stack pointers. The default values (section 4.7) are usually insufficient for application needs.
Page 380: Using An External Clock
4.5 Oscillator The XA contains an on-chip oscillator which may be used as the clock source for the XA CPU, or an external clock source may be used. A quartz crystal or ceramic resonator may be connected as shown in Figure 4.8a to use the internal oscillator. To use an external clock, connect the source to pin XTAL1 and leave pin XTAL2 open, as shown in Figure 4.8b.
Page 381: Idle Mode
Power-Down mode is activated set by setting the PCON bit PD. This shuts down the XA entirely, stopping the oscillator. The reset values of IDL and PD are 0. If a 1 is written to both bits simultaneously, PD takes precedence and the XA goes into Power-Down mode.
Page 382: Push And Pop
that time. Once the oscillator counter times out, the XA will execute the interrupt that woke it up, if that interrupt is of a higher priority than the currently executing code. Note that if an external oscillator is used, power supply current reduction in the Power-Down mode is reduced from what would be obtained when using the XA on-chip oscillator.
Page 383 The POP operation copies the data at the top of the stack and then adds two to the stack pointer, as follows shown in Figure 4.11. All stack pushes and pops occur in word multiples. If a byte quantity is pushed on the stack it is stored as the least significant byte of a word and the high byte is left unwritten;...
Page 384: Stack Overflow
The stack should always be word-aligned. If the SP (R7) is modified to an odd value, the offending LSB of the stack pointer is ignored and the word at the next-lower even address is accessed. Note that neither PUSH or POP operations have any effect on the PSW flags. MOV R0,#9876h PUSH R0H after...
Page 385 Rn, [R7+offset] [R7+offset], Rn SP (R7) SM bit in PSW 8 or 16-bit offset 16-bit pointer (from instruction) 8-bit segment identifier 16 bits 8 bits Data Memory complete 24-bit memory address [SP+8] [SP+6] [SP+4] [SP+2] [SP+0] Figure 4.14 Stack-based addressing of the 64 bytes on the stack is available for handler processing, which should carefully limit further use of the stack.
Page 386 These default stack pointer start-up values overlap the System and User stacks and are applicable only when one of these stacks will never be used. Since the System stack is used for all exception and interrupt processing, this may not be appropriate in all XA applications.
Page 387 Returns from all interrupts should in most cases be accomplished by the RETI instruction, which pops the System Stack and continues execution with the restored PSW context. Since RETI executed while in User Mode will result in an exception trap, as described further below, interrupt service routines will normally be executed in System Mode.
Page 388: Service Precedence
2. The breakpoint (caused by execution of the BKPT instruction, or a hardware breakpoint in an emulation system) and Trace exceptions are intended to be mutually exclusive. In both cases, the handler code will want to know the address in user code where the exception occurred. If a breakpoint occurs during trace mode, or if trace mode is activated during execution of the breakpoint handler code, one of the handlers will see a return address on the stack that points within the other handler code.
Page 389: Software Interrupt
Note that, like all other forms of interrupts, the PSW (including the Interrupt Mask bits) is loaded from the interrupt vector table when an event interrupt is serviced. Thus, the priority at which the interrupt service routine executes could be different than the priority at which the interrupt occurred (since that was determined not by the PSW image in the vector table, but by the Interrupt Priority register setting for that interrupt).
Page 390 at which the service routine began. An example of this would be an event Interrupt Service Routine that has been given a very high priority in order to respond quickly to some critical external event. This ISR has a relatively small portion of code that must be executed immediately, and a larger portion of follow-up or “clean-up”...
Page 391 split into 2 pieces: the high priority portion, and the lower priority portion. The high priority portion remains associated with the original interrupt vector. The lower priority portion is associated with the interrupt vector for software interrupt 5. At the completion of the high priority portion of the ISR, the code sets the request bit for software interrupt 5, then returns.
Page 392: Interrupt Stack Frame
of code memory. Understanding the structure and contents of each is essential to the understanding of how XA interrupts are processed. Interrupt Stack Frame A stack frame is generated, always on the System Stack, for each XA interrupt. With one exception, the stack frame is stored for the duration of interrupt service and used to return to and restore the CPU state of the interrupted code.
Page 393: Interrupt Vector Table
Interrupt Vector Table The XA uses the first 284 bytes of code memory (addresses 0 through 11B hex) for an interrupt vector table. The table may contain up to 71 double-word entries, each corresponding to a particular interrupt event. The double-word entries each consist of a 16 bit address of an interrupt service routine address and a 16 bit PSW replacement value.
Page 394 7 Software Interrupt Vectors 0100h Event Interrupt Vectors 16 bits Service Routine Address Replacement PSW Increasing addresses Trap Interrupt Vectors Exception Vectors Code Memory Figure 4.19 Interrupt vectors Instruction n Instruction n+1 Instruction n-1 Figure 4.20 XA Instruction Sequence Overview A detailed model of this sequence is shown in Figure 4.21: First, at the beginning of the instruction cycle, the state of the TM flag is latched.
Page 395 Instruction n latch Execute Instruction Interrupt Check latch; instruction Instruction illegal? allowed? pending? TM = 1? state service service service exception interrupt trace Figure 4.21 Instruction Execution Clock Detail One consequence of this sequence is that the instruction that sets TM = 1 cannot generate a Trace, since TM is not latched when the instruction is actually executed.
Page 396 XA User Guide 4-28 3/24/97...
Page 397 5 Real-time Multi-tasking Multi-tasking as the name suggests, allows tasks, which are pieces of code that do specific duties, to run in an apparently concurrent manner. This means that tasks will seem to all run at the same time, doing many specific jobs simultaneously. High end applications (like automotive) require instantaneous responses when dealing with high speed events, such as engine management, traction control and adaptive braking system (ABS) and hence there is a trend towards multi-tasking in a wide variety of high performance embedded...
Page 398: Register Banks
5.1.2 Register Banks The XA also supports 4 banks of 8 byte/4 word registers, in addition to 12 shared registers. In some applications, the register banks can be designated statically to tasks, cutting significantly on the overhead for saving and restoring registers on context switching. 5.1.3 Interrupt Latency and Overhead Interrupt latency is extremely critical in a multitasking environment.
Page 399 Protected Features in the XA Table 5.1: Segment and Stack Register Protection Write Write Read Read Read Write to Write to Write to Write to Mode through through through through through SSEL bit 7 System Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed...
Page 400 Protection Via Dual Stack Pointers The XA provides a two-level user/supervisor protection mechanism. These are the user or application mode and the system or supervisor mode. In a multitasking environment, tasks in a supervisor level are protected from tasks in the application level. The XA has two stack pointers (in the register file) called the System Stack Pointer (SSP) and the User Stack Pointer (USP).
Page 401: Addressing Modes
6 Instruction Set and Addressing This section contains information about the addressing modes and data types used in the XA. The intent is to help the user become familiar with the programming capabilities of the processor. 6.1 Addressing Modes Addressing modes are ways to form effective addresses of the operands. The XA provides seven basic powerful addressing modes for access on word, byte, and bit data, or to specify the target address of a branch instruction.
Page 402: Description Of The Modes
6.2 Description of the Modes 6.2.1 Register Addressing Instructions using this addressing mode contain a field that addresses the Register File that contains an operand. The Register file is byte , word, double-word or bit addressable. Example: ADD R6, R4 Before: R4 contains 005Ah R6 contains A5A5h After:...
Page 403 6.2.2 Indirect Addressing Instructions using this addressing mode contain a 16-bit address field. This field is contained in 1 out of 8 pointer registers in the Register File (that contain the 16-bit address of the operand in any 64K data segment). For data, the segment is identified by the 8-bit contents of DS or the ES and for code by the 8-bit contents of PC23-16 or CS as selected by the appropriate bit (SSEL.bit n = 0 selects DS and 1 selects ES for data and SSEL.bitn = 0 selects PC and 1 selects CS for code) in the segment select register SSEL corresponding to the indirect register number.
Page 404 6.2.3 Indirect-Offset Addressing This addressing mode is just like the Register-Indirect addressing mode above except that an additional displacement value is added to obtain the final effective address. Instructions using this addressing mode contain a 16-bit address field and an 8 or 16-bit signed displacement field. This field addresses 1 out of 8 pointer registers in the Register File that contains the 16-bit address of the operand in any 64K data segment.
Page 405 6.2.4 Direct Addressing Instructions using this addressing mode contain an 10-bit address field, which contains the actual address of the operand in any 64K data memory segment or sfr space.The direct address data memory space is always the bottom 1K byte (0:3FFh) of any segment. The associated data segment is always identified by the 8-bit contents of DS.
Page 406: Immediate Addressing
6.2.5 SFR Addressing This is identical to the direct addressing mode described before, except it addresses the 1K SFR space. Although encoded into the same instruction field as the direct addressing described above, this is actually a separate space. Instructions using this addressing mode contain an 10-bit SFR address.
Page 407 6.2.7 Bit Addressing Instructions using the bit addressing mode contain a 10-bit field containing the address of the bit operand. The XA supports three bit address spaces, which are encoded into the same format. The spaces are: 256 bits in the register file (the entire active register file); 256 bits in the data memory (byte addresses 20 through 3F hex on the current data segment);...
Page 408 6.3 Relative Branching and Jumps Program memory addresses as referenced by Jumps, Calls, and Branch instructions must be word aligned in XA. For instance, a branch instruction may occur at any code address, but it may only branch to an even address. This forced alignment to even address provides three benefits: •...
Page 409: Instruction Set Overview
6.4 Data Types in XA The XA uses the following types of data: • Bits • 4/5-bit signed integers • 8-bit (byte) signed and unsigned integers • 8-bit, two digit BCD numbers • 16-bit (word) signed and unsigned integers • 10-bit address for bit-addressing in data memory and SFR space •...
Page 410 Glossary of mnemonics, notations used General: offset8 An 8-bit signed offset (immediate data in the instruction) that is added to a register to produce an absolute address. offset16 A 16-bit signed offset (immediate data in the instruction) that is added to a register to produce an absolute address.
Page 411 Mnemonic text: Source register. Destination register. In the instruction mnemonic, indicates an indirect reference (e.g.: [R4] refers to the memory address pointed to by the contents of register 4). [R+] Used to indicate an automatic increment of the pointer register in some indirect addressing modes.
Page 412 Others 0x = prefix for Hex values [] = For indirect addressing [[]] = For Double-indirect addressing dest = destination src = source Table 6.2 Instruction Set in XA Mnemonic Usage MOV, MOVC, MOVS, MOVX, LEA, XCH, PUSH, POP, Data Movement PUSHU, POPU ADD, ADDS, ADDC, SUB, SUBB Add and Subtract...
Page 413 Table 6.3 shows a summary of the basic addressing modes available for data transfer and calculation related instructions. Table 6.3 Instruction Addressing Modes Modes/ ADDS MOVX Shift bytes Operands ADDC SUBB MOVS R, R • • • • • • •...
Page 414 MOVC PUSH DA, SEXT JUMP DJNZ CJNE MISC bytes Modes/ CPL, NEG CALL Operands R, [R+] • [R+], R • • [A+DPTR] A, [A+PC] • direct • Rlist • • addr24 • • [A+DPTR] R, rel • direct, rel • R, direct, rel •...
Page 415 Table 6.4 summarizes the status flag updates for the various XA instruction types. Table 6.4 Status Flag Updates Flags Updated Instruction Type ADD, ADDC, CMP, SUB, SUBB ADDS, MOVS AND, OR, XOR ASR, LSR branches, all bit operations, NOP Calls, Jumps, and Returns CJNE DIV, MUL DJNZ...
Page 416 Instruction Set Summary Table 6.5 lists the entire XA instruction set by instruction type. This can be used as a quick reference to find specific instructions that may be looked up in the detailed alphabetical description section. Instruction timing data given in this table and in the following detailed instruction description section are based on code execution from internal code memory and data accesses to internal RAM and registers only.
Page 417 — Collision of external code fetch and external data access. When an externally executing program accesses data on the external bus, the pre-fetch queue tends to starve more often that for internal execution. Table 6.5 Mnemonic Description Bytes Clocks Arithmetic Operations Rd, Rs Add registers direct Rd, [Rs]...
Page 418 Table 6.5 Mnemonic Description Bytes Clocks [Rd+offset16], #data16 Add 16-bit immediate data to register-indirect with 16-bit offset direct, #data8 Add 8-bit immediate data to memory direct, #data16 Add 16-bit immediate data to memory ADDC Rd, Rs Add registers direct with carry ADDC Rd, [Rs] Add register-indirect to register with carry...
Page 419 Table 6.5 Mnemonic Description Bytes Clocks ADDC [Rd+offset16], #data8 Add 8-bit immediate data to register-indirect with 16-bit offset and carry ADDC [Rd+offset16], #data16 Add 16-bit immediate data to register-indirect with 16-bit offset and carry ADDC direct, #data8 Add 8-bit immediate data to memory with carry ADDC direct, #data16...
Page 420 Table 6.5 Mnemonic Description Bytes Clocks Rd, [Rs+] Compare auto-increment register-indirect with register [Rd+], Rs Compare register with auto-increment register-indirect direct, Rs Compare register with memory Rd, direct Compare memory with register Rd, #data8 Compare 8-bit immediate data to register Rd, #data16 Compare 16-bit immediate data to register [Rd], #data8...
Page 421 Table 6.5 Mnemonic Description Bytes Clocks DIVU.w Rd, Rs 16X8 unsigned register divide DIVU.w Rd, #data8 16X8 unsigned register divide with immediate byte DIVU.d Rd, Rs 32X16 unsigned double register divide DIVU.d Rd, #data16 32X16 unsigned double register divide with immediate word Rd, Rs+offset8 Load 16-bit effective address with 8-bit offset...
Page 422 Table 6.5 Mnemonic Description Bytes Clocks direct, Rs Subtract register to memory Rd, direct Subtract memory to register Rd, #data8 Subtract 8-bit immediate data to register Rd, #data16 Subtract 16-bit immediate data to register [Rd], #data8 Subtract 8-bit immediate data to register- indirect [Rd], #data16 Subtract 16-bit immediate data to register-...
Page 423 Table 6.5 Mnemonic Description Bytes Clocks SUBB [Rd+], Rs Subtract with borrow register-indirect with auto increment to register SUBB direct, Rs Subtract with borrow register to memory SUBB Rd, direct Subtract with borrow memory to register SUBB Rd, #data8 Subtract with borrow 8-bit immediate data to register SUBB Rd, #data16...
Page 424 Table 6.5 Mnemonic Description Bytes Clocks Rd, [Rs+offset16] Logical AND register-indirect with 16-bit offset to register [Rd+offset16], Rs Logical AND register to register-indirect with 16-bit offset Rd, [Rs+] Logical AND register-indirect with auto increment to register [Rd+], Rs Logical AND register-indirect with auto increment to register direct, Rs Logical AND register to memory...
Page 425 Table 6.5 Mnemonic Description Bytes Clocks Rd, Rs Logical OR registers Rd, [Rs] Logical OR register-indirect to register [Rd], Rs Logical OR register to register-indirect Rd, [Rs+offset8] Logical OR register-indirect with 8-bit offset to register [Rd+offset8], Rs Logical OR register to register-indirect with 8- bit offset Rd, [Rs+offset16] Logical OR register-indirect with 16-bit offset...
Page 426 Table 6.5 Mnemonic Description Bytes Clocks direct, #data16 Logical OR16-bit immediate data to memory Rd, #data4 Rotate left register by the 4-bit immediate value Note 1 Rd, #data4 Rotate left register though carry by the 4-bit immediate value Note 1 Rd, #data4 Rotate right register by the 4-bit immediate value...
Page 427 Table 6.5 Mnemonic Description Bytes Clocks [Rd+offset8], #data8 Logical XOR 8-bit immediate data to register- indirect with 8-bit offset [Rd+offset8], #data16 Logical XOR 16-bit immediate data to register-indirect with 8-bit offset [Rd+offset16], #data8 Logical XOR 8-bit immediate data to register- indirect with 16-bit offset [Rd+offset16], #data16 Logical XOR 16-bit immediate data to...
Page 428 Table 6.5 Mnemonic Description Bytes Clocks [Rd], #data8 Move 16-bit immediate data to register- indirect [Rd], #data16 Move 16-bit immediate data to register- indirect [Rd+], #data8 Move 8-bit immediate data to register-indirect with auto-increment [Rd+], #data16 Move 16-bit immediate data to register- indirect with auto-increment [Rd+offset8], #data8 Move 8-bit immediate data to register-indirect...
Page 429 Table 6.5 Mnemonic Description Bytes Clocks MOVS [Rd+offset16], #data4 Move register-indirect with 16-bit offset to 4- bit sign-extended immediate data MOVS direct, #data4 Move 4-bit sign-extended immediate data to memory MOVX Rd, [Rs] Move external data from memory to register MOVX [Rd], Rs Move external data from register to memory...
Page 430 Table 6.5 Mnemonic Description Bytes Clocks rel8 Branch if less than or equal to (unsigned) 6t/3nt rel8 Branch if less than or equal to (signed) 6t/3nt rel8 Branch if less than (signed) 6t/3nt rel8 Branch if the negative flag is set 6t/3nt rel8 Branch if the negative flag is clear...
Page 431 Table 6.5 Mnemonic Description Bytes Clocks bit,rel8 Jump if bit not set 10t/6nt rel8 Jump if accumulator not equal zero 6t/3nt rel8 Jump if accumulator equals zero 6t/3nt No operation Return from subroutine 8/6(PZ) RETI Return from interrupt 8(PZ) Bit Manipulation C, bit Logical AND bit to carry C, /bit...
Page 432 Integer Addition Syntax: ADD dest, source Operation: dest <- src + dest Description: Performs a twos complement binary addition of the source and destination operands, and the result is placed in the destination operand. The source data is not affected by the operation. Note: If used with write to PSWL, takes precedence to flag updates Sizes: Byte-Byte, Word-Word Flags Updated: C, AC, V, N, Z...
Page 433 ADD Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset8) Encoding: 0 SZ byte 3: offset8 ADD [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + (Rs) Encoding: 0 SZ byte 3: offset8 ADD Rd, [Rs+offset16] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset16) Encoding: 0 SZ...
Page 434 ADD Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ ADD [Rd+], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + (Rs) (Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ ADD direct, Rs...
Page 435 ADD Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) + #data8 Encoding: byte 3: #data8 ADD Rd, #data16 Bytes: Clocks: Operation: (Rd) <-- (Rd) + #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 ADD [Rd], #data8 Bytes: Clocks:...
Page 436 ADD [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 ADD [Rd+], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data16 (Rd) <-- (Rd) + 2 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 ADD [Rd+offset8], #data8 Bytes:...
Page 437 ADD [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 ADD [Rd+offset16], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + #data16 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 438 ADDC Integer addition with Carry Syntax: ADDC dest, source Operation: dest <- dest + src + C Description: Performs a two’s complement binary addition of the source operand and the previously generated carry bit with the destination operand. The result is stored in the destination operand.The source data is not affected by the operation.
Page 439 ADDC [Rd], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + (Rs) + (C) Encoding: 1 SZ ADDC Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset8) + (C) Encoding: 1 SZ byte 3: offset8 ADDC [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + (Rs) + (C) Encoding:...
Page 440 ADDC [Rd+offset16], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + (Rs) + (C) Encoding: SZ 1 byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 ADDC Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)) + (C) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: SZ 0...
Page 441 ADDC Rd, direct Bytes: Clocks: Operation: (Rd) <-- (Rd) + (direct) + (C) Encoding: SZ 1 direct: 3 bits byte 3: lower 8 bits of direct ADDC Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) + #data8 + (C) Encoding: byte 3: #data8 ADDC Rd, #data16 Bytes:...
Page 442 ADDC [Rd], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data16 + (C) Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 ADDC [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data8 + (C) (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8...
Page 443 ADDC [Rd+offset8], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + #data16 + (C) Encoding: byte 3: offset8 byte 4: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 ADDC [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + #data8 + (C) Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 444 ADDC direct, #data16 Bytes: Clocks: Operation: (direct) <-- (direct) + #data16 + (C) Encoding: 0 direct: 3 bits 0 byte 3: lower 8 bits of direct byte 4: upper 8 bits of #data16 byte 5: lower 8 bits of #data16 XA User Guide 6-44 4/17/98...
Page 445 ADDS Add Short Syntax: ADDS dest, #value Operation: dest <- dest + #data4 Description: Four bits of signed immediate data are added to the destination. The immediate data is sign-extended to the proper size, then added to the variable specified by the destination operand, which may be either a byte or a word.
Page 446 ADDS [Rd+offset8], #data4 Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + #data4 Encoding: 0 SZ #data4 byte 3: offset8 ADDS [Rd+offset16], #data4 Bytes: Clocks: Operation:((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + #data4 Encoding: 0 SZ #data4 byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 ADDS direct, #data4 Bytes: Clocks:...
Page 447 Logical AND Syntax: AND dest, src Operation: dest <- dest AND src Description: Bitwise logical AND the contents of the source to the destination. The byte or word specified by the source operand is logically ANDed to the variable specified by the destination operand.
Page 448 AND Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) • ((WS:Rs)+offset8) Encoding: 1 SZ byte 3: offset8 AND [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) • (Rs) Encoding: 1 SZ byte 3: offset8 AND Rd, [Rs+offset16] Bytes: Clocks: Operation: (Rd) <-- (Rd) •...
Page 449 AND Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) • ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 1 SZ AND [Rd+], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) • (Rs) (Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation) Encoding: 1 SZ AND direct, Rs...
Page 450 AND Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) • #data8 Encoding: byte 3: #data8 AND Rd, #data16 Bytes: Clocks: Operation: (Rd) <-- (Rd) • #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 AND [Rd], #data8 Bytes: Clocks:...
Page 451 AND [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) • #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 AND [Rd+], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) • #data16 (Rd) <-- (Rd) + 2 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 AND [Rd+offset8], #data8 Bytes:...
Page 452 AND [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) • #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 AND [Rd+offset16], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) • #data16 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 453 Logical AND a bit to the Carry flag Syntax: C, bit Operation: C <- C (AND) Bit Description: Read the specified bit and logically AND it to the Carry flag. Size: Bit Flags Updated: none Note: Here the Carry bit is implicitly written by the instruction, and not to be confused with carry affected by the result of an ALU operation Bytes: Clocks:...
Page 454 Logical AND the complement of a bit to the Carry flag Syntax: C, /bit Operation: Carry <- C (AND) bit Description: Read the specified bit, complement it, and logically AND it to the Carry flag. Size: Bit Flags Updated: none Note: Here the Carry bit is implicitly written by the instruction, and not to be confused with carry affected by the result of an ALU operation Bytes:...
Page 455 Arithmetic Shift Left Syntax: ASL dest, count Operation: Do While (count not equal to 0) (C) <- (dest.msb) (dest.bit n+1) <- (dest.bit n) count = count-1 if sign change during shift, (V) <- 1 End While Description: If the count operand is greater than 0, the destination operand is logically shifted left by the number of bits specified by the count operand.
Page 456: Operation
ASL Rd, Rs Operation: (Rd) Bytes: Clocks: For 8/16 bit shifts -> 4 + 1 for each 2 bits of shift For 32 bit shifts -> 6 + 1 for each 2 bits of shift Encoding: 0 SZ1 SZ0 Rd, #data4 Rd,#data5 Bytes: Clocks:...
Page 457 Arithmetic Shift Right Syntax: ASR dest, count Operation: Do While (count not equal to 0) (C) <- (dest.0) (dest.bit n) <- (dest.bit n+1) dest.msb <- Sign bit count = count-1 End While Description: If the count operand is greater than 0, the destination operand is logically shifted right by the number of bits specified by the count operand.
Page 458 Rd, Rs Bytes: Clocks: For 8/16 bit shifts -> 4 + 1 for each 2 bits of shift For 32 bit shifts -> 6 + 1 for each 2 bits of shift Operation: (Rd) Encoding: 0 SZ1 SZ0 1 ASR Rd, #data4 Rd,#data5 Operation: (Rd)
Page 459 Branch if carry clear Syntax: BCC rel8 Operation: (PC) <-- (PC) + 2 if (C) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic instruction (or other instruction that updates the C flag) did not generate a carry (the carry flag contains a 0).
Page 460 Branch if carry set Syntax: rel8 Operation: (PC) <-- (PC) + 2 if (C) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic instruction (or other instruction that updates the C flag) generated a carry (the carry flag contains a 1).
Page 461 Branch if zero Syntax: BEQ rel8 Operation: (PC) <-- (PC) + 2 if (Z) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic/logic instruction (or other instruction that updates the Z flag) had a result of zero (the Z flag contains a 1). The branch range is +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory.
Page 462 Branch if greater than (unsigned) Syntax: BG rel8 Operation: (PC) <-- (PC) + 2 if (Z) OR (C) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last compare instruction had a destination value that was greater than the source value, in an unsigned operation.
Page 463 Branch if greater than or equal to (signed) Syntax: BGE rel8 Operation: (PC) <-- (PC) + 2 if (N) XOR (V) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last compare instruction had a destination value that was greater than or equal to the source value, in a signed operation.
Page 464 Branch if greater than (signed) Syntax: BGT rel8 Operation: (PC) <-- (PC) + 2 if ((Z) OR (N)) XOR (V) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last compare instruction had a destination value that was greater than the source value, in a signed operation.
Page 465 BKPT Breakpoint Syntax: BKPT Operation: (PC) <-- (PC) + 1 (SSP) <-- (SSP) - 6 ((SSP)) <-- (PC) ((SSP)) <-- (PSW) (PSW) <-- code memory (bkpt vector) (PC.15-0) <-- code memory (bkpt vector) 23-16) <-- 0; (PC.0) <-- 0 Description: Causes a breakpoint trap. The breakpoint trap acts like an immediate interrupt, using a vector to call a specific piece of code that will be executed in system mode.
Page 466 Branch if less than or equal to (unsigned) Syntax: rel8 Operation: (PC) <-- (PC) + 2 if (Z) OR (C) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last compare instruction had a destination value that was less than or equal to the source value, in an unsigned operation.
Page 467 Branch if less than or equal (signed) Syntax: rel8 Operation: (PC) <-- (PC) + 2 if ((Z) OR (N)) XOR (V) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last compare instruction had a destination value that was less than or equal to the source value, in a signed operation.
Page 468 Branch if less than (signed) Syntax: rel8 Operation: (PC) <-- (PC) + 2 if (N) XOR (V) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last compare instruction had a destination value that was less than the source value, in a signed operation.
Page 469 Branch if negative Syntax: rel8 Operation: (PC) <-- (PC) + 2 if (N) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic/logic instruction (or other instruction that updates the N flag) had a result that is less than 0 (the N flag contains a 1). The branch range is +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory.
Page 470 Branch if not equal Syntax: BNE rel8 Operation: (PC) <-- (PC) + 2 if (Z) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic/logic instruction (or other instruction that updates the Z flag) had a non-zero result (the Z flag contains a 0).
Page 471 Branch if no overflow Syntax: rel8 Operation: (PC) <-- (PC) + 2 if (V) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic/logic instruction (or other instruction that updates the V flag) did not generate an overflow (The V flag contains a 0). The branch range is +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory.
Page 472 Branch if overflow flag Syntax: BOV rel8 Operation: (PC) <-- (PC) + 2 if (V) = 1 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic/logic instruction (or other instruction that updates the V flag) generated an overflow (the V flag contains a 1).
Page 473 Branch if positive Syntax: rel8 Operation: (PC) <-- (PC) + 2 if (N) = 0 then (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: The branch is taken if the last arithmetic/logic instruction (or other instruction that updates the N flag) had a result that is greater than 0 (the N flag contains a 0). The branch range is +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory.
Page 474 Unconditional Branch Syntax: rel8 Operation: (PC) <-- (PC) + 2 (PC) <-- (PC + rel8*2) (PC.0) <-- 0 Description: Branches unconditionally in the range of +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory. Note: Refer to section 6.3 for details of branch range Size: None Flags Updated: none...
Page 475 CALL Call Subroutine Relative Syntax: CALL rel16 Operation: (PC) <-- (PC) + 3 (SP) <-- (SP) - 4 ((SP)) <-- (PC.23-0) (PC) <-- (PC + rel16*2) (PC.0) <-- 0 Description: Branches unconditionally in the range of +65,534 bytes to -65,536 bytes, with the limitation that the target address is word aligned in code memory.
Page 476 CALL Call Subroutine Indirect Syntax: CALL [Rs] Operation: (PC) <-- (PC) + 2 (SP) <-- (SP) - 4 ((SP)) <-- (PC.23-0) (PC.15-1) <-- (Rs.15-1) (PC.0) <-- 0 Description: Causes an unconditional branch to the address contained in the operand register, anywhere within the 64K page following the CALL instruction.The return address (the address following the CALL instruction) of the calling routine is saved on the stack.
Page 477 CJNE Compare and jump if not equal Syntax: CJNE dest, src, rel8 Operation: (PC) <-- (PC) + # of instruction bytes (dest) - (direct) (result not stored) if (Z) = 0 then (PC) <-- (PC + rel8*2); (PC.0) <-- 0 Description: The byte or word specified by the source operand is compared to the variable specified by the destination operand and the status flags are updated.
Page 478 CJNE Rd, #data8, rel8 Bytes: Clocks: 9t/6nt Encoding: byte 3: rel8 byte 4: data#8 CJNE Rd, #data16, rel8 Bytes: Clocks: 9t/6nt Encoding: byte 3: rel8 byte 4: upper 8 bits of #data16 byte 5: lower 8 bits of #data16 CJNE [Rd], #data8, rel8 Bytes: Clocks: 10t/7nt...
Page 479 Clear Bit Syntax: CLR bit Operation: (bit) <-- 0 Description: Writes a 0 (clears) to the specified bit. Size: Bit Flags Updated: none Bytes: Clocks: Encoding: bit: 2 byte 3: lower 8 bits of bit address 4/17/98 6-79 Addressing Modes and Data Types...
Page 480 Integer Compare Syntax: CMP dest, src Operation: dest - src Description: The byte or word specified by the source operand is compared to the specified destination operand by performing a twos complement binary subtraction of src from dest. The flags are set according to the rules of subtraction. The source and destination data are not affected by the operation.
Page 481 CMP [Rd], Rs Operation: ((WS:Rd)) - (Rs) Bytes: Clocks: Encoding: 0 SZ CMP Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) - ((WS:Rs)+offset8) Encoding: 0 SZ byte 3: offset8 CMP [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) - (Rs) Encoding: 0 SZ byte 3: offset8 CMP Rd, [Rs+offset16] Bytes: Clocks:...
Page 482 CMP [Rd+offset16], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset16) - (Rs) Encoding: 0 SZ byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 CMP Rd, [Rs+] Bytes: Clocks: Operation: (Rd) - ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ CMP [Rd+], Rs...
Page 483 CMP Rd, direct Bytes: Clocks: Operation: (Rd) - (direct) Encoding: 0 SZ direct: 3 bits byte 3: lower 8 bits of direct CMP Rd, #data8 Bytes: Clocks: Operation: (Rd) - #data8 Encoding: byte 3: #data8 CMP Rd, #data16 Bytes: Clocks: Operation: (Rd) - #data16 Encoding:...
Page 484 CMP [Rd], #data16 Bytes: Clocks: Operation: ((WS:Rd)) - #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 CMP [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) - #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 CMP [Rd+], #data16 Bytes: Clocks:...
Page 485 CMP [Rd+offset8], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset8) - #data16 Encoding: byte 3: offset8 byte 4: upper 8 bits of #data16 byte 5: lower 8 bits of #data16 CMP [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) - #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 CMP [Rd+offset16], #data16...
Page 486 CMP direct, #data16 Bytes: Clocks: Operation: (direct) - #data16 Encoding: 0 direct: 3 bits 0 byte 3: lower 8 bits of direct byte 4: upper 8 bits of #data16 byte 5: lower 8 bits of #data16 XA User Guide 6-86 4/17/98...
Page 487 Integer Ones Complement Syntax: CPL Rd Operation: Rd <-- (Rd) Description: Performs a ones complement of the destination operand specified by the register Rd. The result is stored back into Rd. The destination may be either a byte or a word. Size: Byte, Word Flags Updated: N, Z Bytes:...
Page 488 Decimal Adjust Syntax: DA Rd Operation: if (Rd.3-0) > 9 or (AC) = 1 then (Rd.3-0) <-- (Rd.3-0) + 6 if (Rd.7-4) > 9 or (C) = 1 then (Rd.7-4) <-- (Rd.7-4) + 6 Description: Adjusts the destination register to BCD format (binary-coded decimal) following an ADD or ADDC operation on BCD values.
Page 489 The following table shows the possible actions that may occur during the DA instruction, related to the input conditions. Table 6.6 Carry to High Number Low nibble Initial Resulting high nibble added to (bits 3-0) C ﬂag C ﬂag nibble (bits 7-4) value 0 - 9...
Page 490 DIV.w 16x8 Signed Division DIV.d 32x16 Signed Division DIVU.b Unsigned Division DIVU.w 16x8 Unsigned Division DIVU.d 32x16 Unsigned Division Description: The byte or word specified by the source operand is divided into the variable specified by the destination operand. For DIVU.b, the destination operand can be any byte register that is the least significant byte of a word register.
Page 491 Note: For all divides except DIVU.b, the destination register size is the same as indicated by the instruction (by the “.b”, “.w”, or “.d”) and the source register is half that size. DIV.w Rd, Rs (signed 16 bits / 8 bits --> 8 bit quotient, 8 bit remainder) Bytes: Clocks: Operation:...
Page 492 DIV.d Rd, #data16 (signed 32 bits / 16 bits --> 16 bit quotient, 16 bit remainder) Bytes: Clocks: Operation: (Rd) <-- 16-bit integer portion of (Rd) / #data16 (signed divide) (Rd+1) <-- 16-bit remainder of (Rd) / #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 DIVU.b Rd, Rs (unsigned 8 bits / 8 bits -->...
Page 493 DIVU.w Rd, Rs (unsigned 16 bits / 8 bits --> 8 bit quotient, 8 bit remainder) Bytes: Clocks: Operation: (RdL) <-- 8-bit integer portion of (Rd) / (Rs) (unsigned divide) (RdH) <-- 8-bit remainder of (Rd) / (Rs) Encoding: DIVU.w Rd, #data8 (unsigned 16 bits / 8 bits -->...
Page 494 DIVU.d Rd, #data16 (unsigned 32 bits / 16 bits --> 16 bit quotient, 16 bit remainder) Bytes: Clocks: Operation: (Rd) <-- 16-bit integer portion of (Rd) / #data16 (unsigned divide) (Rd+1) <-- 16-bit remainder of (Rd) / #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 XA User Guide 6-94...
Page 495 DJNZ Decrement and jump if not zero Syntax: DJNZ dest, rel8 Operation: (PC) <-- (PC) + 3 (dest) <-- (dest) - 1 if (Z) = 0 then (PC) <-- (PC + rel8*2); (PC.0) <-- 0 Description: Controls a loop of instructions. The parameters are: a condition code (Z), a counter (register or memory), and a displacement value.
Page 496 FCALL Far Call Subroutine Absolute Syntax: FCALL addr24 Operation: (PC) <-- (PC) + 4 (SP) <-- (SP) - 4 ((SP)) <-- (PC) (PC.23-0) <-- addr24 (PC.0) <-- 0 Description: Causes an unconditional branch to the absolute memory location specified by the second operand, anywhere in the 16 megabytes XA address space.
Page 497 FJMP Far Jump Absolute Syntax: FJMP addr24 Operation: (PC.23-0) <-- addr24 (PC. ) <-- 0 Description: Causes an unconditional branch to the absolute memory location specified by the second operand, anywhere in the 16 megabytes XA address space. Note: The target address must be word aligned as JMP always forces PC to an even address. Note: if the XA is in page 0 mode, only 16-bits of the address will be used.
Page 498 Relative Jump if bit set Syntax: JB bit, rel8 Operation: (PC) <-- (PC) + 4 if (bit) = 1 then (PC) <-- (PC + rel8*2); (PC.0) <-- 0 Description: If the specified bit is a one, program execution jumps at the location of the PC, plus the specified displacement.
Page 499 Jump if bit is set then clear bit Syntax: JBC bit, rel8 Operation: (PC) <-- (PC) + 4 if (bit) = 1 then (PC) <-- (PC + rel8*2); (PC.0) <-- 0; (bit) <-- 0 Description: If the bit specified is set, branch to the address pointed to by the PC plus the specified displacement.
Page 500 Relative Jump Syntax: rel16 Operation: (PC) <-- (PC) + 3 (PC) <-- (PC + rel16*2) (PC.0) <-- 0 Description: Jumps unconditionally. The branch range is +65,535 bytes to -65,536 bytes, with the limitation that the target address is word aligned in code memory. Note: Refer to section 6.3 for details of jump range Size: None Flags Updated: none...
Page 501 Jump Indirect through Register Syntax: JMP [Rs] Operation: (PC) <-- (PC) + 2 (PC.15-1) <-- (Rs.15-1) (note that PC. is not affected) 23-16 (PC.0) <-- 0 Description: Causes an unconditional branch to the address contained in the operand word register, anywhere within the 64K code page following the JMP instruction.The value of the PC used in the target address calculation is the address of the instruction following the JMP instruction.
Page 502 Jump indirect through register Syntax: JMP [A+DPTR] Operation: (PC) <-- (PC) + 2 (PC15-1) <-- (A) + (DPTR) (PC.0) <-- 0 Description: Causes an unconditional branch to the address formed by the sum of the 80C51 compatibility registers A and DPTR, anywhere within the 64K code page following the JMP instruction.
Page 503 Jump double indirect Syntax: JMP [[Rs+]] Operation: (PC) <-- (PC) + 2 (PC.15-0) <-- code memory ((WS:Rs)) (PC.0) <-- 0 (Rs) <-- (Rs) + 2 Description: Causes an unconditional branch to the address contained in memory at the address pointed to by the register specified in the instruction. The specified register is post-incremented. This 2-byte instruction may be used to compress code size by using it to index through a table of procedure addresses that are accessed in sequence.
Page 504 Jump if bit not set Syntax: JNB bit, rel8 Operation: (PC) <-- (PC) + 4 if (bit) = 0 then (PC.15-0) <-- (PC + rel8*2); (PC.0) <-- 0 Description: If the specified bit is a zero, program execution jumps at the location of the PC, plus the specified displacement.
Page 505 Jump if the A register is not zero Syntax: JNZ rel8 Operation: (PC) <-- (PC) + 2 if (A) not equal to 0, then (PC.15-0) <-- (PC + rel8*2); (PC.0) <-- 0 Description: A relative branch is taken if the contents of the 80C51 Accumulator are not zero. The branch range is +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory.
Page 506 Jump if the A register is zero Syntax: JZ rel8 Operation: (PC) <-- (PC) + 2 If (A) = 0 then (PC.15-0) <-- (PC + rel8*2); (PC.0) <-- 0 Description: A relative branch is taken if the contents of the 80C51 Accumulator are zero. The branch range is +254 bytes to -256 bytes, with the limitation that the target address is word aligned in code memory.
Page 507 Load effective address Syntax: LEA Rd, Rs+offset8/16 Operation: (Rd) <-- (Rs)+offset8/16 Description: The word specified by the source operand is added to the offset value and the result is stored into the register specified by the destination operand. The source and destination operands are both registers.
Page 508: Operation
Logical Shift Right Syntax: dest, count Operation: Do While (count not equal to 0) (C) <- (dest.0) (dest.bit n) <- (dest.bit n+1) (dest.msb) <- 0 count = count-1 End While Description: If the count operand is greater than the variable specified by the destination operand is logically shifted right by the number of bits specified by the count operand.
Page 509 LSR Rd, #data4 Rd, #data5 Operation: (Rd) Bytes: Clocks: For 8/16 bit shifts --> 4+1 for each 2 bits of shift For 32 bit shifts --> 6+1 for each 2 bits of shift Encoding: (for byte and word data sizes) SZ1 SZ0 #data4 (for double word data size)
Page 510 Move Data Syntax: MOV dest, src Operation: dest <- src Description: The byte or word specified by the source operand is copied into the variable specified by the destination operand. The source data is not affected by the operation. Source and destination operands may be a register in the register file, an indirect address specified by a pointer register, an indirect address specified by a pointer register added to an immediate offset of 8 or 16 bits, or a direct address.
Page 511 MOV [Rd], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- (Rs) Encoding: 0 SZ MOV Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- ((WS:Rs)+offset8) Encoding: 0 SZ byte 3: offset8 MOV [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- (Rs) Encoding: 0 SZ byte 3: offset8 MOV Rd, [Rs+offset16] Bytes: Clocks:...
Page 512 MOV [Rd+offset16], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- (Rs) Encoding: 0 SZ byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 MOV Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ MOV [Rd+], Rs...
Page 513 MOV direct, Rs Bytes: Clocks: Operation: (direct) <-- (Rs) Encoding: 0 SZ direct:3 bits byte 3: lower 8 bits of direct MOV Rd, direct Bytes: Clocks: Operation: (Rd) <-- (direct) Encoding: 0 SZ 0 direct:3 bits byte 3: lower 8 bits of direct MOV direct, [Rs] Bytes: Clocks:...
Page 514 MOV Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- #data8 Encoding: byte 3: #data8 MOV Rd, #data16 Bytes: Clocks: Operation: (Rd) <-- #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 MOV [Rd], #data8 Bytes: Clocks: Operation:...
Page 515 MOV [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 MOV [Rd+], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- #data16 (Rd) <-- (Rd) + 2 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 MOV [Rd+offset8], #data8 Bytes:...
Page 516 MOV [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 MOV [Rd+offset16], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- #data16 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: upper 8 bits of #data16 byte 6: lower 8 bits of #data16...
Page 517 MOV direct, direct Bytes: Clocks: Operation: (direct) <-- (direct) Encoding: 1 SZ 0 d dir: 3 bits s dir: 3 bits byte 3: lower 8 bits of direct (dest) byte 4: lower 8 bits of direct (src) MOV Rd, USP (move from user stack pointer) Bytes: Clocks: Operation:...
Page 518 Move Bit to Carry Syntax: MOV C, bit Operation: (C) <-- (bit) Description: Copies the specified bit to the carry flag. Size: Bit Flags Updated: none Note: C is written as the destination of the move, not as a status flag Bytes: Clocks: Encoding:...
Page 519 Move Carry to Bit Syntax: MOV bit, C Operation: (bit) <-- (C) Description: Copies the carry flag to the specified bit. Size: Bit Flags Updated: none Bytes: Clocks: Encoding: bit: 2 byte 3: lower 8 bits of bit address 4/17/98 6-119 Addressing Modes and Data Types...
Page 520 MOVC Move Code Syntax: MOVC Rd, [Rs+] Operation: (Rd) <-- code memory ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Description: Contents of code memory are copied to an internal register. The byte or word specified by the source operand is copied to the variable specified by the destination operand. In the case of MOVC, the pointer segment selection gives the choices of PC or CS segment 23-16...
Page 521 MOVC Move Code to A (DPTR) Syntax: MOVC A, [A+DPTR] Operation: PC <- PC+2 (A) <-- code memory (PC.23-16:(A) + (DPTR)) Description: The byte located at the code memory address formed by the sum of A and the DPTR is copied to the A register. The A and DPTR registers are pre-defined registers used for 80C51 compatibility.
Page 522 MOVC Move Code to A (PC) Syntax: MOVC A, [A+PC] Operation: PC <- PC+2 (A) <-- code memory [PC.23-16: (A +PC.15-0)] Note: Only 16-bits of A+PC are used Description: The byte located at the code memory address formed by the sum of A and the current Program Counter value is copied to the A register.
Page 523 MOVS Move Short Syntax: MOVS dest, #data Description: Four bits of signed immediate data are moved to the destination. The immediate data is sign-extended to the proper size, then moved to the variable specified by the destination operand, which may be a byte or a word. The immediate data range is +7 to -8. This instruction is used to save time and code space for the many instances where a small data constant is moved to a destination.
Page 524 MOVS [Rd+offset8], #data4 Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- sign-extended #data4 Encoding: 1 SZ #data4 byte 3: offset8 MOVS [Rd+offset16], #data4 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- sign-extended #data4 Encoding: 1 SZ #data4 byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 MOVS direct, #data4 Bytes: Clocks:...
Page 525 MOVX Move External Data Syntax: MOVX dest, src Description: Move external data to or from an internal register. The byte or word specified by the source operand is copied into the variable specified by the destination operand. This instruction allows access to data external to the microcontroller in the address range of 0 to 64K. The standard indirect move may access external data only above the boundary where internal data RAM ends, whereas MOVX always forces an external access.
Page 526 MUL.w 16x16 Signed Multiply MULU.b 8x8 Unsigned Multiply MULU.w 16x16 Unsigned Multiply Description: The byte or word specified by the source operand is multiplied by the variable specified by the destination operand. The destination operand must be the first half of a double size register (word for a byte multiply and double word for a word multiply).
Page 527 MUL.w Rd, Rs (signed 16 bits * 16 bits --> 32 bits) Bytes: Clocks: Operation: (Rd+1) <-- Most significant word of (Rd) * (Rs) (signed multiply) (Rd) <-- Least significant word of (Rd) * (Rs) Encoding: MUL.w Rd, #data16 (signed 16 bits * 16 bits --> 32 bits) Bytes: Clocks: Operation:...
Page 528 MULU.b Rd, #data8 (unsigned 8 bits * 8 bits --> 16 bits) Bytes: Clocks: Operation: (RdH) <-- Most significant byte of (RdL) * #data8 (unsigned multiply) (RdL) <-- Least significant byte of (RdL) * #data8 Encoding: byte 3: #data8 MULU.w Rd, Rs (unsigned 16 bits * 16 bits -->...
Page 529 Negate Syntax: NEG Rd Operation: Rd <-- (Rd) + 1 Description: The destination register is negated (twos complement). The destination may be a byte or a word. Size: Byte, Word Flags Updated: V, N, Z The V flag is set if a twos complement overflow occurred: the original value = result = 8000 hex for a word operation or 80 hex for a byte operation.
Page 530 No Operation Syntax: Operation: PC <- PC + 1 Description: Execution resumes at the following instruction. This instruction is defined as being one byte in length in order to allow it to be used to force word alignment of instructions that are branch targets, or for any other purpose.
Page 531: Operation
NORM Normalize Syntax: NORM Rd, Rs Operation: (Rd) Description: Logically shifts left the contents of the destination until the MSB is set, storing the number of shifts performed in the count (source) register. The data size may be 8, 16, or 32 bits. If the destination value already has the MSB set, the count returned will be 0.
Page 532 Logical OR Syntax: OR dest, src Description: Bitwise logical OR the contents of the source to the destination. The byte or word specified by the source operand is logically ORed to the variable specified by the destination operand. The source data is not affected by the operation. Size: Byte-Byte, Word-Word Flags Updated: N, Z OR Rd, Rs...
Page 533 OR Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset8) Encoding: 0 SZ byte 3: offset8 OR [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) + (Rs) Encoding: 0 SZ byte 3: offset8 OR Rd, [Rs+offset16] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)+offset16) Encoding: 0 SZ...
Page 534 OR Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) + ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ OR [Rd+], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + (Rs) (Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ OR direct, Rs...
Page 535 OR Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) + #data8 Encoding: byte 3: #data8 OR Rd, #data16 Bytes: Clocks: Operation: (Rd) <-- (Rd) + #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 OR [Rd], #data8 Bytes: Clocks:...
Page 536 OR [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 OR [Rd+], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) + #data16 (Rd) <-- (Rd) + 2 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 OR [Rd+offset8], #data8 Bytes:...
Page 537 OR [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 OR [Rd+offset16], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) + #data16 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 538 Logical OR bit Syntax: ORL C, bit Operation:(C) <-- (C) + (bit) Description: Logical (inclusive) OR a bit to the Carry flag. Read the specified bit and logically OR it to the Carry flag. (C is written as the destination of the ORL, not as a status flag) Size: Bit Flags Updated: none Bytes:...
Page 539 Logical OR complement of bit Syntax: ORL C, /bit Operation: (C) <-- (C) + (bit) Description: Logically OR the complement of a bit to the Carry flag. Read the specified bit, complement it, and logically OR it to the Carry flag. (C is written as the destination of the move, not as a status flag) Flags Updated: none Bytes:...
Page 540 POPU Pop User Syntax: POP dest Description: The stack is popped and the data written to the specified directly addressed location. The data size may be byte or word. POP uses the current stack pointer, while POPU forces an access to the user stack. Size: Byte, Word Flags Updated: none POP direct...
Page 541 Pop Multiple POPU Pop User Multiple Syntax: Rlist POPU Rlist Description: Pop the specified registers (one or more) from the stack. The stack is popped (from 1 to 8 times) and the data stored in the specified registers. Any combination of word registers in the group R0 to R7 may be popped in a single instruction in a word operation.
Page 542 Rlist bit definitions for a byte POP from register(s) in the upper register group (R4L through R7H): Rlist bit definitions for a byte POP from register(s) in the lower register group (R0L through R3H): Rlist bit definitions for a word POP from any register(s) (R0 through R7): XA User Guide 6-142 4/17/98...
Page 543 PUSH Push PUSHU Push User Syntax: PUSH PUSHU Description: The specified directly addressed data is pushed onto the stack. The data size may be byte or word. PUSH uses the current stack pointer, while PUSHU forces an access to the user stack. Size: Byte, Word Flags Updated: none PUSH direct...
Page 544 PUSH Push Multiple PUSHU Push User Multiple Syntax: PUSH Rlist PUSHU Rlist Description: Push the specified registers (one or more) onto the stack. The specified registers are pushed onto the stack. Any combination of word registers in the group R0 to R7 may be pushed in a single instruction in a word operation.
Page 545 Rlist bit definitions for a byte PUSH from register(s) in the upper register group (R4L through R7H): Rlist bit definitions for a byte PUSH from register(s) in the lower register group (R0L through R3H): Rlist bit definitions for a word PUSH from any register(s) (R0 through R7): 4/17/98 6-145 Addressing Modes and Data Types...
Page 546: Software Reset
RESET Software Reset Syntax: RESET Operation: (PC) <-- vector(0) (PSW) <-- vector(0) (SFRs) <-- reset values (refer to the description of reset for details) Description: The chip is reset exactly as if the external hardware reset has been asserted with the exception that it does not sample inputs for configuration, e.g., EA, BUSW, etc.
Page 547 Return from Subroutine Syntax: Operation: (PC) <-- ((SP)) (SP) <-- (SP) + 4 Description: A 24-bit return address is popped from the stack and used to replace the entire program counter value (PC ). This instruction is used to return from a subroutine that was called 23-0 with a CALL or Far Call (FCALL).
Page 548: Return From Interrupt
RETI Return from Interrupt Syntax: RETI Operation: (PSW) <-- ((SSP)) (PC.23-0) <-- ((SSP)) (SSP) <-- (SSP) + 6 Description: A 24-bit return address is popped from the stack and used to replace the entire program counter value. The Program Status Word is also restored by being popped from the stack. This instruction is a privileged instruction (limited to system mode) and is used to return from an interrupt/exception.
Page 549: Rotate Left
Rotate Left Syntax: RL Rd, #data4 Operation: (Rd) count <- #data4 Do While (count not equal to 0) (dest ) <- (dest (dest ) <- (dest (count) <- count -1 End While Description: The variable specified by the destination operand is rotated left by the number of bits specified in the immediate data operand.
Page 550 Rotate Left Through Carry Syntax: RLC Rd, #data4 Operation: (Rd) count <- #data4 Do While (count not equal to 0) (temp) <- (C) (C) <- (dest (dest ) <- (dest (dest ) <- (temp) (count) <- count -1 End While Description: The variable specified by the destination operand is rotated left through the carry flag by the number of bits specified in the immediate data operand.
Page 551: Rotate Right
Rotate Right Syntax: RR Rd, #data4 Operation: (Rd) count <- #data4 Do While (count not equal to 0) (dest ) <- (dest (dest ) <- (dest (count) <- count -1 End While Description: If the count operand is greater than 0, the destination operand is rotated right by the number of bits specified in the immediate data operand.
Page 552 Rotate Right Through Carry Syntax: RRC Rd, #data4 Operation: (Rd) count <- #data4 Do While (count not equal to 0) (temp) <- (C) (C) <- (dest (dest ) <- (dest (dest ) <- (temp) (count) <- count -1 End While Description: If the count operand is greater than 0, the destination operand is rotated right through the carry flag by the number of bits specified in the immediate data operand.
Page 553 SETB Set Bit Syntax: SETB bit Operation: (bit) <-- 1 Description: Writes (sets) a 1 to the specified bit. Size: Bit Flags Updated:none Bytes: Clocks: Encoding: bit: 2 byte 3: lower 8 bits of bit address 4/17/98 6-153 Addressing Modes and Data Types...
Page 554 SEXT Sign Extend Syntax: SEXT Rd Operation: if N = 1 then (Rd) <-- FF in byte mode or FFFF in word mode if N = 0 then (Rd) <-- 00 in byte mode or 0000 in word mode Description: Copies the N flag (the sign bit of the last ALU operation) into the destination register. The destination register may be a byte or word register.
Page 555 Integer Subtract Syntax: SUB dest, src Operation: dest <- dest - src Description: Performs a twos complement binary subtraction of the source and destination operands, and the result is placed in the destination operand. The source data is not affected by the operation.
Page 556 SUB Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) - ((WS:Rs)+offset8) Encoding: 0 SZ byte 3: offset8 SUB [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) - (Rs) Encoding: 0 SZ byte 3: offset8 SUB Rd, [Rs+offset16] Bytes: Clocks: Operation: (Rd) <-- (Rd) - ((WS:Rs)+offset16) Encoding: 0 SZ...
Page 557 SUB Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) - ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ SUB [Rd+], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) - (Rs) (Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation) Encoding: 0 SZ SUB direct, Rs...
Page 558 SUB Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) - #data8 Encoding: byte 3: #data8 SUB Rd, #data16 Bytes: Clocks: Operation: (Rd) <-- (Rd) - #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 SUB [Rd], #data8 Bytes: Clocks:...
Page 559 SUB [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) - #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 SUB [Rd+], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) - #data16 (Rd) <-- (Rd) + 2 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 SUB [Rd+offset8], #data8 Bytes:...
Page 560 SUB [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) - #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 SUB [Rd+offset16], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) - #data16 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 561 SUBB Subtract with Borrow Syntax: SUBB dest, src Operation: dest <- dest - src - C Description: Performs a twos complement binary addition of the source operand and the previously generated carry bit (borrow) with the destination operand. The result is stored in the destination operand.The source data is not affected by the operation.
Page 562 SUBB [Rd], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) - (Rs) - (C) Encoding: 1 SZ SUBB Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) - ((WS:Rs)+offset8) - (C) Encoding: 1 SZ byte 3: offset8 SUBB [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) - (Rs) - (C) Encoding:...
Page 563 SUBB [Rd+offset16], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) - (Rs) - (C) Encoding: 1 SZ byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 SUBB Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) - ((WS:Rs)) - (C) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 1 SZ...
Page 564 SUBB Rd, direct Bytes: Clocks: Operation: (Rd) <-- (Rd) - (direct) - (C) Encoding: 1 SZ direct: 3 bits byte 3: lower 8 bits of direct SUBB Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) - #data8 - (C) Encoding: byte 3: #data8 SUBB Rd, #data16 Bytes:...
Page 565 SUBB [Rd], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) - #data16 - (C) Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 SUBB [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) - #data8 - (C) (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8...
Page 566 SUBB [Rd+offset8], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) - #data16 - (C) Encoding: byte 3: offset8 byte 4: upper 8 bits of #data16 byte 5: lower 8 bits of #data16 SUBB [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) - #data8 - (C) Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 567 byte 3: lower 8 bits of direct byte 4: #data8 SUBB direct, #data16 Bytes: Clocks: Operation: (direct) <-- (direct) - #data16 - (C) Encoding: 0 direct: 3 bits 0 byte 3: lower 8 bits of direct byte 4: upper 8 bits of #data16 byte 5: lower 8 bits of #data16 4/17/98 6-167...
Page 568 TRAP Software Trap Syntax: TRAP #data4 Operation: (PC) <-- (PC) + 2 (SSP) <-- (SSP) - 6 ((SSP)) <-- (PC) ((SSP)) <-- (PSW) (PSW) <-- code memory (trap vector (#data4)) (PC. ) <-- code memory (trap vector (#data4)) 15-0 (PC. ) <-- 0;...
Page 569 Exchange Syntax: XCH dest, src Operation: dest <--> src Description: The data specified by the source and destination operands is exchanged. Size: Byte-Byte, word-word. Flags Updated: none XCH Rd, Rs Bytes: Clocks: Operation: (Rd) <--> (Rs) Encoding: 0 SZ XCH Rd, [Rs] Bytes: Clocks: Operation:...
Page 570 Exclusive OR Syntax: XOR dest, src Operation: dest <- dest (XOR) Description: The byte or word specified by the source operand is bitwise logically XORed to the variable specified by the destination operand. The source data is not affected by the operation. Size: Byte-Byte, Word-Word Flags Updated: N, Z XOR Rd, Rs...
Page 571 XOR Rd, [Rs+offset8] Bytes: Clocks: Operation: (Rd) <-- (Rd) (XOR) ((WS:Rs)+offset8) Encoding: 1 SZ byte 3: offset8 XOR [Rd+offset8], Rs Bytes: Clocks: Operation: ((WS:Rd)+offset8) <-- ((WS:Rd)+offset8) (XOR) (Rs) Encoding: 1 SZ byte 3: offset8 XOR Rd, [Rs+offset16] Bytes: Clocks: Operation: (Rd) <-- (Rd) (XOR) ((WS:Rs)+offset16) Encoding: 1 SZ...
Page 572 XOR Rd, [Rs+] Bytes: Clocks: Operation: (Rd) <-- (Rd) (XOR) ((WS:Rs)) (Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation) Encoding: 1 SZ XOR [Rd+], Rs Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) (XOR) (Rs) (Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation) Encoding: 1 SZ XOR direct, Rs...
Page 573 XOR Rd, #data8 Bytes: Clocks: Operation: (Rd) <-- (Rd) (XOR) #data8 Encoding: byte 3: #data8 XOR Rd, #data16 Bytes: Clocks: Operation: (Rd) <-- (Rd) (XOR) #data16 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 XOR [Rd], #data8 Bytes: Clocks:...
Page 574 XOR [Rd+], #data8 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) (XOR) #data8 (Rd) <-- (Rd) + 1 Encoding: byte 3: #data8 XOR [Rd+], #data16 Bytes: Clocks: Operation: ((WS:Rd)) <-- ((WS:Rd)) (XOR) #data16 (Rd) <-- (Rd) + 2 Encoding: byte 3: upper 8 bits of #data16 byte 4: lower 8 bits of #data16 XOR [Rd+offset8], #data8 Bytes:...
Page 575 XOR [Rd+offset16], #data8 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) (XOR) #data8 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16 byte 5: #data8 XOR [Rd+offset16], #data16 Bytes: Clocks: Operation: ((WS:Rd)+offset16) <-- ((WS:Rd)+offset16) (XOR) #data16 Encoding: byte 3: upper 8 bits of offset16 byte 4: lower 8 bits of offset16...
Page 576 6.6 Summary Of Illegal Operand Combinations On The XA All but one case are instructions that specify or imply 2 write operations to a single register file location within a single instruction. The other case is a possible corruption of the source register data by an auto-increment before it is read.
Page 577 7 External Bus Most XA derivatives have the capability of accessing external code and/or data memory through the use of an external bus. The external bus provides address information to external devices that are to be accessed, then generates a strobe for the required operation, with data passing in or out on the data bus.
Page 578: Address Lines
subsequent read or write operation. The active high ALE signal directs the external latch to allow information to be stored for a data address or a code address. The external latch must close and retain this address when the ALE signal ends, by going low (inactive). 7.1.6 Address Lines Some of the address lines used by the external bus interface are driven during a complete bus operation and do not need to be latched.
Page 579: Bus Configuration
7.1.10 BUSW - Bus Width The external XA bus may be configured to be 8 or 16 bits in width. The XA allows the bus width to be programmed in 2 ways. In a system where instructions are initially fetched from on-chip code memory, the user program can configure the external bus size (and many other aspects of the bus) prior to the bus actually being used.
Page 580 WAITD BUSD WAITD: WAIT disable. Causes the XA external bus interface to ignore the value on the WAIT input. This allows tying the WAIT input high for applications that use internal code and do not need the WAIT function. BUSD: Bus disable.
Page 581 Figures 7.2 and 7.3 show the address and data functions present on XA bus related pins when used with each available bus width. 4 low order address lines, A3 - A0 always driven 8 multiplexed address A4 - A11/ and data lines D0 - D7 Up to 12 high order address A12 - A23...
Page 582 A4D0- A4 - A11 A11D7 8-bit peripheral device D0 - D7 A3 - A0, A3 - A0, (A12 - A19) (A12 - A19) Address decode for data device for code PSEN device Figure 7.4 Typical XA External Bus Connections for 8-Bit Peripheral Devices Address decode A4D0-...
Page 583 7.3 Bus Timing and Sequences The standard XA external bus allows programming the widths of the bus control signals ALE, PSEN, WRL, WRH, and RD. There is also an option to extend the data hold time after a write operation. The combinations available will allow interfacing most devices to the XA directly without the need for special buffers or a WAIT state generator.
Page 584 XTAL1 Address bus Address/ address instruction data Data bus PSEN Note: the timing of this type of bus operation is user programmable. The timing shown here is generated by the Bus Timing Register setup: ALEW = 0, CRA1/0 = 01. Figure 7.6 Typical External Code Read Using ALE The following diagram shows a typical sequential code fetch where no ALE is issued between code reads.
Page 585 7.3.2 Data Memory Reads and writes on the XA external bus are controlled through the use of the RD, WRL, and WRH signals. Since the XA bus supports both 8-bit and 16-bit widths, as well as byte and word read and write operations, several different versions of the basic bus cycles are possible. These are described in the following sections.
Page 586 Word Read on an 8-Bit Data Bus When the XA external bus is configured for an 8-bit data width, a word read operation is automatically performed as two byte reads at sequential addresses. Since the XA CPU requires word operations to be performed at even addresses, the second half of any word read on a byte- wide bus always uses the same upper address latched by ALE.
Page 587 Typical Data Write A data write operation begins with an ALE cycle, like a read operation, followed by the assertion of one or both of the write strobes, WRL and WRH. This simple bus cycle applies to byte writes on an 8-bit data bus and all writes on a 16-bit data bus. A byte write on an 8-bit data bus will always use only the WRL strobe.
Page 588 Word Write on an 8-Bit Data Bus When a word write operation is done with the bus configured to an 8-bit width, the XA automatically performs two byte writes. First, the low order byte is written (at the even byte address), then the high order byte is written at the next (odd) address.
Page 589 External Bus Signal Timing Configuration The standard XA bus also provides a high degree of bus timing configurability. There are separate controls for ALE width, data read and write cycle lengths, and data hold time. These times are programmable in a range that will support most RAMs, ROMs, EPROMs, and peripheral devices over a wide range of oscillator frequencies without the need for additional external latches, buffers, or WAIT state generators.
Page 590 ALEW CRA1 CRA0 BTRL WM1: Write Mode 1. Selects the width of the write pulse. 0 : Write pulse (WR) width is 1 CPU clock. 1 : Write pulse (WR) width is 2 CPU clocks. WM0: Write Mode 0. Selects the data hold time. 0 : Data hold time is minimum (0 clocks).
Page 591: Reset Configuration
Disallowed Bus Timing Configurations Some possible combinations of bus timing register settings do not make sense and the XA cannot produce working bus signals that match those settings. The disallowed combinations occur where the sum of the specified components of a bus cycle exceed the specified length of the entire cycle.
Page 592: I/O Port Access
7.4 Ports I/O ports on any microcontroller provide a connection to the outside world. The capabilities of those I/O ports determine how easily the microcontroller can be interfaced to the various external devices that make up a complete application. The standard XA I/O ports provide a high degree of versatility through the use of programmable output modes and allow easy connection to a wide variety of hardware.
Page 593 7.4.2 Port Output Configurations Standard XA I/O ports provide several different output configurations. One is the 80C51 type quasi-bidirectional port output. Others are open drain, push-pull, and high impedance (input only). It is important to note that the port configuration applies to a pin even if that pin is part of the external bus.
Page 594 The third (and final) pullup is referred to as the "strong" pullup. This pullup is included to speed up low-to-high transitions on a port pin when the port latch changes from 0 to 1. When this occurs, the strong pullup turns on for a brief time, two CPU clocks, pulling the port pin high quickly, then turning off again.
Page 595: Open Drain Output
Open Drain Output Another port output configuration provided by the standard XA I/O ports is open drain. This configuration turns off all pullups and only drives the pulldown transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pullup, typically a resistor tied to Vdd.
Page 596 High Impedance Output The final XA port output configuration is called high impedance mode. This mode simply turns all output drivers on a port pin off. Thus, the pin will not source or sink current and may be used effectively as an input-only pin with no internal drivers for an external device to overcome. 7.4.4 Reset State and Initialization Upon chip reset, all of the port output configurations are set to quasi-bidirectional, and the port latches are written with all ones.
Page 597 8 Special Function Register Bus The Special Function Register Bus or SFR Bus is the means by which all Special Function Registers are connected to the XA CPU so that they may be read and written by user programs. This includes all of the registers contained in peripherals such as Timers and UARTs, as well as some CPU registers such as the PSW.
Page 598 The SFR bus implementation on initial XA derivatives is an 8-bit interface. This means that word reads and writes are not allowed. In the future, higher performance XA architecture implementations may expand the capabilities of the SFR bus by supporting 16-bit accesses. One enhancement to the SFR bus would be to have it divide 16-bit access requests into two 8-bit accesses.
Page 599: Compatibility Considerations
9 80C51 Compatibility Many architectural decisions and features were guided by the goal of 80C51 compatibility when the XA core specification was written. The processor's memory configuration, memory addressing modes, instruction set, and many other things had to be taken into account. 9.1 Compatibility Considerations Source code compatibility of the XA to the 80C51 was chosen as a goal for many reasons.
Page 600 R6H = DPH R6L = DPL DPTR Global registers. R4L = A (ACC) R4H = B Banked Registers Figure 9.1. XA Register File Other important registers of the 80C51 are provided in other ways. The program status word (PSW) of the XA is slightly different than the 80C51 PSW, so a special SFR address is reserved to provide an 80C51 compatible "view"...
Page 601 The 80C51 mapped the special function registers (SFRs) into the direct address space, from address 80 hex to FF hex. SFRs were only accessed by instruction that contain the entire SFR address, so translation to the XA is fairly simple. Since references to SFRs are normally done by their name in 80C51 source code, the translation just copies the name into the XA code output.
Page 602: On-Chip Peripherals
different (and much more powerful) than any 80C51 derivative, and will require minor changes to code that is translated. The method of entering an interrupt routine in the XA uses a vector table stored in low addresses of the code memory. Each interrupt or exception source has a vector which consists of the address of the handler routine for that event and a new PSW value that is loaded when the vector is taken.
Page 603 The XA, however, uses only as many clocks as are needed to execute each instruction, so an ALE for every fetch would slow things down considerably. With this change, up to 16 bytes (or 8 words) of code may be accessed without the need to insert an ALE cycle on the XA bus. The number of XA clocks used for each type of bus cycle (code read, data read, or data write) can also be programmed, so that slower peripheral devices can work with the XA without the need for an external WAIT state generator.
Page 604 Since the XA optimizes the timing of each instruction, there will be very little correspondence to the original 80C51 timing for the same code prior to translation to the XA. If the exact timing of a sequence of instructions is important to the application, the translated code must be altered, perhaps by adding NOPs or delay loops, to provide the necessary timing.
Page 605 In this case, the translated code actually changed very little. Primarily, the 80C51 register names have been replaced by the new ones reserved for them in the XA. The increment (INC) instruction became a short add (ADDS), and the mnemonic for multiply (MUL) changed to MULU8.
Page 606 9.2 Code Translation Table 9.2 shows every 80C51 instruction type and the XA instruction that replaces it. An actual 80C51 to XA source code translator can make use of this table, but must also flag the compatibility exceptions noted in this section, so that any necessary adjustments may be made to the resulting XA source code.
Page 607 Table 9.2: 80C51 to XA Instruction Translations 80C51 Instruction XA Translation Logical operations A, Rn AND.b R, R A, #data8 AND.b R, #data8 A, dir8 AND.b R, direct A, @Ri AND.b R, [R] dir8, A AND.b direct, R dir8, #data8 AND.b direct, #data8 A, Rn OR.b...
Page 608 Table 9.2: 80C51 to XA Instruction Translations 80C51 Instruction XA Translation Data transfer A, Rn MOV.b R, R A, #data8 MOV.b R, #data8 A, dir8 MOV.b R, direct A, @Ri MOV.b R, [R] Rn, A MOV.b R, R Rn, #data8 MOV.b R, #data8 Rn, dir8 MOV.b R, direct...
Page 609 Table 9.2: 80C51 to XA Instruction Translations 80C51 Instruction XA Translation Relative branches SJMP rel8 rel8 CJNE A, dir8, rel CJNE.b R, direct, rel CJNE A, #data8, rel CJNE.b R, #data8, rel CJNE Rn, #data8, rel CJNE.b R, #data8, rel CJNE @Ri, #data8, rel CJNE.b [R], #data8, rel DJNZ Rn, rel...
Page 610 Table 9.3: Instructions and addressing modes new to the XA New Instructions and Addressing Modes alu.w ..., ... All of the 80C51 arithmetic and logic instructions with a 16-bit data size. SUBB R,... Subtract (without borrow), all addressing modes. [R], R Arithmetic and logic operations (ADD, ADDC, SUB, SUBB, CMPAND, OR, XOR, and MOV) from a register to an indirect address.
Page 611 Table 9.3: Instructions and addressing modes new to the XA New Instructions and Addressing Modes ADDS [R+], #data4 Add a short value to an indirect offset address, with the indirect pointer automatically incremented. ADDS [R+offset8/16], #data4 Add a short value to an indirect offset address (with 8 or 16-bit offset).
Page 612 Table 9.3: Instructions and addressing modes new to the XA New Instructions and Addressing Modes MULU R, #data8/16 Unsigned multiply of 16 bit register by 16 bit immediate, or 8 bit register by 8 bit immediate. R, R+offset8/16 Load effective address, duplicates the offset8 or 16-bit addressing mode calculation but saves the address in a register.
Page 613 Table 9.3: Instructions and addressing modes new to the XA New Instructions and Addressing Modes FCALL addr24 Far call, anywhere within the XA 16Mbyte code address space. Jump indirect, to an address contained in a register. rel16 Jump anywhere in a +/- 64K range. FJMP addr24 Far jump, anywhere within the XA 16Mbyte code address space.
Page 614 XA User Guide 9-16 3/24/97...
Page 615 80C32/80C52 CMOS 0 to 44 MHz Single Chip 8–bit Microntroller Description TEMIC’s 80C52 and 80C32 are high performance CMOS modes of reduced activity for further reduction in power versions of the 8052/8032 NMOS single chip 8 bit µC. consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial port and the interrupt The fully static design of the TEMIC 80C52/80C32 system continue to function.
Page 616 80C32/80C52 Interface Figure 1. Block Diagram MATRA MHS Rev. G (14 Jan. 97)
Page 617 80C32/80C52 Figure 2. Pin Configuration P1.5 P0.4/A4 P1.6 P0.5/A5 P0.6/A6 P1.7 P0.7/A7 RxD/P3.0 80C32/80C52 TxD/P3.1 INT0/P3.2 PSEN INT1/P3.3 P2.7/A14 P2.6/A13 T0/P3.4 T1/P3.5 P2.5/A12 P /A4 P /A5 P /A6 P /A7 RxD/P 80C32/80C52 TxD/P INT0/P PSEN INT1/P P /A15 T0/P P /A14 T1/P P /A13...
Page 618: Pin Description
80C32/80C52 Pin Description Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when Circuit ground potential. emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register.
Page 619 80C32/80C52 PSEN 1 FFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must not be floated. Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine XTAL1 cycle during fetches from external Program Memory.
Page 620 80C32/80C52 There are three ways to terminate the Idle mode. Power Down Mode Activation of any enabled interrupt will cause PCON.0 to The instruction that sets PCON.1 is the last executed prior be cleared by hardware, terminating Idle mode. The to entering power down.
Page 621: Hardware Description
80C32/80C52 When the port latch contains a 0, all pFETS in figure 4 are Figure 5. Crystal Oscillator. off while the nFET is turned on. When the port latch makes a 0-to-1 transition, the nFET turns off. The strong pFET, T1, turns on for two oscillator periods, pulling the output high very rapidly.
Page 622 80C32/80C52 The capture mode is illustrated in Figure 7. with the 16 bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a Figure 7.
Page 623 80C32/80C52 80C52 with Secret ROM 80C52 with Secret TAG TEMIC offers 80C52 with the encrypted secret ROM TEMIC offers special 64-bit identifier called “SECRET option to secure the ROM code contained in the 80C52 TAG” on the microcontroller chip. microcontrollers. The Secret Tag option is available on both ROMless and The clear reading of the program contained in the ROM masked microcontrollers.
Page 624 80C32/80C52 Electrical Characteristics * Notice Absolute Maximum Ratings* Stresses at or above those listed under “ Absolute Maximum Ratings” Ambiant Temperature Under Bias : may cause permanent damage to the device. This is a stress rating only C = commercial .
Page 625 80C32/80C52 Absolute Maximum Ratings* * Notice Stresses above those listed under “ Absolute Maximum Ratings” may Ambient Temperature Under Bias : cause permanent damage to the device. This is a stress rating only and A = Automotive ......–40 to +125 functional operation of the device at these or any other conditions above...
Page 626 80C32/80C52 Absolute Maximum Ratings* * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” Ambient Temperature Under Bias : may cause permanent damage to the device. This is a stress rating only M = Military ....... –55 to +125 and functional operation of the device at these or any other conditions...
Page 627 80C32/80C52 Absolute Maximum Ratings* * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” Ambient Temperature Under Bias : may cause permanent damage to the device. This is a stress rating only C = Commercial ....... . to 70 and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is...
Page 628 80C32/80C52 Note 1 : ICC is measured with all output pins Figure 9. ICC Test Condition, Idle Mode. disconnected ; XTAL1 driven with TCLCH, TCHCL = All other pins are disconnected. 5 ns, VIL = VSS + .5 V, VIH = VCC –.5 V ; XTAL2 N.C.
Page 629 80C32/80C52 Explanation of the AC Symbol Each timing symbol has 5 characters. The first character Example : is always a “T” (stands for time). The other characters, TAVLL = Time for Address Valid to ALE low. depending on their positions, stand for the name of a TLLPL = Time for ALE low to PSEN low.
Page 630 80C32/80C52 External Data Memory Characteristics (values in ns) 16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz SYM- PARAMETER min max min max min max min max min max min max min max min max TRLRH RD pulse Width TWLWH...
Page 631 80C32/80C52 Serial Port Timing – Shift Register Mode (values in ns) 16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz SYM- PARAMETER min max min max min max min max min max min max min max min max TXLXL Serial Port Clock Cycle Time TQVXH...
Page 632 80C32/80C52 External Clock Drive Characteristics (XTAL1) SYMBOL PARAMETER UNIT FCLCL Oscillator Frequency TCLCL Oscillator period 22.7 TCHCX High Time TCLCX Low Time TCLCH Rise Time TCHCL Fall Time External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at VIH min for a logic “1”...
Page 633: Clock Waveforms
80C32/80C52 Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading.
Page 634: Ordering Information
80C32/80C52 Ordering Information 80C52C Part Number 80C52 Rom 8 K 8 –12 : 12 MHz version 80C32 External ROM –16 : 16 MHz version 80C52C Secret ROM version –20 : 20 MHz version 80C52T Secret Tag version Temperature Range –25 : 25 MHz version 80C32E Radiation Tolerant blank : Commercial...
Page 635 82C55A CMOS Programmable Peripheral Interface June 1998 Features Description • Pin Compatible with NMOS 8255A The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a • 24 Programmable I/O Pins self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be •...
Page 636 82C55A Pin Description SYMBOL NUMBER TYPE DESCRIPTION : The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. GROUND D0-D7 27-34 DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
Page 637 82C55A Functional Description PA7- POWER GROUP A Data Bus Buffer GROUP A PORT A SUPPLIES CONTROL This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or PC7- received by the buffer upon execution of input or output GROUP A PORT C BI-DIRECTIONAL...
Page 638 82C55A Ports A, B, and C register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a The 82C55A contains three 8-bit ports (A, B, and C). All can single output instruction. This allows a single 82C55A to be conﬁgured to a wide variety of functional characteristics service a variety of peripheral devices with a simple software by the system software but each has its own special features...
Page 639: Operating Modes
82C55A The modes for Port A and Port B can be separately deﬁned, This function allows the programmer to enable or disable a while Port C is divided into two portions as required by the CPU interrupt by a speciﬁc I/O device without affecting any Port A and Port B deﬁnitions.
Page 640: Control Word
82C55A Mode 0 (Basic Input) INPUT CS, A1, A0 D7-D0 Mode 0 (Basic Output) D7-D0 CS, A1, A0 OUTPUT Mode 0 Conﬁgurations CONTROL WORD #0 CONTROL WORD #2 PA7 - PA0 PA7 - PA0 82C55A 82C55A PC7 - PC4 PC7 - PC4 D7 - D0 D7 - D0 PC3 - PC0...
Page 641 82C55A Mode 0 Conﬁgurations (Continued) CONTROL WORD #4 CONTROL WORD #8 PA7 - PA0 PA7 - PA0 82C55A 82C55A PC7 - PC4 PC7 - PC4 D7 - D0 D7 - D0 PC3 - PC0 PC3 - PC0 PB7 - PB0 PB7 - PB0 CONTROL WORD #5 CONTROL WORD #9...
Page 642 82C55A Mode 0 Conﬁgurations (Continued) CONTROL WORD #12 CONTROL WORD #14 PA7 - PA0 PA7 - PA0 82C55A 82C55A PC7 - PC4 PC7 - PC4 D7 - D0 D7 - D0 PC3 - PC0 PC3 - PC0 PB7 - PB0 PB7 - PB0 CONTROL WORD #13 CONTROL WORD #15...
Page 643 82C55A tSIB tSIT tRIB INTR tRIT INPUT FROM PERIPHERAL FIGURE 7. MODE 1 (STROBED INPUT) INTR (Interrupt Request) INTE A A “high” on this output can be used to interrupt the CPU Controlled by Bit Set/Reset of PC6. when and input device is requesting service. INTR is set by INTE B the condition: STB is a “one”, IBF is a “one”...
Page 644 82C55A tWOB tAOB INTR tWIT tAIT OUTPUT FIGURE 9. MODE 1 (STROBED OUTPUT) PA7-PA0 PA7-PA0 STBA OBFA CONTROL WORD CONTROL WORD IIBFA ACKA D3 D2 D1 D0 D3 D2 D1 D0 INTRA INTRA PC6, PC7 PC4, PC5 PC6, PC7 PC4, PC5 1 = INPUT 1 = INPUT PB7, PB0...
Page 645 82C55A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 INTRA 1/0 1/0 PA7-PA0 OBFA INTE ACKA PC2-PC0 1 = INPUT 0 = OUTPUT INTE STBA PORT B 1 = INPUT 0 = OUTPUT IBFA GROUP B MODE 0 = MODE 0 1 = MODE 1 PC2-PC0 FIGURE 11.
Page 646 82C55A MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) INTRA INTRA PA7-PA0 PA7-PA0 OBFA OBFA CONTROL WORD CONTROL WORD ACKA ACKA D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 STBA STBA PC2-PC0 PC2-PC0...
Page 647 82C55A MODE DEFINITION SUMMARY MODE 0 MODE 1 MODE 2 GROUP A ONLY Mode 0 or Mode 1 Only INTRB INTRB IBFB OBFB STBB ACKB INTRA INTRA INTRA STBA STBA IBFA IBFA ACKA ACKA OBFA OBFA Special Mode Combination Considerations INPUT CONFIGURATION There are several combinations of modes possible.
Page 648 82C55A Applications of the 82C55A Reading Port C Status (Figures 15 and 16) In Mode 0, Port C transfers data to or from the peripheral The 82C55A is a very powerful tool for interfacing peripheral device. When the 82C55A is programmed to function in equipment to the microcomputer system.
Page 649 82C55A INTERRUPT REQUEST FULLY INTERRUPT DECODED REQUEST KEYBOARD MODE 1 SHIFT (INPUT) CONTROL FULLY DECODED STROBE KEYBOARD MODE 1 SHIFT (INPUT) CONTROL 82C55A STROBE 82C55A BURROUGHS BUST LT SELF-SCAN TEST LT DISPLAY MODE 1 TERMINAL (OUTPUT) BACKSPACE ADDRESS CLEAR MODE 0 DATA READY (INPUT) BLANKING...
Page 650 82C55A INTERRUPT INTERRUPT REQUEST REQUEST FLOPPY DISK B LEVEL CONTROLLER PAPER AND DRIVE TAPE READER MODE 1 MODE 2 (INPUT) DATA STB ACK (IN) DATA READY STOP/GO ACK (OUT) MACHINE TOOL 82C55A 82C55A TRACK “0” SENSOR START/STOP MODE 0 SYNC READY LIMIT SENSOR (H/V) (INPUT) INDEX...
Page 651 82C55A Absolute Maximum Ratings Thermal Information = 25 θ θ Supply Voltage ........+8.0V Thermal Resistance (Typical, Note 1) Input, Output or I/O Voltage .
Page 652 82C55A AC Electrical Speciﬁcations = +5V± 10%, GND = 0V; T = -55 C to +125 C (M82C55A) (M82C55A-5); = -40 C to +85 C (I82C55A) (I82C55A-5); C to +70 C (C82C55A) (C82C55A-5) 82C55A-5 82C55A TEST SYMBOL PARAMETER UNITS CONDITIONS READ TIMING (1) tAR Address Stable Before RD...
Page 653: Timing Waveforms
82C55A Timing Waveforms tRR (3) tIR (13) tHR (14) INPUT tAR (1) tRA (2) CS, A1, A0 D7-D0 tRD (4) tDF (5) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) tWD (11) (10) D7-D0 tAW (7) tWA (8) CS, A1, A0 OUTPUT tWS (12) FIGURE 26.
Page 654 82C55A Timing Waveforms (Continued) tWOB (21) tAOB (22) tWIT INTR (28) tAK (15) tAIT (27) OUTPUT tWB (12) FIGURE 28. MODE 1 (STROBED OUTPUT) DATA FROM CPU TO 82C55A (NOTE) tAOB (22) tWOB (21) INTR (15) (16) (NOTE) tSIB (23) tAD (19) tPS (17) (20)
Page 655 82C55A Timing Waveforms (Continued) A0-A1, A0-A1, tAW (7) tWA (8) tAR (1) tRA (2) tRR (3) DATA tDW (10) tWD (11) (4) tRD tDF (5) DATA VALID HIGH IMPEDANCE tWW (9) FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING AC Test Circuit AC Testing Input, Output Waveforms INPUT OUTPUT...
Page 656 82C55A Die Characteristics DIE DIMENSIONS: GLASSIVATION: 95 x 100 x 19 ±1mils Type: SiO ±1k Å Å Thickness: 8k METALLIZATION: Type: Silicon - Aluminum WORST CASE CURRENT DENSITY: ±1k Å Å Thickness: 11k 0.78 x 10 A/cm Metallization Mask Layout 82C55A PA3 PA4 PA5 PA6...
Page 657 82C55A Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS INDEX 1 2 3 AREA SYMBOL NOTES 0.250 6.35 0.015 0.39 0.125 0.195 3.18 4.95 BASE PLANE 0.014 0.022 0.356 0.558 SEATING 0.030 0.070 0.77 1.77...
Page 658 82C55A Plastic Leaded Chip Carrier Packages (PLCC) N44.65 0.042 (1.07) (JEDEC MS-018AC ISSUE A) 0.042 (1.07) 0.048 (1.22) 0.004 (0.10) 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.056 (1.42) PIN (1) IDENTIFIER 0.025 (0.64) INCHES MILLIMETERS 0.050 (1.27) TP SYM- 0.045 (1.14) NOTES 0.165...
Page 659 82C55A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F40.6 LEAD FINISH MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A) 40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS BASE METAL SYMBOL NOTES 0.225 5.72 0.014 0.026 0.36 0.66 0.014 0.023 0.36 0.58 SECTION A-A C A - B 0.045 0.065...
Page 660 82C55A Ceramic Leadless Chip Carrier Packages (CLCC) J44.A MIL-STD-1835 CQCC1-N44 (C-5) 0.010 44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL NOTES x 45 0.064 0.120 1.63 3.05 6, 7 0.054 0.088 1.37 2.24 0.033 0.039 0.84 0.99 0.022 0.028 0.56 0.71...
Page 661 82C59A CMOS Priority Interrupt Controller March 1997 Features Description • 12.5MHz, 8MHz and 5MHz Versions Available The Intersil 82C59A is a high performance CMOS Priority Interrupt Controller manufactured using an advanced 2µm - 12.5MHz Operation ....82C59A-12 CMOS process.
Page 662 82C59A Pinouts 82C59A (PDIP, CERDIP, SOIC) 82C59A (PLCC, CLCC) TOP VIEW TOP VIEW INTA CAS 0 SP/EN CAS 1 CAS 2 DESCRIPTION D7 - D0 Data Bus (Bidirectional) Read Input Write Input Command Select Address Chip Select CAS 2 - CAS 0 Cascade Lines SP/EN Slave Program Input Enable...
Page 663: Functional Description
82C59A Pin Description SYMBOL NUMBER TYPE DESCRIPTION : The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for decoupling. GROUND CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the 82C59A.
Page 664 82C59A A more desirable method would be one that would allow the The Programmable Interrupt Controller (PlC) functions as an microprocessor to be executing its main program and only overall manager in an Interrupt-Driven system. It accepts stop to service peripheral devices when it is told to do so by requests from the peripheral equipment, determines which the device itself.
Page 665 82C59A Priority Resolver The Cascade Buffer/Comparator This logic block determines the priorities of the bits set in the This function block stores and compares the IDs of all lRR. The highest priority is selected and strobed into the cor- 82C59As used in the system. The associated three I/O pins responding bit of the lSR during the INTA sequence.
Page 666 82C59A ADDRESS BUS (16) CONTROL BUS I/OR I/OW INTA DATA BUS (8) INTA CAS 0 CASCADE 82C59A CAS 1 LINES CAS 2 SP/EN INTERRUPT SLAVE PROGRAM/ REQUESTS ENABLE BUFFER FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE 6. This completes the interrupt cycle. In the AEOI mode, the CONTENT OF SECOND INTERRUPT VECTOR BYTE ISR bit is reset at the end of the second INTA pulse.
Page 667 82C59A Initialization Command Words (lCWs) CONTENT OF THIRD INTERRUPT VECTOR BYTE General Whenever a command is issued with A0 = 0 and D4 = 1, this 80C86, 8OC88, 80C286 Interrupt Response Mode is interpreted as Initialization Command Word 1 (lCW1). lCW1 starts the initialization sequence during which the fol- 80C86/88/286 mode is similar to 8080/85 mode except that lowing automatically occur:...
Page 668 82C59A ICW1 LTIM SNGL 1 = ICW4 needed 0 = No ICW4 needed 1 = Single 0 = Cascade Mode CALL address interval 1 = Interval of 4 0 = Interval of 8 1 = Level triggered mode 0 = Edge triggered mode of Interrupt vector address (MCS-80/85 mode only) ICW2...
Page 669 82C59A The address format is 2 bytes long (A0 - A15). When the AEOI: If AEOI = 1, the automatic end of interrupt mode is routine interval is 4, A0 - A4 are automatically inserted by programmed. the 82C59A, while A5 - A15 are programmed externally. µPM: Microprocessor mode: µPM = 0 sets the 82C59A for When the routine interval is 8, A0 - A5 are automatically...
Page 670: Special Mask Mode
82C59A immediately before returning from the service routine, or if After the initialization sequence, IR0 has the highest priority the AEOI (Automatic End of Interrupt) bit is set, until the trail- and IR7 the lowest. Priorities can be changed, as will be ing edge of the last INTA.
Page 671 82C59A End of Interrupt (EOI) After Rotate (lR4 was serviced, all other priorities rotated correspondingly) The In-Service (IS) bit can be reset either automatically fol- lowing the trailing edge of the last in sequence INTA pulse (when AEOI bit in lCW1 is set) or by a command word that “IS”...
Page 672 82C59A The Special Mask Mode is set by OCW3 where: ESMM = 1, The word enabled onto the data bus during RD is: SMM = 1, and cleared where ESMM = 1, SMM = 0. Poll Command In this mode, the INT output is not used or the microproces- W0 - W2: Binary code of the highest priority level request- sor internal Interrupt Enable ﬂip ﬂop is reset, disabling its ing service.
Page 673 82C59A treats the RD following a “poll write” operation as an INTA. In both the edge and level triggered modes the IR inputs After initialization, the 82C59A is set to lRR. must remain high until after the falling edge of the ﬁrst INTA. If the IR input goes low before this time a DEFAULT lR7 will For reading the lMR, no OCW3 is needed.
Page 674 82C59A This modiﬁcation forces the use of software programming to release the device routine address during bytes 2 and 3 of determine whether the 82C59A is a master or a slave. Bit 3 INTA. (Byte 2 only for 80C86/88/286). in ICW4 programs the buffered mode, and bit 2 in lCW4 The cascade bus lines are normally low and will contain the determines whether it is a master or a slave.
Page 675 82C59A Absolute Maximum Ratings Thermal Information θ θ Supply Voltage ........+8.0V Thermal Resistance (Typical) C/W) C/W)
Page 676 82C59A = +5.0V ±10%, GND = 0V, T AC Electrical Speciﬁcations C to +70 C (C82C59A), T C to +85 C (l82C59A), = -55 C to +125 C (M82C59A) 82C59A-5 82C59A 82C59A-12 TEST SYMBOL PARAMETER UNITS CONDITIONS TIMING REQUIREMENTS (1) TAHRL A0/CS Setup to RD/INTA (2) TRHAX A0/CS Hold after RD/INTA...
Page 677 82C59A AC Test Circuit OUTPUT FROM TEST DEVICE UNDER POINT TEST (NOTE) NOTE: Includes stray and jig capacitance. TEST CONDITION DEFINITION TABLE TEST CONDITION 1.7V 523Ω Open 100pF 1.8kΩ 1.8kΩ 50pF AC Testing Input, Output Waveform INPUT OUTPUT +0.4V 1.5V 1.5V - 0.4V NOTE: AC Testing: All input signals must switch between V...
Page 678 82C59A Timing Waveforms (Continued) RD/INTA TRLRH (18) (19) TRLEL TRHEH TRHAX TAHRL ADDRESS BUS (14) (15) TRLDV TRHDZ DATA BUS (20) TAHDV FIGURE 13. READ/INTA INTA (11) TRHRL (12) TWHWL INTA (13) TCHCL INTA FIGURE 14. OTHER TIMING (16) TJHIH SEE NOTE 3 SEE NOTE 4 TJLJH...
Page 679 82C59A Burn-In Circuits MD82C59A CERDIP INTA CAS 0 CAS 1 SP/EN CAS 2 MR82C59A CLCC RD WR GND A0 INTA NOTES: = 5.5V ±0.5V. 7. R3 = 10kΩ ±5%. 1. V = 4.5V ±10%. 8. R4 = 1.2kΩ ±5%. 2. V 3.
Page 680 82C59A Die Characteristics DIE DIMENSIONS: 143 x 130 x 19 ±1mils (3630 x 3310 x 525µm) METALLIZATION: Type: Si-Al-Cu ± 0.75k Å Å Thickness: Metal 1: 8k ± 1.0k Å Å Metal 2: 12k GLASSIVATION: Type: Nitrox ± 3.0k Å Å...
Page 681 82C59A Priority Interrupt Controller Application Note April 1999 AN109.3 PAGE Introduction ..................1.0 Glossary of Terms for the 82C59A .
Page 682: Application Note
Application Note 109 Introduction Acknowledge pulse (INTA) from the CPU. Using this mode of operation frees the software (service routines) from needing The Intersil 82C59A is a CMOS Priority Interrupt Controller, to send an EOI manually to the 82C59A. designed to relieve the system CPU from the task of polling in a multi-level priority interrupt system.
Page 683 Application Note 109 1.3 Buffered Mode that bit D2 (M/S) of ICW4 be set to indicate if the particular 82C59A is being used as a “master” or “slave” interrupt When using the 82C59A in a large system, it may be controller in the system.
Page 684 Application Note 109 1.6 Fully Nested Mode Communications between the master and slaves occurs via the CAS0 - 2 lines. See Figure 2. By default, the 82C59A operates in the Fully Nested Mode. It will remain in this mode until it is programmed otherwise. In 1.9 Special Fully Nested Mode the Fully Nested Mode, interrupts are ordered by priority The Special Fully Nested Mode (SFNM) is used in a system...
Page 685 Application Note 109 2.0 Initialization Control Words ICW4: Issuance of this ICW is selectable through the IC4 (D0) bit of ICW1. If ICW4 is to be written to the 82C59A, A0 The following section gives a description of the Initialization from the CPU must be high (1) when writing to it.
Page 686 Application Note 109 ICW1 ICW3 (SLAVE DEVICE) LTIM SNGL 1 = ICW4 NEEDED SLAVE ID (NOTE) 0 = NO ICW4 NEEDED 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 1 = SINGLE 0 0 1 1 0 0 1 1 0 = CASCADE MODE 0 0 0 0 1 1 1 1 CALL ADDRESS INTERVAL...
Page 687 Application Note 109 D2 - ADI: Call Address Interval (for 8080/8085 use only). If D0 - IC4: Speciﬁes to the 82C59A whether or not it can using the 82C59A in an 80C86/88 based system, the value expect to receive ICW4. If this device is being used in an of this bit can be either a 0 or 1.
Page 688 Application Note 109 ICW4 (which will be discussed later), or through the state of 00000101b, or 05H. This informs the “slave” as to which the SP/EN pin (pin 16). priority level it holds with the “master”. 82C59A AS A MASTER D7 thru D3: These bits must be set to zeros (0) for proper operation of the device.
Page 689 Application Note 109 used for determining whether the particular 82C59A is a we need only write this control word when we wish to disable “master” or a “slave”. speciﬁc interrupt lines. D2 - M/S: This bit is of signiﬁcance only when the BUF bit is A direct mapping occurs between the bits in this control word set (BUF =1).
Page 690 Application Note 109 D5 - SMM: Special Mask Mode - The SMM bit is used to TABLE 4. ROTATE AND EOI MODES enable or disable the Special Mask Mode. This bit will only affect the 82C59A when the ESMM bit is set to 1. Non-specific EOI command 0: Disable the Special Mask Mode.
Page 691 Application Note 109 4.0 Addressing the 82C59A used. It should be noted that address line AD1 from the 80C88 is not being used in the addressing of this particular There are two factors that must be taken into account when peripheral.
Page 692 Application Note 109 5.0 Programming the 82C59A selection of priority rotation, issuance of EOIs, reading of the ISR and/or IRR etc. These OCWs can be written to the As described earlier, there are two different types of 82C59A at any time during operation of the 82C59A. The command words that are used for controlling 82C59A various command words are identiﬁed by the state of operation;...
Page 693 Application Note 109 5.2 Example 2: Cascaded 82C59As example, only one interrupt can occur. This is generated by the 82C52 UART. Except for the fact that this system is Example 2 illustrates how we can use multiple 82C59As in conﬁgured with a Master-Slave interrupt scheme, it is the Cascade Mode.
Page 694 Application Note 109 6.0 Expansion Past 64 Interrupts system software. Therefore, it is the task of the software to poll the various 82C59As in the system to see if any In some instances, it may be desirable to expand the number interrupts are pending.
Page 695 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 DESCRIPTION PIN CONFIGURATION The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and N PACKAGES capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry.
Page 696 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 BLOCK DIAGRAM (–) – AUTO ZERO LADDER AND COMPARATOR DECODER A GND – D7 (MSB) (11) (12) (13) (14) OUTPUT LATCHES (15) (16) (17) D0 (LSB) (18) D GND 8–BIT CLOCK SHIFT REGISTER...
Page 697: Dc Electrical Characteristics
Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 DC ELECTRICAL CHARACTERISTICS = 5.0V, f = 1MHz, T , unless otherwise specified. ADC0803/4 SYMBOL SYMBOL PARAMETER PARAMETER TEST CONDITIONS TEST CONDITIONS UNIT UNIT ADC0803 relative accuracy error (adjusted) Full-Scale adjusted 0.50 ADC0804 relative accuracy error (unadjusted)
Page 698 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 AC ELECTRICAL CHARACTERISTICS ADC0803/4 SYMBOL SYMBOL PARAMETER PARAMETER FROM FROM TEST CONDITIONS TEST CONDITIONS UNIT UNIT µs Conversion time =1MHz Clock frequency Clock duty cycle CS=0, f =1MHz Free-running conversion rate 13690 conv/s INTR tied to WR...
Page 699 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 Large values of source resistance where an input bypass capacitor Reference Voltage Span Adjust is not used will not cause errors as the input currents settle out prior Note that the Pin 9 (V /2) voltage is either 1/2 the voltage applied to the comparison time.
Page 700 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 differential mode of the converter. Any offset adjustment should be At higher CPU clock frequencies, time can be extended for I/O done prior to full scale adjustment. reads (and/or writes) by inserting wait states (8880) or using clock-extending circuits (6800, 8035).
Page 701 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 decoder. The RD and WR signals are generated by reading from A Digital Thermostat and writing to a dummy address. Circuit Description Digitizing a Transducer Interface Output The schematic of a Digital Thermostat is shown in Figure 11. The A/D digitizes the output of the LM35, a temperature transducer IC Circuit Description with an output of 10mV per C.
Page 702 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Current vs Clock Frequency vs Input Current vs Temperature Clock Capacitor Applied Voltage at V REF/2 10.0 = 1MHz 5.0V CS = H = 25 MAX.
Page 703 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1) 20ns DATA OUTPUT DATA OUTPUT 10pF DATA DATA OUTPUT OUTPUT 10pF TIMING DIAGRAMS (All timing is measured from the 50% voltage points) START CONVERSION W(WR)L ”BUSY”...
Page 704 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 (5V) – TO V 0.1µF OFFSET ADJUST DIGITAL CIRCUITS ANALOG OFFSET TO V (–) CIRCUITS ADJUST Figure 2. Offsetting the Zero Scale and Adjusting the Input Range (Span) NOTE: The V /2 voltage is either 1/2 the V voltage or is that which is forced at Pin 9.
Page 705 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 CLK R 2.7k CLK IN INTR 47µF TO (–) 100µF 56pF A GND D GND Figure 5. Connection for Continuous Conversion CLK R 19 CLK IN 4 19 CLK R P1.0 = 1/1.7 R C P1.1...
Page 706 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 4.7k 1.5k LVDT NE5521 1µF 0.47µF 4.7k IN4148 3.3k FULL (–) SCALE ADJUST Figure 10. Digitizing a Transducer Interface Output August 31, 1994...
Page 707 Philips Semiconductors Linear Products Product specification CMOS 8-bit A/D converters ADC0803/4-1 RBI 5 NE587 HEF4071 RBO 4 RBI 5 NE587 HEF4071 LOWER RAISE 10µF CLK R SCC80C51 CLK IN 56pF INTR LM35 (–) D GND 10 8 A GND 29 P12 20 GND 2N3906 1N4148...
Page 708 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series DESCRIPTION PIN CONFIGURATIONS The DAC08 series of 8-bit monolithic multiplying Digital-to-Analog F, N Packages Converters provide very high-speed performance coupled with low cost and outstanding applications flexibility. COMP Advanced circuit design achieves 70ns settling times with very low REF–...
Page 709 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 16-Pin Hermetic Ceramic Dual In-Line Package (Cerdip) -55 C to +125 C DAC08F 0582B 16-Pin Hermetic Ceramic Dual In-Line Package (Cerdip) -55 C to +125 C DAC08AF 0582B...
Page 710 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series DC ELECTRICAL CHARACTERISTICS Pin 3 must be at least 3V more negative than the potential to which R is returned. V = 15V, I =2.0mA. Output characteristics refer to both and I unless otherwise noted.
Page 711 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series DC ELECTRICAL CHARACTERISTICS (Continued) Pin 3 must be at least 3V more negative than the potential to which R15 is returned. V = +15V, I = 2.0mA, Output characteristics refer to both I and I , unless otherwise noted.
Page 712: Test Circuits
Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series AC ELECTRICAL CHARACTERISTICS DAC08E DAC08H DAC08C DAC08 DAC08A SYMBOL SYMBOL PARAMETER PARAMETER TEST CONDITIONS TEST CONDITIONS UNIT UNIT 1/2LSB, all bits Settling time switched on or off, =25 C Propagation delay Low-to-High...
Page 713 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series TEST CIRCUITS (Continued) = 200Ω DAC-08 OPEN SCOPE 2.0mA 0.1µF SLEWING TIME Figure 3. Reference Current Slew Rate Measurement DAC-08 DIGITAL INPUTS OUTPUT NOTES: (See text for values of C.) Typical values of R = 1k = +2.0V...
Page 714 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series TYPICAL PERFORMANCE CHARACTERISTICS Output Current vs Output Voltage True and Complementary Output Fast Pulsed Reference Operation (Output Voltage Compliance) Operation ALL BITS ON TO T 2.5V = 2mA V–...
Page 715 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Reference AMP Common-Mode Range – V vs Temperature All Bits On Logic Input Current vs Input Voltage to T V– = –15V V– = –5V V+ = +5V = 2mA = 1mA...
Page 716: Typical Application
Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series TYPICAL APPLICATION is 2mA or less, and at least 8V more positive than the negative supply when the reference current is between 2mA and 4mA. This is necessary to avoid saturation of the output transistors, which would OPTIONAL RESISTOR cause serious accuracy degradation.
Page 717 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series SETTLING TIME AND PROPAGATION DELAY + = +15V = 1000Ω = 1000Ω = 5kΩ = 10V = 2mA = 500Ω 50Ω = 5kΩ – = –15V NOTES: = IN6263 or equivalent = IN914 or equivalent = 0.01µF...
Page 718 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series RECOMMENDED FULL-SCALE AND ZERO-SCALE ADJUST DAC-08 = 1MΩ V– = 20kΩ NOTES: = low T.C. 0.1 R to minimize pot. contribution to full-scale drift UNIPOLAR VOLTAGE OUTPUT FOR LOW IMPEDANCE OUTPUT 5kΩ...
Page 719 Philips Semiconductors Linear Products Product specification 8-Bit high-speed multiplying D/A converter DAC08 Series UNIPOLAR VOLTAGE OUTPUT FOR HIGH IMPEDANCE OUTPUT V = 10V 5kΩ 5kΩ = 2mA DAC-08 a. Positive Output = 2mA DAC-08 a. Negative Output BASIC BIPOLAR OUTPUT OPERATION (OFFSET BINARY) V = 10V 10kΩ...
Page 720 A connection to the address bus is necessary to allow the programmer to address the ports. Assuming an I/O address space of 256 ports (the standard for older Intel processors which is still compatible with newer members of the Intel family), we need to be able to decode I/O addresses of just eight bits, since 2 = 256 unique locations.
Page 721 We will work an example showing how to interface the Intel 8253 Programmable Interval Timer (PIT) to an Intel 8088 chip. The timer is a device that we could use to count off the length of a time slice for the kernel of a multitasking operating system. The timer has other uses as well, but we will assume this particular application.
Page 722 has a base address of 80h. That is, we want the CS# pin of the timer to be active (low voltage) only when the given address is 80h, 81h, 82h, or 83h. It should not be active for any other address.
Page 723 Before the hardware connection is complete, we must also connect the other pins of the timer. The data sheet of the 8253 gives the purpose of these pins. Simplest are the data bus pins: D0- D7. These obviously must connect to the corresponding lines of the data bus. The Vcc pin is for power, so it must connect to the power supply of the computer.
Page 724: Programming Devices
Programming a device generally involves writing one or more values to its control register, but may also require writing values to other ports on the device as well. The 8253 timer is fairly representative and has the advantage of also being quite simple. The first consideration for programming virtually any device is to determine the operation required and the meaning of the bits in the control register.
Page 725 The various modes actually determine the shape of the OUT signals for a particular timer. The 8253 PIT can generate various types of square waves by holding the OUT line alternately high and low for given amounts of time. Such output signals can be useful for determining timing for various kinds of applications, such as delays.
Page 726 The low order bit of the control word gives us the ability to specify the initial count value (the frequency divisor) as a 16-bit binary number (0001h-10000h) or as a BCD (binary coded decimal) number in the range of 1-10000. The data sheet also specifies that a value of all zeros written to the counter signifies the largest number in the range of possible count values.
Page 727 References Intel. Microprocessor and Peripheral Handbook. Intel Corporation, 1983. Mazidi, A.M. and J.G. Mazidi. The 80x86 IBM PC and Compatible Computers, Volumes I and II: Assembly Language, Design and Interfacing. Englewood Cliffs, NJ: Prentice Hall, 1995.
Page 728 Interfacing the 80C286-16 with the 80287-10 Application Note March 1997 AN120.1 Introduction An important requirement in many systems is the ability to 80287 with a 1/3 duty cycle to allow the 80287-10 to run at off-load numeric data processing. In an 80C286 system, this it’s full 10MHz capability.
Page 729 Application Note 120 The proper PEACK timing can be achieved using the circuit (3) On the falling edge of the 80C286 CLK at the beginning shown in Figure 1 comprised of a 74AC04, 74AC08, and a of Phase 2 of the T cycle, the low state of PEACK is 74AC112.
Page 730: Hardware Interrupts
Peripheral Devices and I/O Peripheral devices are the means of communication between the CPU and the outside world. As human beings, we are accustomed to the interface between ourselves and the devices. For instance, we know that to operate a keyboard, we press the keys; to operate a mouse, we place a hand over it and move it or press its buttons.
Page 731 CPU considers some interrupt requests to be more important than others. Intel Interrupt Prioritization The implementation of this prioritization is as follows. First, it is important to understand that peripheral devices do not connect directly to the CPU. Instead, an interrupt controller (the 8259A chip) stands between the devices and the processor.
Page 732 Available/Secondary Interrupt Controller Serial Communications Port (COM2) Serial Communications Port (COM1) Parallel Communications Port (LPT1) Standard Floppy Disk Controller lowest Parallel Communications Port (LPT2) The combination of the separate, prioritized, interrupt request lines and the operation of the 8259A controller chip allows the CPU to ignore at least temporarily some relatively unimportant interrupts so that it can process more important ones instead.
Page 733 diagram above, several different types of hardware error conditions can trigger this interrupt request. This line, unlike the IRQ lines, signal a hardware failure of some sort or a request from the 8087 floating point processor and therefore it would be inappropriate to attach a normal peripheral device to the NMI line.
Page 734 Cascaded Interrupt Controllers ("IBM BIOS Technical Reference", 1984, IBM Corp.) Motorola 680x0 Family The Motorola family uses some of the same general concepts that we have seen with the Intel family, but interrupt prioritization and recognition also includes some important differences. The Motorola chips have a status register (SR) that corresponds in many ways to the Intel FLAGS register.
Page 735 (unless a higher-priority device requests an interrupt at this moment). This scheme presents a problem in terms of NMIs, both for Intel and Motorola processors, since it is impossible to set priority high enough to ignore them. For this reason, NMIs are edge- sensitive or edge-triggered.
Page 736 the "ticks" of the clock. The CPU recognizes an edge-sensitive interrupt only at the moment of the transition from low to high voltage. Thus, the detection of this type of interrupt occurs within one clock pulse of the moment it is asserted and does not occur again. This scheme prevents an NMI from interrupting itself.
Page 737 Understanding when the CPU recognizes different sorts of exceptions and interrupts will also help you understand that there are actually very few exceptions that can occur truly simultaneously. For instance, although there are a number of exceptions that the CPU detects when it decodes an instruction, there is only one instruction at a time (ignoring pipelining).
Page 738 1. The CPU saves state (the FLAGS register or SR and the return address) 2. The CPU (Motorola) or interrupt controller (Intel) disables interrupts of the same or lower priority 3. The CPU clears the trace bit of the SR or FLAGS register (on the Motorola processor, SR also contains a "mode"...
Page 739 The second pulse is a request for the 8259A to place the vector number on the data bus to send it to the processor. We can summarize the Intel interrupt acknowledge cycle (a special bus cycle, different from the normal read and write cycles) that occurs as a response to an interrupt request as follows: 1.
Page 740 (vector numbers 25-31). When a hardware interrupt occurs, the MC680x0 also executes an . Unlike the Intel interrupt acknowledge cycle, the Motorola chip will also need to determine which sort of interrupt is occurring and thus how it should obtain the vector number.
Page 741 normal execution state, but this time with the processor executing an interrupt handler. We can define context switch time as the time it takes to perform a state save. Part of the state save occurs before entering the handler, the rest occurs as a result of the first instruction(s) of the service routine itself.
Page 742 I/O. Typically, the mnemonics for these instructions are IN and OUT, as they are for the Intel family of chips. True isolated I/O also requires a dedicated I/O bus, separate from normal data and address buses. Having separate buses for I/O means that bus cycles can occur simultaneously for conventional memory and I/O devices.
Page 743: Memory Mapped I/O
Isolated I/O (from Wakerly) Intel machines incorporate a less expensive form of isolated I/O. They use a control line to select between conventional memory and I/O ports rather than a dedicated I/O bus. The bus connects to a bank of 8-bit I/O ports to which both the device and the CPU have access. The same bus also connects to conventional memory.
Page 744 The conventional memory chips installed in the computer do not include these addresses. Memory-Mapped I/O (from Wakerly) Memory-Mapped I/O on the MC68000 (contrast with Intel) (from Orejel) Advantages of memory mapped I/O: 1. No special opcodes are necessary, making instruction set design simpler (the fewer the opcode bit patterns, the easier it is to avoid ambiguity in these patterns).
Page 745 2. Interfaces (controllers) need less circuitry since they do not have to decode 24-bit addresses (only one byte is needed to designate a unique I/O port). 3. I/O instructions are quicker because they are optimized for a single special purpose. As a rule, the more general an operation must be, the more complex and thus the slower it will 4.
Page 746 Block Diagram of the ACIA (from Motorola MC6850 data sheet) The ACIA has four onboard registers (ports): 1. the Transmit Data Register (TDR), which is a buffer for data that the ACIA must transmit 2. the Receive data register (RDR), which is a buffer for data that the ACIA is receiving 3.
Page 747 Ford, William and William Topp. Assembly Language and Systems Programming for the M68000 Family (Second Ed.). Lexington, MA: D.C. Heath, 1992. Intel. i486 Microprocessor: Hardware Reference Manual. Intel Corporation, 1990. 86/88, 186/188 User's Manual: Programmer's Reference. Intel Corporation, 1985. Intel486™ Microprocessor Family: Programmer's Reference Manual. Intel Corporation, 1992.
Page 748 Dell™ PowerEdge™ Systems MICROPROCESSOR UPGRADE GUIDE www.dell.com...
Page 749 Trademarks used in this text: Dell, the DELL logo, and PowerEdge are trademarks of Dell Computer Corporation; Intel and Pentium are registered trademarks of Intel Corporation. Other trademarks and trade names may be used in this document to refer to either the entities claiming the marks and names or their products.
Page 750 Contents Precautionary Measures ..........1-2 Before You Begin .
Page 752 “Safety Instructions” in your system’s Installation and Troubleshooting Guide. ® ® This document provides procedures for upgrading the Intel Pentium II or III microprocessors with either Intel Pentium II or Pentium III microprocessors in the following Dell PowerEdge systems: • PowerEdge 1300 • PowerEdge 2300 •...
Page 753: Precautionary Measures
The contents of your kit will vary, depending on the PowerEdge system and the number of microprocessors you are installing. Each kit will have one or more new Pentium II or Pentium III microprocessor(s), diskettes containing the Resource Configuration Utility (RCU), BIOS, embedded server management (ESM) firmware, and diagnostics.
Page 754: Before You Begin
NOTICE: Do not attempt to operate a system with one Pentium II microprocessor and one Pentium III microprocessor. Damage to one or both of the microprocessors and/or the system board may occur. NOTICE: All empty microprocessor connectors must be populated with a termi- nator card.
Page 755: Saving Rcu Configuration Settings
After the system completes the boot routine, follow the instructions on the screen. After the message appears on the screen, remove the BIOS diskette from the diskette drive and follow the instructions on the screen to reboot the system. Saving RCU Configuration Settings Use the RCU to save the current system configuration settings by performing the following steps:...
Page 756 Install the upgrade microprocessor. See “Installing the Upgrade Microprocessors” found later in this document. Replace the cooling shroud. See “Removing and Replacing the Cooling Shroud,” found later in this document. If the upgrade kit comes with a new cooling shroud, you must install the new cooling shroud.
Page 757: Installing Upgrade Microprocessors In The Poweredge 2300
Installing Upgrade Microprocessors in the PowerEdge 2300 To upgrade to Pentium II or Pentium III microprocessors in the PowerEdge 2300, perform the following steps. WARNING: The power supplies in this computer system produce high voltages and energy hazards, which can cause bodily harm. Only trained service technicians are authorized to remove the computer cover and access any of the components inside the computer.
Page 758 Record the locations and disconnect all internal cables attached to the sys- tem board. At the left side of the system, locate and remove the three screws that secure the system board and mounting plate to the chassis (see Figure 1-1). mounting screws (3) system board and mounting- plate assembly...
Page 759: Installing Upgrade Microprocessors In The Poweredge 2400
Remove the microprocessor. See “Removing the Microprocessors,” found later in this document. Remove the cooling shroud. See “Removing and Replacing the Cooling Shroud,” found later in this document. Install the upgrade microprocessor. See “Installing the Upgrade Microprocessor,” found later in this document. Replace the cooling shroud.
Page 760 CAUTION: When handling the SEC cartridge and heat sink assembly, take care to avoid sharp edges on the heat sink. NOTICE: See "Precautionary Measures," found earlier in this document for important information to prevent damage to the system from ESD. Remove the cooling shroud.
Page 761: Installing Upgrade Microprocessors In The Poweredge 4300
Install the replacement SEC cartridge and heat sink assembly as follows: Remove the terminator card or old SEC cartridge from the guide bracket assembly. Slide the SEC cartridge into the guide bracket assembly, and firmly seat the assembly until the tabs on the guide bracket assembly snap into place over the ends of the heat sink (see Figure 1-3).
Page 762 If you are upgrading a PowerEdge 4300 with a microprocessor with an operating frequency less than 600 MHz, you do not need to replace the system board mounting tray. Remove the system board mounting tray as follows. WARNING: The power supplies in this computer system produce high voltages and energy hazards, which can cause bodily harm.
Page 763 Replace the guide brackets. See “Removing and Replacing the Guide Brackets,” found later in this document. Install the upgrade microprocessor. See “Installing the Upgrade Microprocessor,” found later in this document. Reassemble and check the system. See “Reassembling and Checking the System,” found later in this document. system board tray tray...
Page 764: Installing Upgrade Microprocessors In The Poweredge 4350
inner card-guide brackets (6) thumbscrew Figure 1-5. Removing the System Board Installing Upgrade Microprocessors in the PowerEdge 4350 To upgrade to Pentium II or Pentium III microprocessors in the PowerEdge 4350, per- form the following steps: Access the system board, which involves the following steps: Disconnecting power and peripheral cables.
Page 765: Removing The Microprocessors
Remove the microprocessors. See “Removing the Microprocessors,” found later in this document. Remove and replace the guide brackets. See “Removing and Replacing the Guide Brackets,” found later in this document. Install the upgrade microprocessor. See “Installing the Upgrade Microprocessor,” found later in this document. Reassemble and check the system.
Page 766: Removing And Replacing The Guide Brackets
release latches (2) thumbscrews (2) heat sink microprocessor Figure 1-6. Removing the Microprocessor Removing and Replacing the Guide Brackets To remove the guide bracket assembly, perform the following steps: Remove any terminator card installed in the guide bracket. Remove any microprocessor assembly installed in the guide bracket. Use a #2 Phillips screwdriver to loosen the four captive nuts that secure the guide bracket assembly to the system board (see Figure 1-7).
Page 767 captive nuts (4) guide bracket assembly threaded posts (4) system board connector Figure 1-7. Removing the Old Guide Bracket Assembly captive nuts (4) guide bracket assembly threaded posts (4) system board connector Figure 1-8. Installing the New Guide Bracket Assembly 1-16 Dell PowerEdge Systems —...
Page 768: Removing And Replacing The Cooling Shroud
Removing and Replacing the Cooling Shroud The plastic cooling shroud inside the system is used to improve airflow over the microprocessors. You may need to remove this shroud to access certain components on the system board. Removing the Cooling Shroud To remove the cooling shroud, perform the following steps.
Page 769: Replacing The Cooling Shroud
thumbscrew retention pins (2) Figure 1-9. Removing the Cooling Shroud Replacing the Cooling Shroud To replace the cooling shroud, perform the following steps: Hook the upper edge of the large opening on the end of the cooling shroud over the top of the cooling fan on the system back panel. Lower the other end of the shroud into place over the microprocessor(s).
Page 770 To install an upgrade microprocessor, perform the following steps: Insert the new microprocessor into the system board connector (see Figure 1-10). Press the microprocessor firmly into its connector until it is fully seated and the latches snap into place. You must use up to 25 lb of force to fully seat the microprocessor. For Pentium III microprocessors, you do not need to change the jumper settings on the system board.
Page 771: Installing A New Cooling Shroud
Installing a New Cooling Shroud If a cooling shroud came with your microprocessor upgrade kit and your system is a PowerEdge 1300 or PowerEdge 2300, you must install the cooling shroud provided in the upgrade kit. To install a cooling shroud, perform the following steps: Carefully position the shroud into place with the square opening over the bulk- head fan and the top of the shroud’s other end resting over the microprocessors, as shown in Figure 1-11.
Page 772 Close the computer panel doors (for PowerEdge 4350 systems only) or replace the covers and front bezel, and reconnect your computer and peripherals to their power sources and turn them on. As the system boots, it detects the presence of the new microprocessor and automatically changes the system configuration information in the System Setup program.
Page 773 1-22 Dell PowerEdge Systems — Microprocessor Upgrade Guide...

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