Chrontel CH7023 Application Notes

AN-96
Chrontel
Application Notes
PCB Layout and Design Considerations for CH7023/CH7024
1.0 Introduction
The CH7023/CH7024 is a device targeting handheld and similar systems which accepts digital input signal,
encodes and transmits data through a 10-bit high speed DAC. The device is able to encode the video signals and
generate synchronization signals for NTSC, PAL interface standards. The device accepts different data formats
including RGB and YCrCb (e.g. RGB565, RGB666, RGB888, ITU656 like YCrCb, etc.).
This application note focuses only on the basic PCB layout and design guidelines for CH7023/CH7024 TV
encoder. Guidelines in component placement, power supply decoupling, grounding, input/output signal
interface are discussed in this document.
The guidelines discussed here are intended to optimize the PCB layout and applications for this product. They
are only for reference. Designers are urged to implement the configurations and evaluate the performance of
the system prior to bringing the design to production.
2.0 Component Placement
Components associated with CH7023/CH7024 should be placed as close as possible to the respective pins.
The following discussion will describe guidelines on how to connect critical pins, component placement, and
layout associated with these pins.
2.1 Power Supply Decoupling
There is only one type of grounding associated with power supply and ground pins. The optimal power supply
decoupling is accomplished by placing a 0.1uF to each of the power supply pins as in . These
Figure 1
capacitors should be connected as close as possible to their respective power and ground pins using short and
wide traces to minimize lead inductance.
2.1.1 Ground Pins
The ground pins of CH7023/CH7024 should be connected to a common ground plane to provide a low
impedance return path for the supply currents. Whenever possible, each of CH7023/CH7024 ground pins
should connect directly to its respective decoupling capacitor ground lead, then connected to the ground plane
through a ground via. Short and wide traces should be used to minimize the lead inductance.
2.1.2 Power Supply Pins
There are four power supply pins, AVDD, AVDD_DAC, AVDD_PLL, and DVDD. See Figure 1 for proper
design of the power-ground pairs. Table 1 shows the power supply and ground pins assignment of
CH7023/CH7024.
206-0000-096 Rev. 1.1, 12/19/2006 1