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XK-1A Hardware Manual
Document Revision 1.0
Publication Date: 2011/03/29
Copyright © 2011 XMOS Limited, All Rights Reserved.

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Summary of Contents for XMOS XK-1A

  • Page 1 XK-1A Hardware Manual Document Revision 1.0 Publication Date: 2011/03/29 Copyright © 2011 XMOS Limited, All Rights Reserved.
  • Page 2 It comprises a single XS1-L1 device, 128KBytes SPI FLASH memory, four LEDs and two press-button switches. Two XMOS Links allow you to link multiple XK-1A boards together in a chain, two I/O expansion areas are provided for connecting additional components to the XK-1A, and an XTAG-2 debug adapter can be connected to debug the XK-1A board with a PC.
  • Page 3 3/15 2 XS1-L1 Device [A] The XK-1A is based on a single XS1-L1 device in a 128TQFP package. The XS1-L1 consists of a single XCore, which comprises an event-driven multi-threaded processor with tightly integrated general purpose I/O pins and 64 KBytes of on-chip RAM. The pins are brought out of the package and connected to the card’s components as...
  • Page 4 The LED pins are active high. 4 Push-Button Switches [D] The XK-1A provides two push-button switches whose states can be sampled at any time by software. The layout of these switches is shown below. The switches are connected to two pins, which are mapped to ports as described in the table on the next page.
  • Page 5 5/15 5 XSYS Connectors [B] The XK-1A includes two XSYS 20-way IDC Headers, which can be used to link to an XTAG-2 debug adapter for debugging programs on the board, or to connect additional XK-1A boards together in a chain.
  • Page 6 TRST_N SENSE The XTAG-2 converts between XSYS and USB 2.0, allowing the XK-1A to be connected to most PCs. On power on, the XS1-L1 boots from the on-board flash memory. The XS1-L1 can then be put into JTAG mode by the PC, which then boots another program.
  • Page 7 XK-1A Hardware Manual 7/15 6 Expansion Areas [E] The I/O pins of the processor are brought out to expansion areas on the top and bottom of the card. These areas have 0.1" pitch through-plated holes and are populated with 0.1" right-angle IDC male connectors. The routing of I/O and power pins in the headers is shown below.
  • Page 8 XK-1A Hardware Manual 8/15 Port Processor P1A0 P1B0 P4A0 P8A0 P4A1 P8A1 P4B0 P8A2 P4B1 P8A3 GPIO_A P4B2 P8A4 P4B3 P8A5 P4A2 P8A6 P4A3 P8A7 XD10 P1C0 XD11 P1D0 XD12 P1E0 XD13 P1F0 XD14 P4C0 P8B0 XD15 P4C1 P8B1 XD16...
  • Page 9 XD65 XLD0_up XD66 XLD0_dn XD67 XLD1_dn Some of the I/O pins on the expansion areas can also be configured as 2-bit XMOS Links. The mapping of XMOS Links to the headers is shown in the table below. XMOS Link Expansion Area...
  • Page 10 400MHz, the I/O ports at 100MHz, by an on-chip phase-locked loop (PLL). 9 Power Connector [H] An XK-1A can be powered from the XTAG-2 debug adapter or an external 5V power supply. Additional boards that have been chained together may be able to be powered by the XTAG-2 (depending on the length of the chain) or from an external 5V power supply.
  • Page 11 XK-1A Hardware Manual 11/15 11 XK-1A Block Diagram The diagram on page shows how the XK-1A components are connected to the XS1-L1. Processor 0 PORT_LED PORT_BUT_1, PORT_BUT_2 GPIO HEADERS A, B PORT_UART_RX PORT_UART_TX XS1-L1 TDOC TDOC TRST_N TRST_N DEBUG DEBUG...
  • Page 12 XK-1A Hardware Manual 12/15 Port Processor P1A0 P1B0 P4A0 P8A0 P16A0 P4A1 P8A1 P16A1 P4B0 P8A2 P16A2 P4B1 P8A3 P16A3 GPIO_A P4B2 P8A4 P16A4 P4B3 P8A5 P16A5 P4A2 P8A6 P16A6 P4A3 P8A7 P16A7 XD10 P1C0 XD11 P1D0 XD12 P1E0 XD13...
  • Page 13 XK-1A Hardware Manual 13/15 12 XK-1A Schematic Document Revision 1.0...
  • Page 14 XK-1A Hardware Manual 14/15 13 XK-1A XN File The XK-1A XN file is a platform specific file, similar to a # define . It defines the type of event-driven processor device on the board, and can be used to map the hardware features on the board to generic port identifiers, simplifying the process of writing...
  • Page 15: Related Documents

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