Quantech MPA-100 Hardware Reference Manual

Rs-232 synchronous adapter

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RS-232 SYNCHRONOUS

INTERFACE CARDS FOR IBM PC/AT AND PS/2

Reference Guide

QUATECH, INC.

662 Wolf Ledges Parkway

Akron, Ohio 44311

MPA-100

ADAPTER

for ISA compatible machines

Hardware

TEL: (330) 434-3154

FAX: (330) 434-1409

FAX: (330) 434-2481

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Page 1 MPA-100 RS-232 SYNCHRONOUS ADAPTER for ISA compatible machines INTERFACE CARDS FOR IBM PC/AT AND PS/2 Hardware Reference Guide QUATECH, INC. TEL: (330) 434-3154 662 Wolf Ledges Parkway FAX: (330) 434-1409 Akron, Ohio 44311 FAX: (330) 434-2481...
Page 3 WARRANTY INFORMATION Quatech Inc. warrants the MPA-100 to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
Page 4 Quatech Inc., MPA-100 Manual...
Page 5: Table Of Contents
Appendix 2. Hardware Installation ..... . Appendix 3. Specifications ......Quatech Inc., MPA-100 Manual...
Page 6 Quatech Inc., MPA-100 Manual...
Page 7 List of Tables and Figures Figure 1. MPA-100 board drawing ......
Page 8 Quatech Inc., MPA-100 Manual...
Page 9: Section 1. Introduction
The Quatech MPA-100 is a single channel, synchronous RS-232 compatible serial communication port for systems utilizing the architecture of the IBM AT personal computer or compatible. The port of the MPA-100 occupies an 8 byte block of I/O address space. The base address of this block may be located anywhere within the available I/O address space in the system.
Page 10: Section 2. Board Description
Section BOARD DESCRIPTION The MPA-100 communications are controlled by the SCC labeled U17. There are eight jumper blocks on the MPA-100 that allow the user to select such options as bus speed, DMA channels, interrupt levels and driver control. External connections are made through a male D-25 connector labeled CN1 for both DTE and DCE configurations.
Page 11: Section 3. Scc General Information
Section SCC GENERAL INFORMATION The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPA-100 provides a single channel for communications, however, to provide full DMA capabilities with complete modem control line support, both channels of the SCC can be utilized.
Page 12 Table 2 describes the write registers for each channel. The MPA-100 has been designed to assure that all back to back access timing requirements of the SCC are met without the need for any software timing control. The standard of adding jmp $+2 between IO port accesses is not required when accessing the MPA-100.
Page 13 These clocks can be programmed in WR11 to come from the RTXC pin, the TRXC pin, the output of the BRG, or the transmit output Quatech Inc., MPA-100 Manual...
Page 14 DPLL. The MPA-100 uses the TRXC pin for its clock-on-transmit and the RTXC pin for its clock-on-receive. Programming of the clocks should be done before enabling the receiver, transmitter, BRG, or DPLL. Table SCC write register description. Command Register, Register Pointer, CRC initialization, resets for...
Page 15 WR12 (least significant byte) and WR13 (most significant byte). The equation relating the baud rate to the time constant is given below while Table 3 shows the time constants associated with a number of popular baud rates when using the standard MPA-100 9.8304 MHz clock. Clock_Frequency Baud_Const = −...
Page 16 WR14. They are local loopback and auto echo. For further information on these subjects or any others involving the SCC contact the manufacturer of the SCC being used for a complete technical manual. Quatech Inc., MPA-100 Manual...
Page 17: Section 4. Jumper Block Configurations
J2, J11, and J12 DTE/DCE Configuration Jumpers The jumper groups J2, J11, and J12 control the DTE/DCE configuration of the MPA-100. The jumper J1 controls important clock characteristics. The jumpers J11 and J12 control the routing of the signals to the DB-25 connector. All three jumper groups must be set exclusively to either DTE fo DCE for correct operation of the MPA=100.
Page 18 By selecting pins 1 & 2, the user has the ability to share interrupts. The MPA-100 will drive the interrupt onto the bus only when an interrupt occurs. Otherwise, the output is high impedance. If pins 2 & 3 of J1 are selected, then interrupts abide by the IBM specification and cannot be shared.
Page 19 J8- DMA CHANNEL ON TRANSMIT SELECTION J8 Selects the DMA channel to be used for DMA on transmit. Three channels (1 - 3) are available on the MPA-100 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be selected.
Page 20: Section 5. Addressing
For example, if the base address is set to 300H, then the MPA-100 will occupy address locations 300H-307H. The base address of the MPA-100 may be set to any of the first 64 Kbytes (0 - FFFFH) of available I/O address space through the settings of dip switches SW1 and Quatech Inc.,...
Page 21 SW2 allows the user to select the lower address signals A7 - A3. The sixth position of SW2 is not used and can be ignored. Figure 2 shows some examples of different base addresses. Figure Address switch selection examples. Base Address = 300H Base Address = 3F8H Quatech Inc., MPA-100 Manual...
Page 22 The first four bytes, Base+0 through Base+3, of address space on the MPA-100 contain the internal registers of the SCC. The next two locations Base+4 and Base+5 contain the communications register and the configuration register. The last two address port locations are reserved for future use.
Page 23: Section 6. Interrupts
External/Status (see manufacturers data sheets for more details). Jumper block J4 can be selected to provide for interrupt sharing on the MPA-100. When using interrupts with the MPA-100, it is required that the applications program have an interrpt service routine (ISR).
Page 24: Section 7. Direct Memory Access
EIA-530 requires that this pin is used as the Data Terminal Ready (DTR) line and would not be available for DMA. After programming the SCC for DMA , The DMA on the MPA-100 should be enabled by setting bit D2 of the configuration register. Next, the DMA on the SCC should be enabled, and finally, the DMA channel should be unmasked.
Page 25 Therefore, bits D0 and D1 of the configuration register should never be cleared at the same time while bits D2 and D3 are both set. This situation may result in damage to the system. Figure Block diagram of DMA on MPA-100. W/REQA DMATRQ DTR/REQA...
Page 26: Section 8. Configuration Register
Section CONFIGURATION REGISTER The MPA-100 is equipped with an on-board register used for configuring the board. This register includes such information as DMA enables and sources, along with interrupt enables and sources. Below is a detailed description of the configuration register. The address of this register is Base+5.
Page 27 When set (logic 1), this bit allows the source for DMA on transmit to come from the DTR/REQA pin of channel A on the SCC. When cleared (logic 0), the source for DMA on transmit comes from the W/REQA pin of channel A of the SCC. Quatech Inc., MPA-100 Manual...
Page 28: Section 9. Communications
Test mode bits pertain only to the DTE versions and can be ignored if using a DCE configured MPA-100. The address of this register is Base+4. Table 16 and the descriptions that follow detail the communications register.
Page 29 TCLK. Since a DCE can only transmit its TCLK, writing to this bit has no effect on a DCE. -RECEIVER ENABLE: This bit should always be programmed to 0. -TRANSMITTER ENABLE: This bit should always be programmed to 0. Quatech Inc., MPA-100 Manual...
Page 30: Section 10. Dte/Dce Configuration Differences
The MPA-100 can beconfigured as either a Data Terminal Equipment (DTE) or a Data Communications Equipment (DCE) configuration. The differences on the MPA-100 between the DTE and the DCE configuration include signal definitions, connector pinout, and clocking options. In order to simplify matters, a section for each configuration summarizes these differences.
Page 31: Dte Configuration
DTE CONFIGURATION The MPA-100 is configured as a DTE by the correct configuration of jumper blocks J2, J11 and J12. See Section 4, Tables 5,6 and 7 (pages 9 and 10) for this configuration information. The control signals the DTE can generate are the Request To Send (RTS) and Data Terminal Ready (DTR).
Page 32: Dce Configuration
The RS-232C standard defines each signal with respect to the DTE. These signals still have the same representation for the DCE. The difference on the MPA-100 is that the names given to each of the signals on the DCE connector are interchanged (by jumper blocks J8 and J9), with the exception of a few control signals.
Page 33 The test mode signals for the DCE configuration are the same for the DCE and DTE configurations. These signals are Local Loopback (LLBK) and Remote Loopback (RLBK) for outputs and Test Mode (TM) forinput. These signals also remain on the same connector pins. Quatech Inc., MPA-100 Manual...
Page 34 DCDA of SCC DTR/REQA pin of SCC DTR/REQB pin of SCC TxCLK TRXCA pin of SCC RxCLK RTXC/TRXCB pin of SCC Bit D5 of Comm. Reg Bit D4 of Comm Reg INTM or Bit D7 of Comm Reg Quatech Inc., MPA-100 Manual...
Page 35: Section 11. External Connections
Section EXTERNAL CONNECTIONS The MPA-100 is designed to meet the RS-232 standard through a D-25 connector. The MPA-100 uses a D-25 short body male connector (labeled CN1) for both the DTE and DCE configurations. Jumper blocks J2, J11, and J12 configure the connector pinout for the desired configuration.
Page 36 Figure MPA-100 DTE Output Connector Configuration N/C 13 25 Test Mode (Output) N/C 12 24 TxCLK (DTE) RxCLK (DTE) 11 23 N/C N/C 10 22 N/C 21 RLBK (Output) 20 DTR DGND 19 N/C LLBK (Output) RxCLK (DCE) 16 N/C...
Page 37 This page intentionlly blank. Quatech Inc., MPA-100 Manual...
Page 38: Appendix 1. Definition Of Interface Signals
CONNECTOR NOTATION: TXCLK (DTE) DIRECTION: To DCE This signal, generated by the DTE, provides the DCE with element timing information pertaining to the data transmitted by the DTE. The DCE can use this information for its received data. Quatech Inc., MPA-100 Manual...
Page 39 CONNECTOR NOTATION: CD DIRECTION: From DCE This signal indicates to the DTE whether the DCE is conditioned to receive data from the communication channel, but does not indicate the relative quality of the data signals being received. Quatech Inc., MPA-100 Manual...
Page 40 Quatech Inc., MPA-100 Manual...
Page 41 DIRECTION: From DCE This signal indicates to the DTE that the DCE is in a test condition. The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE. Quatech Inc., MPA-100 Manual...
Page 42 This page intentionlly blank. Quatech Inc., MPA-100 Manual...
Page 43: Appendix 2. Hardware Installation
Appendix HARDWARE INSTALLATION The following are the steps required for installing the MPA-100. 1. Set addressing, interrupts, DMA and other configuration jumper blocks. 2. Turn system unit off. 3. Remove system cover as instructed in the computer reference guide. 4. Insert adapter into any vacant 16 bit slot following the guidelines for installation.
Page 44 This page intentionlly blank. Quatech Inc., MPA-100 Manual...
Page 45: Appendix 3. Specifications
I/O Address range: 0000H - FFFFH Interrupt levels: fx IRQ 2-7, 10-12, 14-15 DMA levels: DMA Channel 1, 2, and 3 on transmit and receive. Power requirements: (mA) (mA) Supply Voltage (Volts) 1248 1402 Quatech Inc., MPA-100 Manual, 2/92, Rev A...
Page 46 MPA-100 RS-232 SYNCHRONOUS ADAPTER FOR EIA-232-D STANDARD HARDWARE REFERENCE GUIDE Revision C, 2/2/93...