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NAT-AMC-ARRIA10-FMC
FMC C
ARRIER
T
ECHNICAL
N.A.T. Gesellschaft für Netzwerk- und Automatisierungs-Technologie mbH
Konrad-Zuse-Platz 9 | 53227 Bonn, Germany | Phone: +49 228 965 864 - 0
sales@nateurope.com | www.nateurope.com
NAT-AMC-ARRIA10-FMC
B
OARD WITH
D
N.A.T. G
ESIGNED BY
R
EFERENCE
HW R
EVISION
T
R
ECHNICAL
EFERENCE
INTEL ARRIA10 FPGA
H
MB
M
V2.1
ANUAL
2.
X
M
V2.1
ANUAL
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Summary of Contents for N.A.T. NAT-AMC-ARRIA10-FMC
- Page 1 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL NAT-AMC-ARRIA10-FMC FMC C INTEL ARRIA10 FPGA ARRIER OARD WITH N.A.T. G ESIGNED BY V2.1 ECHNICAL EFERENCE ANUAL HW R EVISION N.A.T. Gesellschaft für Netzwerk- und Automatisierungs-Technologie mbH Konrad-Zuse-Platz 9 | 53227 Bonn, Germany | Phone: +49 228 965 864 - 0...
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Page 2: Table Of Contents
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL ABLE OF ONTENTS 1. PREFACE ......................6 1.1. Disclaimer ......................6 1.2. About This Document ..................7 2. INTRODUCTION .................... 8 2.1. Main Features ...................... 9 3. QUICK START....................11 3.1. Unpacking ......................11 3.2. Mechanical Requirements ................11 3.3. - Page 3 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 5.3.5. S2: D ..........................42 EBUG ONNECTOR 5.3.6. S3: M SD C ......................... 42 ICRO 5.3.7. SW1: H ........................43 WITCH 5.3.8. SW2: C ....................43 USTOM ELECT WITCH 5.3.9. SW3: JTAG S ........................44...
- Page 4 5 – PLL C ........................24 IGURE LOCK SSIGNMENT 6 – NAT-AMC-ARRIA10-FMC: F ..............25 IGURE RONT ANEL 7 – NAT-AMC-ARRIA10-FMC – L – T ............27 IGURE OCATION IAGRAM 8 - NAT-AMC-ARRIA10-FMC – L – B ........... 27 IGURE...
- Page 5 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 11 – S1: AMC E ) ..................40 IGURE ONNECTOR TOP VIEW 12 – I FMC M 1 ....................47 IGURE NSTALLING ODULE 13 – I FMC M 2 ....................47 IGURE NSTALLING ODULE 14 – C JTAG C ................
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Page 6: Preface
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL REFACE 1.1. Disclaimer The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.), represents the current status of the product´s development. The documentation is updated on a regular basis. Any changes which might ensue, including those necessitated by updated specifications, are considered in the latest version of this documentation. -
Page 7: About This Document
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 1.2. About This Document This document is intended to give an overview on the NAT-AMC-ARRIA10-FMC’s functional capabilities. Preface General information about this document Introduction Abstract on the NAT-AMC-ARRIA10-FMC’s main functionality and application field Quick Start... -
Page 8: Introduction
ANUAL NTRODUCTION The NAT-AMC-ARRIA10-FMC is a FMC carrier board in AMC form factor. It features an Intel Arria10 SX SoC or GX FPGA, high dense memory interfaces, and an FMC slot, which supports High (HPC) and Low Pin Count (LPC) connectors as defined by VITA 57.1. -
Page 9: Main Features
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 2.1. Main Features Table 1 – Main Features Form Factor • Single-width, mid- or full-size AMC, expandable with one or two FMC(s) • Width: 73.5 mm, Depth: 180.6 mm Processing Resources • Intel/Altera Arria10 SoC SX660/SX570 or FPGA / SoC •... - Page 10 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Environmental • 0 to +55 °C with forced cooling Operating • Humidity: 10% to 90% (non-condensing) Environment • -30 to +85 °C with forced cooling Extended • Humidity: 10% to 90% (non-condensing) Operating Temperature • -40 to +100 °C Storage •...
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Page 11: Quick Start
The installation requires a MicroTCA backplane, a power supply, and cooling devices. Before installing or uninstalling the NAT-AMC-ARRIA10-FMC, read the Installation Guide and the User’s Manual of the NAT-AMC-ARRIA10-FMC and the µTCA system the board will be plugged into. Check all installed boards and modules for steps that you have to take before turning on or off the power. -
Page 12: Voltage Requirements
The NAT-AMC-ARRIA10-FMC supports hot-swapping, which means that the board can be inserted or extracted during normal system operation without affecting other modules. Make sure to follow the procedure exactly to prevent the NAT-AMC-ARRIA10-FMC or the system it is plugged into from damage! -
Page 13: Functional Description
ECHNICAL EFERENCE ANUAL UNCTIONAL ESCRIPTION The NAT-AMC-ARRIA10-FMC can be divided into a number of functional blocks, which are described in the following paragraphs. The following figure gives an overview on the functional blocks. Figure 1 – Block Diagram NAT-AMC-ARRIA10-FMC DDR4... -
Page 14: Fpga Resource Overview
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Figure 2 – FPGA Resource Overview 4 GB SD Card QSPI FPGA Flash DDR4 Boot Boot EPCQ (x4) UART (x4) UART Flash Dedicated I/O Shared I/O EMAC1 EMAC0 FPGA SGMII to SGMII to DDR4 RGMII... -
Page 15: Pcb Version
IP core (Avalon I²C). To offer users a more easy and quick start with the NAT-AMC-ARRIA10-FMC, the board is delivered with a Quartus Prime hardware example project which implements most of the functions that are shown in Figure 2 –... -
Page 16: Ddr4 Ram Settings #1
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 4 – DDR4 RAM Settings #1 - 16 - UNCTIONAL ESCRIPTION... -
Page 17: Ddr4 Ram Settings #2
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 5 – DDR4 RAM Settings #2 - 17 - UNCTIONAL ESCRIPTION... -
Page 18: Ddr4 Ram Settings #3
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 6 DDR4 RAM Settings #3 - 18 - UNCTIONAL ESCRIPTION... -
Page 19: Gpio Pin Assignment
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 4.1.3. GPIO Pin Assignment The tables in this paragraph give an overview of the GPIO Pin Assignments. Pin functions are fixed and cannot be changed by the user. Table 7 – HPS dedicated I/O Pins... -
Page 20: Able 8 - Hps / Fpga Shared I/O Pins Art 1
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 8 – HPS / FPGA shared I/O Pins Part 1 Pin Name Pin Location Function GPIO0_IO0 SD_DATA0 GPIO0_IO1 SD_CMD GPIO0_IO2 SD_CLK GPIO0_IO3 SD_DATA1 GPIO0_IO4 SD_DATA2 GPIO0_IO5 SD_DATA3 GPIO0_IO6 UART_TX (Shared IO Soft UART capable) - Page 21 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 9 – HPS / FPGA shared I/O Pins Part 2 Pin Name Pin Location Function GPIO1_IO2 C Data Line to Peripherals (SDA) GPIO1_IO3 C Clock Line to Peripherals (SCL) Optional I C Request. Drive this signal low in order to get GPIO1_IO6 exclusive access to the multi master FMC I2C management bus.
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Page 22: Jtag
4.2. JTAG The NAT-AMC-ARRIA10-FMC implements an electrical circuit to route different JTAG slaves to a specific JTAG master. Possible JTAG slaves are the Arria10 FPGA and the FMC JTAG port. The setting of SW3-1 determines the JTAG master, which is either the embedded JTAG unit or an external JTAG master (e.g. -
Page 23: Pll And Clocking
EFERENCE ANUAL 4.3. PLL and Clocking The NAT-AMC-ARRIA10-FMC clock distribution network consists of an ADN4604 clock multiplexer and two SiLab5347 PLLs, called ‘System PLL’ and ‘Application PLL’. An overview is given in the following figure. Figure 4 – Clock Distribution... -
Page 24: Fpga Clk Gpio To Clk Mux Assignment
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Figure 5 – PLL Clock Assignment System PLL (I²C: 0x6D) Application PLL (I²C: 0x6C) OUT0 SPLL_OUT 100MHz OUT0 APLL_OUT3 125MHz OUT1 CLKUSR 100MHz OUT1 APLL_OUT2 125MHz HPS_CLK1 OUT2 25MHz OUT2 APLL_OUT1 125MHz FPGA_CLK1 OUT3 REF_CLK_P6-11... -
Page 25: Hardware
Front Panel and LEDs The front plate appearance and the labelling vary depending on the number and variant(s) of installed FMCs. The figure below shows the mid-size version of the NAT-AMC-ARRIA10-FMC carrier board. Figure 6 – NAT-AMC-ARRIA10-FMC: Front Panel Mid-Size... -
Page 26: Amc Port Definition
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 5.2. AMC Port Definition Table 11 – AMC Port Definition Connector Region AMC Port # Signal CLK1/TCLKA Telecom Clock CLK2/TCLKB Telecom Clock Clocks CLK3/TCLKC Telecom Clock CLK4/TCLKD Telecom Clock CLK5/FCLKA Fabric Clock Common Options SATA / SAS... -
Page 27: Connector- And Switch-Location
EFERENCE ANUAL 5.3. Connector- and Switch-Location Figure 7 – NAT-AMC-ARRIA10-FMC – Location Diagram – Top Figure 8 - NAT-AMC-ARRIA10-FMC – Location Diagram – Bottom Assignments from connector labelling to function can be found in the table below. - 27 -... -
Page 28: Table 12 - Connector Labelling And Function
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 12 – Connector Labelling and Function Label Function FMC Connector Pin Header for JTAG Converter Pin Header for Microcontroller Programming Standard AMC-Edge Connector Debug Interface via USB Port MicroSD-Card Slot Hot Swap Switch Custom / Boot Select Switch JTAG Select Switch For standard interfaces, no further explanation is given. -
Page 29: J1: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 5.3.1. J1: FMC Connector Connector J1 interfaces to the FMC mezzanine. Table 13 – J1A: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH DP1_M2C_P AD31 1E, CH5 GXB, HSSI... -
Page 30: J1B: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 14 – J1B: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH CLK_DIR DP9_M2C_P 1G, CH1 GXB, HSSI DP9_M2C_N DP8_M2C_P 1G, CH0 GXB, HSSI DP8_M2C_N DP7_M2C_P 1F, CH5 GXB, HSSI... -
Page 31: J1C: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 15 – J1C: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH DP0_C2M_P AG37 1E, CH4 GXB, HSSI DP0_C2M_N AG36 DP0_M2C_P AE33 1E, CH4 GXB, HSSI DP0_M2C_N AE32 LA06_P... -
Page 32: J1D: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 16 – J1D: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH PG_C2M GBTCLK0_M2C_P AE29 1E, CHT GXB, HSSI GBTCLK0_M2C_N AE28 LA01_P_CC VADJ LA01_N_CC LA05_P VADJ LA05_N LA09_P VADJ... -
Page 33: J1E: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 17 – J1E: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH HA01_P_CC VADJ HA01_N_CC HA05_P VADJ HA05_N HA09_P VADJ HA09_N HA13_P VADJ HA13_N HA16_P VADJ HA16_N HA20_P VADJ... -
Page 34: J1F: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 18 – J1F: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH PG_M2C HA00_P_CC VADJ HA00_N_CC HA04_P VADJ HA04_N HA08_P VADJ HA08_N HA12_P VADJ HA12_N HA15_P VADJ HA15_N HA19_P... -
Page 35: J1G: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 19 – J1G: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH CLK1_M2C_P CLK1_M2C_N LA00_P_CC VADJ LA00_N_CC LA03_P VADJ LA03_N LA08_P VADJ LA08_N LA12_P VADJ LA12_N LA16_P VADJ LA16_N... -
Page 36: J1H: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 20 – J1H: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH VREF_A_M2C PRSNT_M2C_L CLK0_M2C_P CLK0_M2C_N LA02_P VADJ LA02_N LA04_P VADJ LA04_N LA07_P VADJ LA07_N LA11_P VADJ LA11_N LA15_P... -
Page 37: J1I: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 21 – J1I: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH CLK3_BIDIR_P CLK3_BIDIR_P HA03_P VADJ HA03_N HA07_P VADJ HA07_N HA11_P VADJ HA11_N HA14_P VADJ HA14_N HA18_P VADJ HA18_N... -
Page 38: J1J: Fmc Connector
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Table 22 – J1J: FMC Connector FPGA Bank / FMC Pin# FMC Label VCCO FPGA Pin# Transceiver CH VREF_B_M2C CLK2_BIDIR_P CLK2_BIDIR_N HA02_P VADJ HA02_N HA06_P VADJ HA06_N HA10_P VADJ HA10_N HA17_P_CC VADJ HA17_N_CC HA21_P VADJ... -
Page 39: J2: Jtag Converter Pin Header
EFERENCE ANUAL 5.3.2. J2: JTAG Converter Pin Header Pin Header J2 provides access to the JTAG Converter Unit of the NAT-AMC-ARRIA10-FMC. Figure 9 – J2: JTAG Converter Pin Header Table 23 – J2: JTAG Converter Pin Header – Pin Assignment... -
Page 40: S1: Amc Edge Connector
V2.1 ECHNICAL EFERENCE ANUAL 5.3.4. S1: AMC Edge Connector The NAT-AMC-ARRIA10-FMC connects to the backplane via S1. Figure 11 – S1: AMC Edge Connector (top view) Table 25 – S1: AMC Edge Connector – Pin Assignment Pin # Signal Signal... - Page 41 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Pin # Signal Signal Pin # PORT1-Rx_P PORT18-Rx_R_P PORT1-Rx_N PORT18-Rx_R_N AMC_GA2 PORT17-Tx_R_P PWR_IN PORT17-Tx_R_N PORT2-Tx_P PORT17-Rx_R_P PORT2-Tx_N PORT17-Rx_R_N PORT2-Rx_P AMC_TCLKD_P PORT2-Rx_N AMC_TCLKD_N PORT3-Tx_P AMC_TCLKC_P PORT3-Tx_N AMC_TCLKC_N PORT3-Rx_P PORT15-Tx_R_P PORT3-Rx_N PORT15-Tx_R_N AMC_ENABLEn PORT15-Rx_R_P PWR_IN PORT15-Rx_R_N PORT4-Tx_P...
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Page 42: S2: Debug Connector
PORT9-Rx_N AMC_FCLKA_P PORT8_Tx_P AMC_FCKLA_N PORT8-Tx_N /AMC_PS0 PORT8-Rx_P PWR_IN PORT8-Rx_N 5.3.5. S2: Debug Connector S2 features a Micro-USB debug interface on the NAT-AMC-ARRIA10-FMC. 5.3.6. S3: MicroSD Card Slot S3 provides a MicroSD Card slot to the NAT-AMC-ARRIA10-FMC. - 42 - ARDWARE... -
Page 43: Sw1: Hot-Swap-Switch
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 5.3.7. SW1: Hot-Swap-Switch Switch SW1 is used to support hot-swapping of the module. It conforms to PICMG AMC.0. 5.3.8. SW2: Custom / Boot Select Switch SW2-1 and SW2-2 are user-defined, whereas SW2-3 to SW2-6 are used as Boot Select Switch. -
Page 44: Sw3: Jtag Select Switch
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 5.3.9. SW3: JTAG Select Switch SW3 is the JTAG Select Switch. Table 27 – SW3: Switch– Operating Parameters Switch # Use Backplane as FPGA JTAG Master Use Embedded Unit as FPGA JTAG Master SW3-1 Switch off Embedded JTAG Unit... -
Page 45: Board Support Package
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL OARD UPPORT ACKAGE The board support package is a combination of hardware and software logic which is generated by Intel Design Software Quartus Prime Pro 17.0 This tool can be download at the Intel FPGA Download Center. The BSP is production programmed and delivered with the NAT- AMC-ARRIA10-FMC hardware board. - Page 46 NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Connected to HPS EMAC0 and AMC Backplane Port 0 • Connected to HPS EMAC1 and AMC Backplane Port 1 • PIO (Parallel IO) IP • Connected to HA/LA/HB Pins on FMC • Connected to LVDS Trigger Lines on AMC Port 17-20 •...
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Page 47: Fmc Operation
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL FMC O PERATION This chapter gives important information about FMC installation and setup. 7.1. Supported FMCs All FMCs compliant to VITA 57.1 are supported. VADJ and VIO_B_M2C are limited to 1.8V. 7.2. Installing an FMC Module When applying an FMC module, it could be necessary to remove or to untighten the front metal in order for the FMC front to fit into the cutout. -
Page 48: Fmc Eeprom Wizard
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 7.3. FMC EEPROM Wizard Per default the carrier will try to parse the FMC FRU records from the modules EEPROM contents to set the carrier’s power supply and clock direction. In case there is an FMC without records, there are two options: 1. -
Page 49: Configuration And Booting
OOTING 8.1. HPS Boot Sources Available processor boot sources on the NAT-AMC-ARRIA10-FMC are the embedded QSPI flash memory (default) or SD-Card. The boot source can be selected by DIP SW2: Custom / Boot Select Switch. Depending on the peripherals being used by the HPS, it is necessary for the FPGA to be fully or partially configured first. -
Page 50: Figure 14 - Create Indirect
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL Figure 14 – Create Indirect JTAG Configuration File Once this is done, you should open the Quartus Programmer from the “Tools -> Programmer” dialogue. Click on “Auto Detect” to detect the proper FPGA device. Then right click on the FPGA device and choose “Change File”. Select the .jic File and enable the “Program / Configure”... -
Page 51: Creating Hps Bootloader Image
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 8.3. Creating HPS Bootloader Image The HPS bootloader (U-Boot) can be generated using the “bsp-editor”. The BSP editor is part of the SoC-EDS (Embedded Design Suite) Tools chain. To call this utility, open the SoC-EDS- Command shell and type “bsp-editor”. -
Page 52: Specifications And Compliances
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL PECIFICATIONS AND OMPLIANCES 9.1. Internal Reference Documentation none • 9.2. External Reference Documentation Altera Intel Arria10 Device Overview Datasheet, 683332 – 02/2022 • Analog Devices ADN4604 Clock Switch Data Sheet, Rev. A – 03/13 •... -
Page 53: Compliance To Rohs Directive
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 9.4. Compliance to RoHS Directive Directive 2011/65/EU of the European Parliament and of the Council of 8 June 2011 on the "Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment" (RoHS) predicts that all electrical and electronic equipment being put on the European market... -
Page 54: Compliance To Ce Directive
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 9.6. Compliance to CE Directive Compliance to the CE directive is declared. A ‘CE’ sign can be found on the PCB. 9.7. Compliance to REACH The REACH EU regulation Regulation (EC) No 1907/2006) is known to N.A.T. GmbH. N.A.T. did not receive information from their European suppliers of substances of very high concern of the ECHA candidate list. -
Page 55: Abbreviation List
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL 9.8. Abbreviation List Table 28 – Abbreviation List Abbreviation Description Advanced Mezzanine Card Board Support Package Central Processing Unit Configuration via Protocol DDR RAM Double Data Rate RAM EEPROM Electrically Erasable PROM FLASH Non-Volatile Memory... -
Page 56: Document's History
NAT-AMC-ARRIA10-FMC V2.1 ECHNICAL EFERENCE ANUAL ’ OCUMENT ISTORY Table 29 – Document’s History Date Description Author 20.03.2018 Initial Release MM / SE • 11.04.2018 Fixed typos • 19.07.2018 Updated contents to PCB V1.4. Added notes • that PL clocks connected to FPGA bank 2L will not work with PCB smaller V1.4.
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