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NOVA 1220
Technical manual
Data General NOVA 1220 Technical Manual
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Contents
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Table of Contents
Table of Contents
Timing for the Memory Timing Generator
The Nova 1220 Central Processor
Adder and Multiplexer Control Signals During EFA Instructions
Adder Control Signals During ALC Instructions (TS3)
Memory Reference Instruction Decoding Chart
Examine AC1 Timing Diagram
ADDO, 1, SKP Timing Diagram
Timing Diagram for both the ISZ and DSZ
LDA Timing Diagram
STA Timing Diagram
JSR @ 20 Timing Diagram
PI Timing Diagram
Data Channel out Timing
The CPU Key Sequence Timing Diagram
Control Switch Decoding to the Instruction Register
Key, KEYM and Manual Flow Diagrams
Backpanel Connections to the Console through POA
Nova 1220 Power Supply Specifications
Output Signals of the Nova 1220 Power Fail Module
Simplified Schematic of the +5Vdc Series Switching Regulator
Simplified Schematic of the +15Vdc Series Switching Regulator
Simplified Schematic of a Memory Core
Wiring up the Select Logic of 1K and 2K Boards
P3 Interconnections for Nova 1220
P4 Interconnections for NOVA 1220
Recommended Maintenance Tool Kit
The Nova 1220 Diagnostics
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Data General Corporation
Technical Manual
Nova 1220
015-00001 1-02
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