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Hunt Engineering FPGA12 Manual

Camera link area-scan camera interface
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HUNT ENGINEERING
Chestnut Court, Burton Row,
Brent Knoll, Somerset, TA9 4BP, UK
Tel: (+44) (0)1278 760188,
Fax: (+44) (0)1278 760199,
Email: sales@hunteng.co.uk
www.hunteng.co.uk
www.hunt-dsp.com
Camera Link Area-scan Camera Interface using the FPGA12
v1.0 R.Williams 14-02-06
The HERON-FPGA and HERON-IO families are ranges of HERON modules with FPGAs, often
combined with some interface capability. The HERON-FPGA family in particular provides an FPGA
along with a large number of signals routed to general-purpose connectors. These modules are suitable for
connecting to digital cameras, where the control of the camera and image capture can be performed by the
FPGA fitted to the module.
For the development of the FPGA function, HUNT ENGINEERING provides a Hardware Interface
Layer written in VHDL. This layer allows developers to focus on the application-specific parts of the
system. All of the module hardware should be accessed using parts from the library.
Through the Camera Link Area-scan Camera example HUNT ENGINEERING provides a structured
starting point for the development of an area-scan camera interface. The example includes several
components suitable for processing a stream of camera data. It is intended to be a generic tutorial, so does
not address any camera specific issues.
History
Rev 1.0
Adapted from the example for HERON-FPGA9.
HUNT ENGINEERING is a trading style of HUNT ENGINEERING (U.K.) Ltd, Co Reg No 3333633
Directors P.Warnes & N.J.Warnes. Reg'd office 34 & 38 North St, Bridgwater, Somerset TA6 3YD. VAT Reg'd No GB 515 8449 31

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Summary of Contents for Hunt Engineering FPGA12

  • Page 1 Adapted from the example for HERON-FPGA9. HUNT ENGINEERING is a trading style of HUNT ENGINEERING (U.K.) Ltd, Co Reg No 3333633 Directors P.Warnes & N.J.Warnes. Reg’d office 34 & 38 North St, Bridgwater, Somerset TA6 3YD. VAT Reg’d No GB 515 8449 31...
  • Page 2 Link area-scan camera interface example entitled “CamLink_Cam”. For the rest of this document we will discuss the Camera Link area-scan camera example provided for the Virtex-4 FX version of the HERON-FPGA12. Camera Link is a communication interface that was specifically developed by camera and frame-grabber manufacturers for use with vision applications.
  • Page 3 This tutorial assumes that the version of ISE design tool you are using is the same as the version of the camera-link example. There are application notes on the HUNT ENGINEERING CD that describe how to re-use CD example projects with different versions of ISE if this is necessary. In addition, if you are using a different synthesis environment to ISE there is an application note ‘Using VHDL tools...
  • Page 4 The Camera Link Area-scan Camera example provided on the HUNT ENGINEERING CD includes bit-streams that can be loaded directly onto the Virtex-4 FX HERON-FPGA12 module. These bit- streams implement a generic area-scan camera interface, with automatic frame-size and region of interest detection and programmable region of interest for capture, and frame capture control.
  • Page 5 Functional Block Diagram Automatic Region of Camera Link Interest Detection Area-scan Area-scan Signal Conn.A Camera Interface RS-232 Interface Capture Region of Interest HERON Frame Message Interface Control Interface Output Packing Synchronisation 511x32 HERON FIFO CoreGen Write Interface FIFO...
  • Page 6 FPGA design. This is done inside the file ‘top.vhd’. The module expects as inputs one LVDS camera clock and four LVDS camera data lines. For the HERON-FPGA12 Camera Link example, no outputs are driven by the FPGA as the Virtex-4 FX does not support 3.3V LVDS signalling, only 2.5V.
  • Page 7 Signal Voltage Levels The Camera Link standard uses Low Voltage Differential Signalling (LVDS) for the electrical interface layer. The LVDS signalling standard is as the name suggests, differential. Therefore, one LVDS connection will involve a positive signal and a negative signal complement. In order to correctly connect to LVDS a Xilinx FPGA must be used that supports the LVDS standard.
  • Page 8 Camera Speeds The bit-streams supplied by HUNT ENGINEERING have been specified for operation using a Camera pixel clock frequency of 50MHz or less. There are two versions of the bitstream, one built using a Low Frequency de-serializer for pixel clocks up to 24MHz and one built using a High Frequency de-serializer for pixel clocks above 24MHz.
  • Page 9 ‘SerTFG+/SerTFG−’ is provided for communication To the Frame-Grabber (TFG). With the HERON-FPGA12 Camera Link example, the RS-232 functionality is not available as it requires 3.3V LVDS outputs which is not supported by the Virtex-4 FX device.
  • Page 10 HSB Control Registers The following table defines the control registers that can be set by sending messages to the FPGA using HSB. HSB Address Register Function Description Byte (decimal) LSB of pixel start register for Capture Pixel Start 0 Register Region Of Interest (register is 12bits) Top 4 bits of pixel start register for Capture Pixel Start 1 Register...
  • Page 11 HSB Address Register Function Description Byte (decimal) Bit 6 is used to indicate whether the Camera Control Register connected camera provides a Camera Link DVAL signal. Set to 0 if no DVAL signal is provided. Set to 1 if a DVAL signal is provided.
  • Page 12 The following table defines the status registers that can be read from the FPGA using HSB. HSB Address Register Function Description Byte (decimal) Returns the bottom byte of the ‘First-Pixel’ First Pixel 0 Register value generated by the Auto-Region-of- Interest logic. Bits 0 to 3 return the top 4-bits of the ‘First- First Pixel 1 Register Pixel’...
  • Page 13 HSB Address Register Function Description Byte (decimal) Receive Data Register A read from this register returns the next data byte available in the RS-232 receive buffer. A read from this register returns the Receive Status Register number of data bytes in the RS-232 receive buffer.
  • Page 14 This tutorial covers downloading a Camera Link area-scan camera interface into the application FPGA of a HERON-FPGA12, followed by building and running the example DSP program to capture and store an image captured by the camera interface. To run the tutorial, follow this sequence: Select “Getting Started”...
  • Page 15 DSP module in your system. The example defaults to a DSP module in slot 1 and a HERON-FPGA12 in slot 2. Other slot positions may be used but if you do so, you will need to modify the example.c source file and, in the case of the HEPC9, the Server/Loader network file as well.
  • Page 16 The program needs to be run using the HUNT ENGINEERING Server/Loader plug-in. The program will be run by clicking on the Start S/L button. If there is no tick in the ‘Skip FPGA’...
  • Page 17 off), so it will be better at this point to tick the box ‘Skip FPGA’. When the program runs, it will reset the Automatic Region-of-Interest logic and begin to detect the frame size and active area of the image. When this information has been obtained it will then send all of the set-up information required over HSB.
  • Page 18 This part of the tutorial will show you how you can make some very simple modifications to the FPGA program. The example projects for ISE are shipped on the HUNT ENGINEERING CD. Using these projects will allow you to run the complete design flow, from RTL-VHDL source files to the proper bit-stream, ready to download on your HERON-FPGA board.
  • Page 19 Opening the Camera Project In the tree that you have just copied from the CD, open the sub-directory. You should CamLink_Cam see some further sub-directories. holds the common project files, including a modified version of Top.vhd. Common holds the Camera Link example CamLink_Ex Below the directory you should see the following sub-directories.
  • Page 20 Setting up the Configuration Package At the top of the user_ap1.vhd file there are the settings that you can use to affect your design (in this case the camera example). The idea is that settings that are often changed are found here. 1.
  • Page 21 project directory. In the "Pin Report" verify a few pins from the busses, to check that the ucf file has been used. If you see different assignments, STOP HERE, and verify the UCF file selected for the project. You can now download this file on your FPGA board and see how it works. Note that the user_ap level includes a very large counter which divides the main system clock and drives the LED #4.
  • Page 22 The FPGA Design Camera Inputs The first major functional block in the Camera example is the VHDL module CLINK. This module is used to directly interface to the Camera Link interface of the camera that you are using. This module expects as inputs, four 7:1 serialised camera data signals, and a camera clock.
  • Page 23 Automatic Region of Interest Detection Data output by the CLINK component is monitored by an automatic region of interest function. This process counts the number of pixels in a line and number of lines in a frame to create the Pixel-Total and Line-Total values.
  • Page 24 The pixel stream that is processed by the CLINK, ROI and FRAME_CONTROL components is a 32- bit wide data stream. This data stream may contain valid data only in the bottom byte, or only in the bottom two bytes or in all four bytes. For 4x8 mode, only the bottom data byte carries camera data.
  • Page 25 When developing a new FPGA program for the HERON-FPGA12, by making a new component that interfaces to camera data in the same way, you will be able to easily insert that component into the processing chain that currently exists in the area-scan example.
  • Page 26 The component will typically need to register the signals on the connectors in IOB registers inside the FPGA to meet the timing requirements of the camera output interface. It will then need to generate the signals as well as N data bits, where PIXEL_STROBE DVALID END_OF_LINE...
  • Page 27 Adding New Components New components can be added to do you want, and can be made to interface to the camera data in any way you choose. However, if you want to add new components and want to use the pipelined-pixel- stream format, then you must consider the following points.
  • Page 28 3. The camera is operating with a set of control signals different to what is expected by the HERON- FPGA12. Please check the User Manual for the camera type you are using. The example program supplied on the CD has been configured for a typical Camera Link camera. As such, it expects that...