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Cypress Semiconductor CYV15G0404DXB Specification Sheet

Independent clock quad hotlink ii transceiver with reclocker
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Features
■
Quad channel transceiver for 195 to 1500 MBaud serial
signaling rate
❐
Aggregate throughput of up to 12 Gbits/second
■
Second-generation HOTLink
■
Compliant to multiple standards
❐
SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ES-
CON, and Gigabit Ethernet (IEEE802.3z)
❐
10 bit uncoded data or 8B/10B coded data
■
Truly independent channels
❐
Each channel is able to:
• Perform reclocker function
• Operate at a different signaling rate
• Transport a different data format
■
Internal phase-locked loops (PLLs) with no external PLL
components
■
Selectable differential PECL compatible serial inputs per
channel
❐
Internal DC restoration
■
Redundant differential PECL compatible serial outputs per
channel
❐
No external bias resistors required
❐
Signaling rate controlled edge rates
❐
Source matched for 50Ω transmission lines
■
MultiFrame™ Receive Framer provides alignment options
❐
Comma or full K28.5 detect
❐
Single or multibyte Framer for byte alignment
❐
Low latency option
■
Selectable input and output clocking options
10
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CYV15G0404DXB
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Cypress Semiconductor Corporation
Document #: 38-02097 Rev. *B
Independent Clock Quad HOTLink II™
®
technology
Figure 1. HOTLink II™ System Connections
Serial Links
Independent
Serial Links
Channel
Reclocker
Serial Links
Serial Links
Connections
•
198 Champion Court
Transceiver with Reclocker
■
Synchronous LVTTL parallel interface
■
JTAG boundary scan
■
Built In Self Test (BIST) for at-speed link testing
■
Link quality indicator by channel
❐
Analog signal detect
❐
Digital signal detect
■
Low power 3W at 3.3V typical
■
Single 3.3V supply
■
256 ball thermally enhanced BGA
■
0.25μ BiCMOS technology
■
JTAG device ID '0C811069'x

Functional Description

The CYV15G0404DXB Independent Clock Quad HOTLink II™
Transceiver is a point-to-point or point-to-multipoint communica-
tions building block enabling the transfer of data over a variety of
high speed serial links including SMPTE 292, SMPTE 259, and
DVB-ASI video applications. The signaling rate can be anywhere
in the range of 195 to 1500 MBaud for each serial link. Each
channel operates independently with its own reference clock
allowing different rates. Each transmit channel accepts parallel
characters in an input register, encodes each character for
transport, and then converts it to serial data. Each receive
channel accepts serial data and converts it to parallel data,
decodes the data into characters, and presents these characters
to an output register. The received serial data can also be
reclocked and retransmitted through the serial outputs.
illustrates typical connections between independent video
coprocessors and corresponding CYV15G0404DXB chips.
Independent
Channel
CYV15G0404DXB
Reclocker
Cable
,
•
San Jose
CYV15G0404DXB
10
10
10
10
10
10
10
10
CA 95134-1709
•
408-943-2600
Revised December 14, 2007
Figure 1
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Summary of Contents for Cypress Semiconductor CYV15G0404DXB

  • Page 1: Functional Description

    ■ JTAG device ID ‘0C811069’x Functional Description The CYV15G0404DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communica- tions building block enabling the transfer of data over a variety of high speed serial links including SMPTE 292, SMPTE 259, and DVB-ASI video applications.
  • Page 2 (data, command, and BIST) with other HOTLink devices. The transmit (TX) section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel accepts either 8-bit data characters or preencoded 10-bit transmission characters.
  • Page 3 ENCBYPC Character-Rate Clock C PABRSTC Bit-Rate Clock Transmit PLL OED[2..1] Clock Multiplier D ENCBYPD Character-Rate Clock D PABRSTD CYV15G0404DXB RECLCK[A..D] are Internal Reclocker Signals TXLB[A..D] are Internal Serial Loopback Signals = Internal Signal RECLCKA OEA[2..1] TXBIST OUTA1+ OUTA1– OUTA2+ OUTA2–...
  • Page 4 RECLCKA Clock RECLCKB Select Clock RECLCKC Select Clock RECLCKD Select Clock Select RFEN[A..D] FRAMCHAR[A..D] DECMODE[A..D] RXBIST[A..D] RXCKSEL[A..D] DECBYP[A..D] RXRATE[A..D] CYV15G0404DXB = Internal Signal RESET TRST JTAG Boundary TCLK Scan Controller LFIA RXDA[7:0] RXSTA[2:0] ÷2 RXCLKA+ RXCLKA– LFIB RXDB[7:0] RXSTB[2:0] ÷2 RXCLKB+ RXCLKB–...
  • Page 5 Device Configuration and Control Block WREN Device Configura- ADDR[3:0] tion and Control DATA[7:0] Interface Document #: 38-02097 Rev. *B CYV15G0404DXB = Internal Signal RFMODE[A..D][1:0] RFEN[A..D] FRAMCHAR[A..D] DECMODE[A..D] RXBIST[A..D] RXCKSEL[A..D] DECBYP[A..D] RXRATE[A..D] SDASEL[A..D][1:0] RXPLLPD[A..D] TXRATE[A..D] TXCKSEL[A..D] PABRST[A..D] TXBIST[A..D] OE[A..D][2..1] ENCBYP[A..D] GLEN[11..0] FLEN[2..0]...

  • Page 6: Pin Configuration (Top View)

    ADDR DD[1] CTA[1] CLKD– DA[1] ADDR STD[0] STD[2] CLKD+ CLKOA ADDR ADDR STD[1] CLKA+ ERRA DD[0] CLKOD CLKA CLKA– CYV15G0404DXB A2– A2– B1– B1– B2– B2– RCLK LDTD TRST LPEND SELD LPENB ULCB LPENA SCAN TMEN3 RCLK STB[1] CLKOB STB[0]...
  • Page 7 DATA ADDR DA[4] DA[1] CLKD– TA[1] ADDR DA[3] CLKOA CLKD+ STD[2] ADDR ADDR DA[2] ERRA CLKA+ DA[0] CLKA– CLKA CLKOD CYV15G0404DXB D1– D1– C2– C2– C1– C1– ULCC ULCD SELB SELC ULCA RESET TCLK SELC SELA SELD RCLK DC[0] DC[7]...
  • Page 8 LVTTL clock source, connect the clock source to either the true or complement REFCLKx input, and leave the alternate REFCLKx input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs. Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the associated TXCLKx input is selected as the character-rate input clock for the TXDx[7:0] and TXCTx[1:0] inputs.
  • Page 9 (depending on RXRATEx) of the associated REFCLKx± that are delayed in phase to align with the data. This phase difference allows the user to select the optimal clock (REFCLKx± or RXCLK±) for setup or hold timing for their specific system.
  • Page 10 The reclocker feature is optimized to be used for SMPTE video applications. Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to REFCLKx± instead of the received serial data stream. While ULCx is LOW, the LFIx for the associated channel is LOW indicating a link fault.
  • Page 11 Pin Definitions (continued) CYV15G0404DXB Quad HOTLink II Transceiver Name I/O Characteristics LFIA LVTTL Output, LFIB asynchronous LFIC LFID Device Configuration and Control Bus Signals WREN LVTTL input, asynchronous, internal pull up ADDR[3:0] LVTTL input asynchronous, internal pull up DATA[7:0] LVTTL input...
  • Page 12 Power CYV15G0404DXB HOTLink II Operation The CYV15G0404DXB is a highly configurable, independent clocking, quad-channel transceiver designed to support reliable transfer of large quantities of data, using high speed serial links from multiple sources to multiple destinations. This device supports four single byte channels.
  • Page 13 ATM Forum standards for data transport. Many of the special character codes listed in generated CYV15G0404DXB is designed to support two independent (but non-overlapping) special character code tables. This allows the CYV15G0404DXB to operate in mixed environments with other Cypress HOTLink devices using the enhanced Cypress command code set, and the reduced command sets of other non-Cypress devices.
  • Page 14 Each clock multiplier PLL is able to accept a REFCLKx± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0404DXB clock multiplier (TXRATEx) and by the level on the associated SPDSELx input.
  • Page 15 Document #: 38-02097 Rev. *B The local internal loopback (LPENx) allows the serial transmit data outputs to be routed internally back to the clock and data recovery circuit associated with each channel. When configured for local loopback, the associated transmit serial driver outputs are forced to output a differential logic-1.

  • Page 16: Clock/Data Recovery

    CONTROL SAMPLING PERIOD before the PLL locks to the input data stream, after which LFIx should be HIGH. Receive Channel Enabled The CYV15G0404DXB contains four receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface.
  • Page 17 To reduce the impact on external circuits that use the recovered clock, the clock period is not stretched by more than two bit periods in any one clock cycle. When operated with a character rate output clock, the...

  • Page 18: Receive Modes

    Device Reset State When the CYV15G0404DXB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state, and the elasticity buffer pointers are set to a nominal offset.
  • Page 19 COMDETx is present on the associated output bus. When the Cypress or alternate mode framer is enabled and half rate receive port clocking is also enabled, the output clock is not modified when framing is detected, but a single pipeline stage...
  • Page 20 This mode of framing RFMODED[1:0] stretches the recovered clock for one or multiple cycles to align that clock with the recovered data. When RFMODEx[1:0] = 01, the alternate mode Multi-Byte parallel framer is selected. This requires detection of the selected framing character(s) in the received serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters.
  • Page 21 RXCLKx+ or falling edge of RXCLKx–. When RXRATEx = 1 with RXCKSELx = 1 and REFCLKx± is a full rate clock, the RXCLKx± clock outputs are complementary clocks that follow the reference clock operating at half the character rate. Data for the associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
  • Page 22 Signal Description TXRATEA Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to select TXRATEB the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated TXRATEC REFCLKx±...
  • Page 23 MASK (1111b) JTAG Support The CYV15G0404DXB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the REFCLKx±...
  • Page 24 Each 3-Level select inputs reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11 respectively. JTAG ID The JTAG device ID for the CYV15G0404DXB is ‘0C811069’x Receive Character Status Bits RXSTx[2:0] Priority Normal Status Normal character received.
  • Page 25 Command Data or Command Data End-of-BIST State Yes, RXSTx = BIST_LAST_GOOD (010) No, RXSTx = BIST_ERROR (110) CYV15G0404DXB Receive BIST Detected LOW RX PLL Out of Lock RXSTx = RXSTx = BIST_DATA_COMPARE (000) Page 25 of 44 [+] Feedback [+] Feedback...

  • Page 26: Maximum Ratings

    Supply Voltage to Ground Potential...–0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State... –0.5V to V Output Current into LVTTL Outputs (LOW) ... 60 mA DC Input Voltage ... –0.5V to V CYV15G0404DXB DC Electrical Characteristics Parameter Description LVTTL-compatible Outputs Output HIGH Voltage...
  • Page 27 CYV15G0404DXB DC Electrical Characteristics Parameter Description Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2± Output HIGH Voltage Referenced) Output LOW Voltage Referenced) Output Differential Voltage ODIF |(OUT+) − (OUT−)| Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±...
  • Page 28 21. The ratio of rise time to falling time must not vary by greater than 2:1. 22. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
  • Page 29 Notes 26. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t time of the upstream device.
  • Page 30 REFCLKx jitter tolerance / Phase noise limits REFJ Transmit PLLx lock to REFCLKx± TXLOCK CYV15G0404DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range Receive PLL lock to input data stream (cold start) RXLOCK Receive PLL lock to input data stream...
  • Page 31 TXDx[7:0], TXCTx[1:0], Note 33. When REFCLKx± is configured for half rate operation (TXRATE = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using both the rising and falling edges of REFCLKx. Transmit Interface...
  • Page 32 Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver Receive Interface Read Timing REFCLKx Selected REFH full rate RXCLKx± REFCLKx RXDx[7:0], RXSTx[2:0], [36] TXERRx RXCLKx Notes 34. The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx±.
  • Page 33 Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver Receive Interface Read Timing Recovered Clock selected RXRATEx = 1 RXCLKx+ RXCLKx- RXDx[7:0], RXSTx[2:0] Note 37. When operated with a half rate REFCLKx±, the setup and hold specifications for data relative to RXCLKx are relative to both rising and falling edges of the...
  • Page 34 LVTTL IN PD TMEN3 LVTTL IN PD POWER POWER POWER POWER POWER POWER POWER POWER RXDC[6] LVTTL OUT CYV15G0404DXB Ball Signal Name Signal Type RCLKENA LVTTL IN PD RXSTB[1] LVTTL OUT TXCLKOB LVTTL OUT RXSTB[0] LVTTL OUT TXDC[7] LVTTL IN...
  • Page 35 POWER RXDA[7] LVTTL OUT RXDA[3] LVTTL OUT RXDA[0] LVTTL OUT RXSTA[0] LVTTL OUT TXDD[5] LVTTL IN TXDD[7] LVTTL IN CYV15G0404DXB Ball Signal Name Signal Type TXDB[6] LVTTL IN RXDC[4] LVTTL OUT RXDC[5] LVTTL OUT LFID LVTTL OUT RXCLKD– LVTTL OUT...
  • Page 36 The encoding defined by the transmission code ensures that sufficient transitions are present in the serial bit stream to make clock recovery possible at the receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information.
  • Page 37 Table 12 Character Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 010101 0101 D21.0 D10.2 CYV15G0404DXB Table 12 shows naming notations and Data or Q Hex Value 43210 00000 00001 00010 00101 11110 11111 shows an example of this behavior.
  • Page 38 D28.1 001 11100 010001 1011 D29.1 001 11101 100001 1011 D30.1 001 11110 010100 1011 D31.1 001 11111 CYV15G0404DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001...
  • Page 39 D28.3 011 11100 010001 0101 D29.3 011 11101 100001 0101 D30.3 011 11110 010100 0101 D31.3 011 11111 CYV15G0404DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0011 011000 1100 011101 0011 100010 1100 101101 0011 010010 1100 110001 1100...
  • Page 40 D28.5 101 11100 010001 1101 D29.5 101 11101 100001 1101 D30.5 101 11110 010100 1101 D31.5 101 11111 CYV15G0404DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1010 011000 1010 011101 1010 100010 1010 101101 1010 010010 1010 110001 1010...
  • Page 41 D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYV15G0404DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0001 011000 1110 011101 0001 100010 1110 101101 0001 010010 1110 110001 1110...
  • Page 42 C0.7 (CE0) 111 00000 C1.7 (CE1) 111 00001 C2.7 (CE2) 111 00010 C4.7 (CE4) 111 00100 CYV15G0404DXB [38, 39] Current RD− Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011...

  • Page 43: Ordering Information

    Ordering Information Speed Ordering Code Standard CYV15G0404DXB-BGC Standard CYV15G0404DXB-BGI Package Diagram 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 Document #: 38-02097 Rev. *B Package Name Package Type BL256 256-Ball Thermally Enhanced Ball Grid Array BL256...
  • Page 44 Document History Page Document Title: CYV15G0404DXB Independent Clock Quad HOTLink II™ Transceiver with Reclocker Document Number: 38-02097 ISSUE REV. ECN NO. DATE 231494 See ECN 384307 See ECN 1845306 See ECN © Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product.

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