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J543 TARGET188EB
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CONTROL SYSTEMS
TARGET188EB
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Summary of Contents for Arcom TARGET188EB

  • Page 1 Whilst Arcom’s sales team is always available to assist you in making your decision, the final choice of boards or systems is solely and wholly the responsibility of the buyer. Arcom’s entire liability in respect of the boards or systems is as set out in Arcom’s standard terms and conditions of sale.
  • Page 2: Table Of Contents

    The STEbus and the TARGET188EB ........
  • Page 3: Preface

    The Manual This manual details the operation and features of Arcom’s TARGET188EB boards. It has been designed as both a guide to getting started with the TARGET188EB Development Kit and a reference for the hardware features of the board. Name Conventions Throughout this document an asterisk ‘*’...
  • Page 4: Packaging

    Arcom’s STEbus Technical Construction File. Packaging Please ensure that should a board need to be returned to Arcom, it is adequately packed. Use an anti-static bag for the board and use a box not bag to physically protect the board. Retain the original packing if possible.
  • Page 5: Section 1. Introduction

    PC/104 Master only, 256K SRAM This manual covers all variants. The TARGET188EB is shipped with a software monitor blown into a 128K Flash EPROM to allow simple exercising of the board and downloading application code. The Development Kit contains an additional 128K Flash EPROM with the ‘remote’ target portion of Arcom’s SourceVIEW development software blown into it.
  • Page 6: Section 2. Getting Started

    3. Plug PL1 of the SVIF1 into PL2 (software development/download port) on the TARGET188EB. The body of the SVIF1 should lie over the TARGET188EB. 4. Align the TARGET188EB into the STEbus rack until it mates with one of the backplane connectors.
  • Page 7: Section 3. Links And Options

    J543 TARGET188EB 2192-10296-000-000 Section 3. Links and Options Default Link Positions LK16 LK17 B LK14 A LK18 LK10 ROM 0 ROM 1 LK11 LK12 B LK15 A LK13 Note: A ‘+’ next to a link position indicates the default shipping position.
  • Page 8 2192-10296-000-000 J543 TARGET188EB LK6. INT1 Source Selection Function PC/104 IRQ4 STEbus ATNRQ1* LK7. SRAM battery back-up from PL4 Function +Omit STEbus used - VSTBY from PL1 STEbus not used - VSTBY from PL4 pin 1 LK8. ROM1 write enable Function...
  • Page 9 J543 TARGET188EB 2192-10296-000-000 ROM Fitting Guide 28 pin ROM 32 pin ROM 32 pin ROMs should take up the entire socket and should be fitted in the orientation shown in the ‘Default Link Position’ diagram. 28 pin ROMs should be fitted to only a portion of the socket, as shown above.
  • Page 10: User Configuration Record

    2192-10296-000-000 J543 TARGET188EB User Configuration Record LK16 LK17 B LK14 A LK18 LK10 ROM 0 ROM 1 LK11 LK12 B LK15 A LK13 Page 10 CONTROL SYSTEMS...
  • Page 11: Section 4. Using The Target188Eb

    Section 4. Using the TARGET188EB Programmable Memory and I/O Map The TARGET188EB has a very flexible scheme for locating its on-board memory, peripherals and expansion busses in its memory and I/O maps. The 188EB processor has eight outputs called ‘general chip selects’, GCS0 to GCS7. These outputs may be programmed so that they become active over a range of memory or I/O addresses and can be used to activate devices connected to the 188EB.
  • Page 12: Memory Map After Power-Up/Reset

    2192-10296-000-000 J543 TARGET188EB Memory Map FFFFFh 16KB Monitor (UCS) after initialisation FC000h Flash ROM0 (UCS) E0000h Flash ROM1 (UCS) [optional] C0000h Max. ROM1 space (UCS) STEbus or PC/104 80000h 7FFFFh PC/104 or STEbus (GCS4-7) 40000 3FFFFh STEbus or PC/104 Alternative 256K RAM (-H version) (LCS)
  • Page 13: On-Board Control Registers

    A0 and A1 are high. User Links and LEDS The TARGET188EB has two user links and two user LEDs and a link that determines whether the monitor software or application code is run on power-up or reset. These links and LEDs are...
  • Page 14: Interrupt Assignments

    Port P2 bit 7 D3 (green) Port P2 bit 6 The C library routines supplied with the TARGET188EB fully support the configuration of and access to these peripherals. Interrupt Assignments Interrupts from STEbus, PC/104 and on-board peripherals are routed to the 188EB INT4-0 lines via links for ease of configuration.
  • Page 15: Stebus Support

    5µA. Watchdog The TARGET188EB has a watchdog time-out facility fixed at 1200ms. If no strobe is received by the watchdog circuit for 1200ms then a CPU reset is generated. LK14 selects the watchdog strobe source. A link in position A (factory default) selects BCLK as the watchdog source; i.e.
  • Page 16 See the SourceView manual supplied with the Development Kit for more details. Arcom can supply a range of other tools for source level development and debugging as well as real time operating systems and development tools. Please contact Arcom for details.
  • Page 17: Section 5. Troubleshooting

    J543 TARGET188EB 2192-10296-000-000 Section 5. Troubleshooting Problem Suggestions • No sign-on screen on terminal • Check power-on board - red surface mount LED should be lit. when running with SVIF1 • Check baud rate, stop bits and parity of terminal.
  • Page 18: Appendix A. Specification

    1 x 85230 SCC RS232 serial communications ports (120KBaud max.) with RX, TX, CTS, RTS, DSR, DTR, DCD and RI Arcom SVIF debug/development port Watchdog timer fixed at 1200ms generates CPU reset (link selectable) 3 counter/timers. Each counter can generate an interrupt on a...
  • Page 19: Appendix B. Connections

    J543 TARGET188EB 2192-10296-000-000 Appendix B. Connections PL1. STEbus Connector Standard 64way a&c row DIN41612 right angle PCB mount plug. Pin-out in accordance with IEEE1000 specification. ADRSTB* DATACK* DATSTB* TFRERR* ATNRQ0* SYSRST* ATNRQ2* ATNRQ1* ATNRQ3* STECLK +VSTBY -12V +12V PL4. External Power Connector Phoenix MCV series two part combicon screw terminal connector.
  • Page 20 FGND FGND Note: During development of the Target188EB it has been found that some manufacturers 50- way IDC connectors foul the PC/104 boards (even with the strain relief removed) when used for the I/O connections. The following connectors have been used with no problems on these boards: Harting - part no.
  • Page 21 J543 TARGET188EB 2192-10296-000-000 PL7 . PC/104 Connectors One 64 way non-stackthrough 0.1” grid socket connectors. Pinout and physical arrangement in accordance with PC/104 specification version 2.3. RESET ENDXFR* IOCHRDY AEN (GND) SMEMW* SMEMR* IOW* IOR* pull-up pull-up pull-up SYSCLK IRQ7...
  • Page 22 2192-10296-000-000 J543 TARGET188EB PL3. Push-button Reset 2 pin Dubox header RST_IN SVIF1 Development Interface Module, PL2 10-way IDC ribbon cable header for use with CAB-SVIF1 in development system. Channel A TX Channel A RX Channel A RTS Channel A CTS...
  • Page 23: Appendix C. Reference

    STEbus master and slave boards may be placed in any slot in the STEbus backplane. The TARGET188EB can act only as an STEbus master. It may not be used in multi-master systems as it does not have an arbiter necessary to arbitrate between multiple masters.
  • Page 24: Stebus And Pc/104 Interaction On The Target188Eb

    At power-up the PC/104 bus is the default bus. All accesses to addresses not covered by one of the 188EB chip select ranges (see Section 4. Using the TARGET188EB) is directed out onto the PC/104 bus. Four of the 188EB chip select lines are left free for application software to program (GCS7 to GCS4).
  • Page 25: Appendix D. Bibliography

    J543 TARGET188EB 2192-10296-000-000 Appendix D. Bibliography Intel188EB Embedded Microprocessor Data Sheet Intel Order No.: 272433-000 Intel188EB Embedded Microprocessor User’s Manual Intel Order No.: 270830-003 These may be ordered from these Intel literature centres: tel: 1-800-548-4725 U.S. and Canada tel: 708-296-9333 U.S.
  • Page 26 2192-10296-000-000 J543 TARGET188EB Page 26 CONTROL SYSTEMS...
  • Page 34 2192-10296-000-000 J543 TARGET188EB Page 34 CONTROL SYSTEMS...

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