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Summary of Contents for BitFlow Axion-CL
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The Axion-CL Hardware Reference Manual BitFlow, Inc. 400 West Cummings Park, Suite 5050 Woburn, MA 01801 Tel: 781-932-2900 Sales: sales@bitflow.com Support: support@bitflow.com Web: www.bitflow.com Revision A.3...
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BitFlow, Inc. BitFlow, Inc. makes no implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document, nor does it make a commit- ment to update the information contained in.
Conventions AXN-P-2 Bitfield definitions AXN-P-3 Example Bitfield Definition AXN-P-3 Bitfield Definition Explanation. AXN-P-3 1 - General Description and Architecture The Axion-CL family AXN-1-1 Camera Link AXN-1-1 Virtual vs. Hardware AXN-1-1 The Virtual Frame Grabber (VFG) AXN-1-2 Axion Configuration Spaces AXN-1-2...
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Table of Contents Triggering the StreamSync Acquisition Engine AXN-2-9 Comparing the StreamSync Acquisition Engine to Other BitFlow products AXN-2-10 AE_CON AXN-2-11 AE_STATUS AXN-2-13 AE_STREAM_SEL AXN-2-15 V_WIN_DIM AXN-2-17 Z_WIN_CON AXN-2-19 Z_WIN_DIM AXN-2-23 Z_WIN_DIM_EXT AXN-2-25 Y_INT_DEC AXN-2-27 Y_WIN_CON AXN-2-29 Y_WIN_DIM AXN-2-33 Y_WIN_DIM_EXT AXN-2-35...
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List of System Probe Counting Modes AXN-10-4 System Probe Examples AXN-10-5 Example - Clocks per Line AXN-10-5 Example - Camera Frame Rate AXN-10-5 SP_EVENTS AXN-10-7 SP_CON AXN-10-10 SP_STAT AXN-10-13 SP_LIMIT AXN-10-15 11 - Axion Camera Link Registers Introduction AXN-11-1 CL_IOBUF_CTL AXN-11-2 CL_CHAN_CONFIG AXN-11-4 BitFlow, Inc.
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CON202 AXN-12-28 CON356 AXN-12-30 CON357 AXN-12-32 13 - Specifications Introduction AXN-13-1 PCI Express Compatibility AXN-13-3 Maximum Pixels Per Line AXN-13-4 Maximum Lines Per Frame AXN-13-5 Axion Power Requirements AXN-13-6 14 - Mechanical Introduction AXN-14-1 The Axion-CL Connectors AXN-14-9 BitFlow, Inc.
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Camera Status LEDS AXN-14-14 Button AXN-14-15 The Auxiliary Power Connector AXN-14-16 The BitBox Box Connector AXN-14-17 I/O Connector Pinout for the Axion-1xE, Axion-2xE and Axion-4xB AXN-14-18 I/O Connector Pinout for the Axion-1xB AXN-14-20 I/O Connector Pinout for the Axion-2xB AXN-14-21 BitFlow, Inc.
Second, it is a reference manual describing in detail the functionality of all of the board’s registers. P.1.1 Support Services BitFlow, Inc. provides both sales and technical support for the Axion family of prod- ucts. P.1.2 Technical Support Our web site is www.bitflow.com.
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Purpose The Axion-CL P.1.4 Conventions Table P-1 shows the conventions that are used for numerical notation in this manual. Table P-1 Base Abbreviations Base Designator Example Binary 1010b Decimal None 4223 Hexidecimal 12fah Table P-2 shows the numerical abbreviations that are used in this manual.
Bitfield definitions P.2 Bitfield definitions P.2.1 Example Bitfield Definition is what each bitfield definition looks like: BITFIELD R/W, CON0[7..0], Axion-CL Bitfield discussion. P.2.2 Bitfield Definition Explanation. The definitions is broken into three sections (see Table P-3). Table P-3 Bitfield Sections.
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This bitfield is functional only the Alta family. Cyton-CXP This bitfield is functional only on the Cyton-CXP family Axion-CL This bitfield is functional only on the Axion-CL family Aon-CXP This bitfield is functional on the Aon-CXP family Claxon-CXP This bitfield is functional on the Axion-CXP family AXN-P-4 BitFlow, Inc.
Chapter 1 1.1 The Axion-CL family The purpose of this chapter is to explain, at a block diagram level, how the Axion-CL works. Currently there are five main models in the Axion-CL family: AXN-PC2-1xE, support for one Base, Medium, Full or 80-bit camera...
1.1.4 Axion Configuration Spaces The Axion-CL model supports up to four VFGs. Each VFG appears to operating sys- tem and your software as a separate device. The block diagrams for the different models are shown in the following section.
General Description 1.2 General Description The Axion-CL is a x4 PCI Express Gen 2 board. It can work in any PCI Express slot that it can fit it. Usually this means an x4, x8 or x16 slot. However, some mother boards have x1 slots with x4 connectors.
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General Description The Axion-CL Physical Layer Physical Layer Camera Link Control Routing Physical Layer Acq. Acq. Physical Layer Control Control Logic Logic Power Virtual Virtual Connector Frame Frame Grabber Grabber PCI Express Bus Figure 1-2 The Axion-2xE Block Diagram AXN-1-4 BitFlow, Inc.
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General Description and Architecture General Description Camera Link Physical Control Layer Routing Power Acq. Control Logic Virtual Connector Frame Grabber PCI Express Bus Figure 1-3 The Axion-1xB Block Diagram Version A.3 BitFlow, Inc. AXN-1-5...
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General Description The Axion-CL Physical Layer Camera Link Control Routing Physical Layer Acq. Acq. Control Control Power Logic Logic Virtual Virtual Connector Frame Frame Grabber Grabber PCI Express Bus Figure 1-4 The Axion-2xB Block Diagram AXN-1-6 BitFlow, Inc. Version A.3...
This can be used to send and receive control data to/from the camera. The serial link is always synchronous. The camera does not send data without being requested from the host. Version A.3 BitFlow, Inc. AXN-1-7...
Axion-CL. 1.2.4 Axion I/O system The Axion-CL has a sophisticated I/O system, which is extremely flexible. The system take in many inputs, routes them to a number of internal signals which can be further manipulate, then routes the results to a wide rand of outputs.
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General Description 1.2.7 The Volume Of Interest Acquisition Engine The Axion-CL introduces the concept of Volume of Interest (VOI) as part of its Stream- Sync Acquisition Engine. This has been designed from the ground up to satisfy the needs of real world machine vision application. The VOI provide robust and flexible...
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The Axion-CL 1.3 Firmware Unlike many of BitFlow’s previous models of frame grabbers, the Axion family does not swap firmware on the fly (this is similar to the Cyton). The Axion is shipped with firmware that supports the latest Camera Link Specification and has been tested with all known cameras at the time of the release.
Axion Camera Configuration Files 1.4 Axion Camera Configuration Files The Axion is the second member of BitFlow’s Gen 2 family. These frame grabber all use an XML based camera configuration file. This differs from previous models of Bit- Flow’s frame grabbers that have all used a binary proprietary file format (which mean they could only be edited using BitFlow’s tools).
The Axion Models The Axion-CL 1.5 The Axion Models There are five models of the Axion-CL. Table 1-1 illustrates the capabilities of each model. Table 1-1 The Axion Models Capability AXN-PC2- AXN-PC2- AXN-PC2- AXN-PC2- AXN-PC2- Number of Base CL cameras supported...
The StreamSync system is a start- from-scratch complete redesign of the acquisition and DMA parts of a frame grabber. BitFlow used its years of experience in this area to design a next generation, super efficient capture system.
The StreamSync Acquisition Engine World The Axion-CL 2.2 The StreamSync Acquisition Engine World We are used to the concept that images have an X and a Y dimension. The Acquisition Engine expands on this concept by adding two further dimension Z and V. The Z dimension controls a sequence of frames or “Volume”...
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Start Of Frame (SOF) packet (or FVAL from a CL camera) is sent from the camera, or it can be opened by a trigger (all SOF packets are ignored Version A.3 BitFlow, Inc. AXN-2-3...
The StreamSync Acquisition Engine World The Axion-CL until the trigger condition is met) or it can just be opened immediately, as soon the Acquisition Engine level is inside the X window (i.e. the stat above). Table 2-1 enumer- ates all of these conditions..
Figure 2-3 Acquisition Engine ROI Similarly there is a Z_OFFS register which if non-zero can cause the board to discard a certain number of frames before starting an acquisition of a sequence. This concept is illustrated in Figure 2-4. Version A.3 BitFlow, Inc. AXN-2-5...
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The StreamSync Acquisition Engine World The Axion-CL V Window Z_OFFS Z_SIZE Z Window Y Window X Window Camera Frames Figure 2-4 Z_OFFS Illustration AXN-2-6 BitFlow, Inc. Version A.3...
V Window (hypervolume). Figure 2-5 Show the relationship between the interrupts and the acquisition Windows. Note: The labels in italics in Figure 2-5 are are the actual interrupt names that can be used with the BitFlow SDK function calls. Z_SIZE BFIntTypeZStart...
Please refer to Figure 2-2 for more information on how a trigger can be used to change the state of the Acquisition Engine. Version A.3 BitFlow, Inc. AXN-2-9...
While the Acquisition Engine might seem very complex, it is actually quite simple to use and has considerably more power than previous acquisition engines used on all previous BitFlow frame grabbers. From a software point of view, the BitFlow API hides the differences between the traditional acquisition systems and the newer Acquisition Engine.
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AE_CON The Axion-CL AE_RUN_LEVEL R/W, AE_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This is the main control for starting/aborting acquisition. Writing this register changes the current run level. Reading this register returns the current run level command (not the current status). The abort run levels exit acquisition on a clean boundary. V exits on a volume boundary, Z on a frame boundary, Y on a line boundary, X on a 128-byte data boundary.
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AE_STATUS The Axion-CL AE_STATE RO, AE_STATUS[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- This register indicates the current run level of the acquisition engine. The following table shows the meanings of each state. AE_STATE Meaning 0 (000b) Idle - System is idle...
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Currently only the values 0 to 3 are supported. Generally this register should be programmed to correspond to the VFG number that is being used to access the acquisition engine. For example, for VFG1 set this register to 1. USE_ R/W, AE_STREAM_SEL[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- SYNTHETIC_ ton-CXP FRAME Use the Synthetic Frame generator instead of the camera.
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The Axion-CL V_SIZE R/W, V_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- This register defines size of the V window, that is, the number of volumes to acquire. A value of 0XFFFF means infinite. When set to infinite, the acquisition engine can be stopped by writing AE_RUN_LEVEL.
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Z_WIN_CON The Axion-CL Z_CLOSE_TRIG_ R/W, Z_WIN_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- FUNC This register determines which trigger change (if any) will end the Z window. Z_CLOSE_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger 2 (0010b)
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The StreamSync Acquisition Engine Z_WIN_CON Z_OPEN_TRIG_ R/W, Z_WIN_CON[15..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- FUNC ton-CXP This register determines which trigger change (if any) will start Z window. Z_OPEN_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger...
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Z_WIN_CON The Axion-CL Z_SYNC R/W, Z_WIN_CON[27..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This field enforces the data-synchronization of streaming video to the acquisition engine for each individual frame in the z window. The following table shows explains this field. Z_SYNC Meaning No synchronization.
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Z_WIN_DIM The Axion-CL Z_SIZE R/W, Z_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Number of frames (Y windows) to acquire per sequence (Z windows). The acquisition of frames will only start after Z_OFFS frames have been skipped after the Z window is opened.
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Z_WIN_DIM_EXT The Axion-CL Z_SIZE_MSB R/W, Z_WIN_DIM_EXT[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Z_SIZE register by 8 more bits. Z_OFFS_MSB R/W, Z_WIN_DIM_EXT[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Z_OFFS register by 8 more bits. AXN-2-26 BitFlow, Inc. Version A.3...
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Y_INT_DEC The Axion-CL Y_INT_DEC_ R/W, Y_INT_DEC[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- COUNT When Y interrupt decimate mode is enable, the register determines the decimation amount. In other words, Y_INT_DEC_COUNT interrupts must occur before the board emits a real interrupt. Y_INT_DEC_RST R/W, Y_INT_DEC[29..28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy-...
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Y_WIN_CON The Axion-CL Y_CLOSE_TRIG_ R/W, Y_WIN_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- FUNC This register determines which trigger change (if any) will end the Y window. Y_CLOSE_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger 2 (0010b)
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(starts the frame) lines are acquired until either the trigger goes low, or Y_SIZE lines have been acquired (i.e. the maximum frame size has been reached). Y_OPEN_TRIG_ R/W, Y_WIN_CON[15..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- FUNC ton-CXP This register determines which trigger change (if any) will start Y window.
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Y window, then starts the setup of the X window. Y_SYNC R/W, Y_WIN_CON[27..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This field enforces the data-synchronization of streaming video to the acquisition engine for each individual line in the y window. The following table explains this field.
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Y_WIN_DIM The Axion-CL Y_SIZE R/W, Y_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Number of lines per frame (Y window) to acquire. This number is only acquired after the Y window is opened and after Y_OFFS lines have been skipped. Y_OFFS R/W, Y_WIN_DIM[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy-...
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Y_WIN_DIM_EXT The Axion-CL Y_SIZE_MSB R/W, Y_WIN_DIM_EXT[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Y_SIZE register by 8 more bits. Y_OFFS_MSB R/W,Y_WIN_DIM_EXT[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Y_OFFS register by 8 more bits. AXN-2-36 BitFlow, Inc. Version A.3...
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X_WIN_DIM The Axion-CL X_SIZE R/W, X_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Number of 16-byte words to acquired per line (X window). This number is only acquired after the X window is opened and after X_OFFS words have been skipped. X_OFFS R/W, X_WIN_DIM[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy-...
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X_WIN_DIM_EXT The Axion-CL X_SIZE_MSB R/W, X_WIN_DIM_EXT[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the X_SIZE register by 8 more bits. X_OFFS_MSB R/W,X_WIN_DIM_EXT[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the X_OFFS register by 8 more bits. X_SHIFT R/W,X_WIN_DIM_EXT[24..18], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP,...
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V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT Reserved Reserved Reserved Reserved V_ACQ_COUNT_CLR_MODE V_ACQ_COUNT_CLR_MODE V_ACQ_COUNT_UPD_MODE V_ACQ_COUNT_UPD_MODE Note: The V_ACQUIRED register is not currently implemented Version A.3 BitFlow, Inc. AXN-2-41...
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V_ACQUIRED The Axion-CL V_ACQ_COUNT R/W, V_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of volumes (frame sequence) acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register V_ACQ_COUNT_CLEAR_MODE.
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Z_ACQUIRED The Axion-CL Z_ACQ_COUNT R/W, Z_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of frames acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register Z_ ACQ_COUNT_CLEAR_MODE.
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Y_ACQUIRED The Axion-CL Y_ACQ_COUNT R/W, Y_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of lines acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register Y_ ACQ_COUNT_CLEAR_MODE.
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X_ACQUIRED The Axion-CL X_ACQ_COUNT R/W, X_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of 16-byte words acquired since the last reset of this regis- ter. The behavior of this register when it reaches it maximum value depends on the register X_ACQ_COUNT_CLEAR_MODE.
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The StreamSync Acquisition Engine CON490 INT_ANY RO, CON490[7], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP T is at least on active interrupt on the board. ENINT_ALL R/W, CON490[8], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Set to 1 to enable board interrupts. Version A.3 BitFlow, Inc.
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The StreamSync Acquisition Engine SF_DIM SF_HEIGHT R/W, SF_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP The height (in lines) of the Synthetic Frame (internally generated synthetic image). SF_WIDTH R/W, SF_DIM[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The width of the Synthetic frame. Units are 16 byte chunks.
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The StreamSync Acquisition Engine SF_CON SF_RUN_LEVEL R/W, SF_CON[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP The register controls the Synthetic Frame generator. SF_RUN_LEVEL Meaning/Command Idle Abort Reserved SF_STATE RO, SF_CON[3..2], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This register can be used to check the current state of the Synthetic Frame generator.
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SF_CON The Axion-CL SF_Y_GAP R/W, SF_CON[23..20], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The number of lines between frames. SF_Z_GAP R/W, SF_CON[27..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The number of frames between volumes. SF_INC_X R/W, SF_CON[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP The amount to increment the grey scale output value every pixel.
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IMAGE_STAMP_CTRL The Axion-CL IS_ALL_LINES R/W, IMAGE_STAMP_CTRL[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Set this bit to 1 to have image stamping on every line in the frame. If it is 0, then just the first line in the frame will be stamped.
BitFlow frame grabbers. The StreamSync system is a start-from-scratch complete redesign of the acquisition and DMA parts of a frame grabber. BitFlow used its years of experience in this area to design a next generation, super efficient capture system.
The Buffer Manager Details The Axion-CL 3.2 The Buffer Manager Details The Buffer Manager interacts with a remote, software managed, set of Scatter Gather DMA lists. A single Scatter Gather DMA list is called a QTab. A QTab is made of indi- vidual DMA instructions (descriptors) called Quads.
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CON485 Register The Axion-CL FIRST_QUAD_ R/W, CON28[31..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP PTR_LO This is the low word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. AXN-3-4 BitFlow, Inc. Version A.3...
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CON486 Register The Axion-CL FIRST_QUAD_ R/W, CON29[31..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP PTR_HI This is the high word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. AXN-3-6 BitFlow, Inc. Version A.3...
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BUF_MGR_CON The Axion-CL BM_RUN_LEVEL R/W, BUF_MGR_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This is the main control for starting/stopping the Buffer Manager. BM_RUN_LEVEL Meaning 0 (0000b) Idle - The Buffer Manager is not moving data 1 (0001b) Run - The Buffer Manger will start to move data...
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BUF_MGR_TIMEOUT The Axion-CL QUAD_ R/W, BUF_MGR_TIMEOUT[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- COMPLETE_ FXP, Cyton-CXP TIMEOUT The maximum amount of time to wait for a Quad completion. Units are 4 nanosec- onds. Writable only when BM_STATE is Idle. DISABLE_ R/W, BUF_MGR_TIMEOUT[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP,...
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BOARD_CONFIG The Axion-CL RO, BOARD_CONFIG[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP The current value of the on board switch SW1. CPLD_MODE RO, BOARD_CONFIG[7..4], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP The current value of switch S3. This switch controls the firmware bank that the FPGA boots from.
PACKETS_SENT_STATUS The Axion-CL NUM_PACKETS_ RO, PACKETS_SENT_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- SENT on-FXP, Cyton-CXP The register indicates the number of PCIe packets that the Buffer Manager has sent across the PCIe bus. This register rolls over to 0 at 0xffff. NUM_PACKETS_ RO, PACKETS_SENT_STATUS[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Clax-...
QUADS_USED_STATUS The Axion-CL NUM_QUADS_ RO, QUADS_USED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- USED FXP, Cyton-CXP This register indicates the number of Quads that have been “consumed” by the Buffer Manager. This register rolls over to 0 at 0xffff. AXN-3-16 BitFlow, Inc. Version A.3...
QTABS_USED_STATUS The Axion-CL NUM_QTABS_ RO, QTABS_USED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- USED FXP, Cyton-CXP This register indicates the number of QTabs that have been “consumed” by the Buffer Manager. This register rolls over to 0 at 0xffff. AXN-3-18 BitFlow, Inc. Version A.3...
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PKT_STAT The Axion-CL PKT_STATE RO, PKT_STAT[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Current state of the DMA engine. PKT_STATE Meaning 0 (00b) PKT_SYNC - Synchronizing DMA descriptors with video 1 (01b) PKT_HDR - Generating PCIe header 2 (10b)~ PKT_DAT - Placing data in PCIe packet...
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The StreamSync Buffer Manager PKT_STAT PKT_FLUSH_ R/W, PKT_STAT[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ENABLE DMA tries to send as large as packets as possible for efficiency. Data is collected in a FIFO until certain size rules are met. However, sometimes no more data will be com- ing (end of frame).
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The StreamSync Buffer Manager QUADS_LOADED_STATUS NUM_QUADS_ RO, QUADS_LOADED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- LOADED on-FXP, Cyton-CXP This register indicates the number of Quads that have been loaded by the Buffer Manager. This register will roll over to 0 at 0xffff. Version A.3 BitFlow, Inc.
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The StreamSync Buffer Manager QTABS_LOADED_STATUS NUM_QTABS_ RO, QTABS_LOADED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- LOADED on-FXP, Cyton-CXP This register indicates the number of QTabs that have been loaded by the Buffer Man- ager. This register will roll over to 0 at 0xffff.
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The StreamSync Buffer Manager BUF_MGR_STATUS BM_STATE RO, BUF_MGR_STATUS[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Returns the current state of the Buffer Manager. BM_STATE Meaning 0 (0000b) Idle - The buffer manager is not current active 1 (0001b) Active - The buffer manager is currently DMAing...
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BUF_MGR_STATUS The Axion-CL SIZE_ERROR_ RO, BUF_MGR_STATUS[23], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Quad size is > 4K. CPL_ERROR RO, BUF_MGR_STATUS[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Error code received as a result of fetching a Quad. Check CPL_STATUS. QUAD_NUM_ RO, BUF_MGR_STATUS[29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP,...
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PKT_CON The Axion-CL MAX_ RO, PKT_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP PAYLOAD_USER This is the maximum sized PCIe packet that will be generated by the Buffer Manager. Writes to this register of values higher than MAX_PAYLOAD_PCIE will be ignored. The coding is shown in the following table.
This section covers the Timing Sequencer (TS) which is available on the Aon, Axion, Claxon and Cyton. The TS is a sophisticated programmable pulse generator. The TS takes the place of the NTG on previous models of BitFlow frame grabbers. The TS improves on the NTG in the following ways: Driven by a “nice”...
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Introduction The Axion-CL Building Pulses The TS was designed to support a wide range of pulse lengths. At the same time, the TS was design to be able to create pulses of very accurate duration. The solution to these two opposing problems is to build up a pulse of a desired length via multiple sub-pulses, each sub-pulse programmed with a different granularity.
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This would be done by setting the Immediate Jump trigger to the End of Frame signal, and the TS_IDX_JUMP to the location of the first pulse that is waiting for the Start of Frame. Version A.3 BitFlow, Inc. AXN-4-3...
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Timing Sequencer TS_CONTROL TS_RUN_LEVEL R/W, TS_CONTROL[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP These bits control the operation of the TS. These bits are used to start and stop the sequencer. They can also be used to program the table to jump to a new section.
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TS_CONTROL The Axion-CL TS_IMMDT_ R/W, TS_CONTROL[8..11], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- JUMP_SEL ton-CXP These bits select the source of the Immediate Jump function. TS_IMMDT_ Meaning JUMP_SEL 0 (0000b) Selected trigger (VGFx_TRIG_SEL) 1 (0001b) Selected encoder A (VFGx_ENCA_SEL) 2 (0010b) Selected encoder B (VFGx_ENCB_SEL)
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Timing Sequencer TS_CONTROL TS_IMMDT_ R/W, TS_CONTROL[12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- JUMP_EN Set this bit to 1 to enable Immediate Jump function. TS_IDX_JUMP R/W, TS_CONTROL[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This is the entry that the table will start from when the TS_RUN_LEVEL register is set to Run.
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TS_CONTROL The Axion-CL TS_TRIG_SEL_0 R/W, TS_CONTROL[31..28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP These bits select the source of the TS trigger 0. TS_TRIG_ Meaning SEL_0 0 (0000b) Selected trigger (VGFx_TRIG_SEL) 1 (0001b) Selected encoder A (VFGx_ENCA_SEL) 2 (0010b) Selected encoder B (VFGx_ENCB_SEL)
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TS_TABLE_CONTROL The Axion-CL TS_IDX_ACCESS R/W, TS_TABLE_CONTROL[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP Indirect access to the TS table. Set this bitfield to the index value that you wish to modify. Access is done through via TS_TABLE_ENTRY register. AXN-4-10 BitFlow, Inc.
R/W, TS_TABLE_ENTRY[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Index of next pulse. Only relevant if TS_TERMINATE = 0. TS_RESOLUTION R/W, TS_TABLE_ENTRY[11..10], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP The time units of this pulse. The length of this pulse is set in the register TS_COUNT.
Timing Sequencer TS_TABLE_ENTRY TS_TRIG_SEL_ R/W, TS_TABLE_ENTRY[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP If this pulse is triggered, this bit sets which trigger will be used. TS_TRIG_SEL_SEL Meaning The trigger selected by TS_TRIG_SEL_0 The trigger selected by TS_TRIG_SEL_1 TS_COUNT R/W, TS_TABLE_ENTRY[26..17], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP The length of this pulse.
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TS_TABLE_ENTRY The Axion-CL TS_END_OF_ R/W, TS_TABLE_ENTRY[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, SEQUENCE Cyton-CXP If this bit is set to 1 and TS_RUN_LEVEL is set to Jump, the TS will jump to the index set in the TS_INDX_JUMP bitfield after the current pulse is output. This bit allows for syn- chronous switching between one section of the table and another section.
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ATS_CONTROL The Axion-CL ATS_RUN_LEVEL R/W, ATS_CONTROL[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP These bits control the operation of the ATS. These bits are used to start and stop the sequencer. They can also be used to program the table to jump to a new section.
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14 (1110b) Reserved 15 (1111b) Reserved Note: * FVAL and LVAL triggers are only support on the Axion models ATS_IMMDT_ R/W, ATS_CONTROL[12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- JUMP_COND ton-CXP This controls the polarity of the Immediate Jump function. ATS_IMMDT_JUMP_ Meaning...
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ATS_CONTROL The Axion-CL ATS_IMMDT_ R/W, ATS_CONTROL[12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- JUMP_EN ton-CXP Set this bit to 1 to enable Immediate Jump function. ATS_IDX_JUMP R/W, ATS_CONTROL[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This is the entry that the table will start from when the ATS_RUN_LEVEL register is set to Run.
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ATS_TABLE_CONTROL The Axion-CL ATS_IDX_ R/W, ATS_TABLE_CONTROL[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- ACCESS FXP, Cyton-CXP Indirect access to the TS table. Set this bitfield to the index value that you wish to modify. Access is done through via TS_TABLE_ENTRY register. AXN-4-20 BitFlow, Inc.
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ATS_TABLE_ENTRY The Axion-CL ATS_NEXT R/W, ATS_TABLE_ENTRY[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Index of next pulse. Only follow if ATS_TERMINATE = 0. ATS_ R/W, ATS_TABLE_ENTRY[11..10], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- RESOLUTION FXP, Cyton-CXP The time units of this pulse. The length of this pulse is set in the register ATS_COUNT.
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Timing Sequencer ATS_TABLE_ENTRY ATS_TRIG_SEL_ R/W, ATS_TABLE_ENTRY[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP If this pulse is triggered, this bit sets which trigger will be used. ATS_TRIG_SEL_SEL Meaning The trigger selected by ATS_TRIG_SEL_0 The trigger selected by ATS_TRIG_SEL_1 ATS_COUNT R/W, ATS_TABLE_ENTRY[26..17], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP The length of this pulse.
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ATS_TABLE_ENTRY The Axion-CL ATS_END_OF_ R/W, ATS_TABLE_ENTRY[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, SEQUENCE Cyton-CXP If this bit is set to 1 and ATS_RUN_LEVEL is set to Jump, the ATS will jump to the index set in the ATS_INDX_JUMP bitfield after the current pulse is output. This bit allows for synchronous switching between one section of the table and another section.
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RD_XXX bit. 5.1.2 I/O Between Virtual Frame Grabbers Because BitFlow’s frame grabber can acquire from more than one camera, it has always been a contention between the desire to let each camera be independent, for example, each with its own trigger, and for them to be synchronized, i.e. all cameras using one trigger.
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Introduction The Axion-CL What this means is that one of the sources, the master VFG’s trigger can be the trigger for all of the VFGs. Thus whatever signal is triggering VFG0, can also trigger all the other VFGs on the board. Of course, each VFG can choose to use the master VFG’s trigger, or choose amongst its own sources.
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Selector Internal Signal B For Internal Signal Internal Internal Circuit M Circuit N External Selector for Output X External Selector for Output Y External Signal X External Signal Y Figure 5-1 Conceptual I/O System Routing Version A.3 BitFlow, Inc. AXN-5-3...
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Note: The signals BOX_IN_XXX are available via an external I/O Box, the BitFlow BitBox, which can be mounted on an external rail system. Contact BitFlow for more information on the BitBox. Note: Each VFG has a copy of the circuit shown in Figure 5-2. This is why the outputs do not specify the VFG number (e.g.
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Figure 5-4 shows the details of the encoder handler block that is part of Figure 5-3. The Filter is used to remove unwanted noise on the incoming signal. The filter is pro- grammable and it will “swallow” a pulse shorter than the programmed size. Version A.3 BitFlow, Inc. AXN-5-5...
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The Aon, Axion, Claxon and Cyton I/O System Internal Signals SEL_ENCDIV SEL_ENCDIV_INPUT TRG_DLY_TRIG_SEL Encoder VFGx_ENCDIV_SEL Divider Multiplier VFGx_TRIG_SEL VFG0_ENCDIV_SEL SCAN_STEP_TRIG SEL_ENCQ Quad Enc Out VFGx_ENCA_SEL Qaudrature Encoder VFGx_ENCQ_SEL Scan Step Out VFGx_ENCB_SEL Decoder VFG0_ENCQ_SEL Figure 5-4 Encoder Handler Version A.3 BitFlow, Inc. AXN-5-7...
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Output Signal Selection The Axion-CL 5.5 Output Signal Selection There are four dynamic output signals for each VFG: CC1, CC2, CC3 and CC4. These dynamic signals can be driven by a variety of sources as shown in Figure 5-5. VFGx_TRIG_SEL...
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Note: The signals VFGx_CC1 to VFGx_CC3 can also be routed to the BitBox, which is an externally mountable I/O Box. VFGx_CC1 VFGx_CXP_TRIG VFGx CXP Uplink VFGx_CC2 VFGx_CC2_TTL VFGx_CC3 VFGx_CC3_TTL Main I/O Connector VFGx_CC4 VFGx_CC4_TTL VFGx_CC3_DIF Figure 5-6 Output Signal Routing Version A.3 BitFlow, Inc. AXN-5-9...
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The Axion-CL 5.7 BitBox Output Signal Routing The BitFlow BitBox has 3 banks of 12 outputs. One bank is TTL, one bank is differen- tial and one bank is a mix of Optocoupled and Open Collector outputs. Each of the 36 outputs can be set to a static output level, or controlled by a dynamic source (waveform).
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The I/O System Registers Introduction The I/O System Registers Chapter 6 6.1 Introduction The registers documented in this section are used to control the I/O system on the Aon, Axion, Claxon and Cyton. Version A.3 BitFlow, Inc. AXN-6-1...
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The I/O System Registers CON60 RD_BOX_IN_ RO, CON60[11..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP TTL_X These bits reflect the real-time state of the 12 TTL inputs on the BitBox. RD_BOX_IN_ RO, CON60[23..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP DIF_X These bits reflect the real-time state of the 12 differential inputs on the BitBox.
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The I/O System Registers CON61 RD_BOX_IN_ RO, CON61[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OPTO_X These bits reflect the real-time state of the eight Opto-Isolated inputs on the BitBox. RD_BOX_IN_ RO, CON61[11..8], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP 24V_X These bits reflect the real-time state of the four 24V inputs on the BitBox.
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The I/O System Registers CON62 RD_TRIG_TTL RO, CON62[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of the VFG’s TTL trigger input. RD_TRIG_DIF RO, CON62[1], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of the VFG’s differential trigger input.
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CON62 The Axion-CL RD_ENCB_DIF RO, CON62[10], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of the VFG’s differential encoder B input. RD_ENCB_VFG0 RO, CON62[11], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of VFG0’s selected encoder B signal.
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The I/O System Registers CON62 RD_ENCA_ RO, CON62[30], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED The bit reflects the real-time status of the VFG’s selected encoder A input. RD_TRIG_ RO, CON62[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED The bit reflects the real-time status of the VFG’s selected trigger input.
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The I/O System Registers CON63 SEL_TRIG R/W, CON63[5..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Selects the VFG’s trigger source. SEL_TRIG Source 0 (000000b) Forced low 1 (000001b) Forced high 2 (000010b) This VFG’s differential trigger VFGx_TRIGGER+/- 3 (000011b) This VFG’s TTL trigger VFGx_TRIGGER_TTL...
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40 to 51 BOX_IN_DIF_0 to BOX_IN_DIF_11 52 to 59 BOX_IN_OPTO_0 to BOX_IN_OPTO_7 61 to 63 BOX_IN_24V_0 to BOX_IN_24V_3 SEL_ENCB R/W, CON63[17..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Selects the source of encoder B. SEL_ENCB Source 0 (000000b) Forced low 1 (000001b)
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The I/O System Registers CON63 SEL_CC1 R/W, CON63[21..18], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Selects the source of CC1. SEL_CC1 Source 0 (0000b) Forced low 1 (0001b) Forced high 2 (0010b) CT0 (from TS) 3 (0011b) CT1 (from TS) 4 (0100b)
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14 (1110b) VFGx_ENCQ_SEL 15 (111b) CT0 (from ATS) SEL_LED R/W, CON63[31..28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Selects the source of the VFG’s green LED. The LED receives a 1/2 second pulse every time the selected event occurs. SEL_LED Source 0 (0000b)
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The I/O System Registers CON63 SEL_LED Source 12 (1100b) VFG0_NTG or VFG0_TS 13 (1101b) AQSTAT[1] 14 (1110b) Overstep, OVS 15 (1111b) Reserved Version A.3 BitFlow, Inc. AXN-6-15...
14 (1110b) VFGx_ENCQ_SEL 15 (111b) CT0 (from ATS) TRIGPOL R/W, CON64[13], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Selects the edge of the trigger signal that corresponds to its assertion. TRIGPOL Meaning Trigger asserted on rising edge Trigger asserted on falling edge...
The I/O System Registers CON64 RD_CC1 RO, CON64[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Returns the current state of the CC1 output. RD_CC1 Meaning Output is low Output is high RD_CC2 RO, CON64[17], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Returns the current state of the CC2 output.
The Axion-CL LED_RED R/W, CON64[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Setting this bit to 1 turns the red LED on. Setting this bit to 1 on any VFG turns the LED on. This bit must be set to 0 on all VFGs in order to turn this LED off.
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The Axion-CL TRIG_FILTER RO, TRIG_OPTS[17..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The trigger circuit includes a programmable noise filter. The value of this register con- trols the size of the noise pulse that will be considered noise and will be filtered out.
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The Axion-CL ENCA_FILTER RO, ENCA_OPTS[17..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The encoder A circuit includes a programmable noise filter. The value of this register controls the size of the noise pulse that will be considered noise and will be filtered out.
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The Axion-CL ENCB_FILTER RO, ENCB_OPTS[17..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The encoder B circuit includes a programmable noise filter. The value of this register controls the size of the noise pulse that will be considered noise and will be filtered out.
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BOX_OUT_DYN_SEL_SET_A The Axion-CL BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_A[7..0], Aon-CXP, Axion-CL, Claxon-CXP, SEL_0 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_0, BOX_OUT_TTL_0 and BOX_OUT_OPTO_0. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
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The I/O System Registers BOX_OUT_DYN_SEL_SET_A BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_A[15..8], Aon-CXP, Axion-CL, Claxon-CXP, SEL_1 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_1, BOX_OUT_TTL_1 and BOX_OUT_OPTO_1. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
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The I/O System Registers BOX_OUT_DYN_SEL_SET_B BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_B[7..0], Aon-CXP, Axion-CL, Claxon-CXP, SEL_4 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_4, BOX_OUT_TTL_4 and BOX_OUT_OPTO_4. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
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The I/O System Registers BOX_OUT_DYN_SEL_SET_C BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_C[7..0], Aon-CXP, Axion-CL, Claxon-CXP, SEL_8 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_8, BOX_OUT_TTL_8 and BOX_OUT_OC_0. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
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The I/O System Registers BOX_OUT_MODE_SET_A BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_TTL_0 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_0. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_0 bitfield.
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BOX_OUT_MODE_SET_A The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[7..6], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_TTL_3 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_3. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_3 bitfield.
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The I/O System Registers BOX_OUT_MODE_SET_A BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[13..12], Aon-CXP, Axion-CL, Claxon-CXP, MODE_TTL_6 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_6. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_6 bitfield.
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BOX_OUT_MODE_SET_A The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[19..18], Aon-CXP, Axion-CL, Claxon-CXP, MODE_TTL_9 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_9. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_9 bitfield.
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BOX_OUT_MODE_SET_B The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_DIFF_0 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_0. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_0 bitfield.
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The I/O System Registers BOX_OUT_MODE_SET_B BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[7..6], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_DIFF_3 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_3 . This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_d bitfield.
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BOX_OUT_MODE_SET_B The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[13..12], Aon-CXP, Axion-CL, Claxon-CXP, MODE_DIFF_6 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_6. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_6 bitfield.
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The I/O System Registers BOX_OUT_MODE_SET_B BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[19..18], Aon-CXP, Axion-CL, Claxon-CXP, MODE_DIFF_9 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_9. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_9bitfield.
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The I/O System Registers BOX_OUT_MODE_SET_C BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_OPTO_0 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OPTO_0. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_0 bitfield.
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BOX_OUT_MODE_SET_C The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[7..6], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_OPTO_3 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OPTO_3. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_3 bitfield.
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The I/O System Registers BOX_OUT_MODE_SET_C BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[13..12], Aon-CXP, Axion-CL, Claxon-CXP, MODE_OPTO_6 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OPTO_6. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_6 bitfield.
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BOX_OUT_MODE_SET_C The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[19..18], Aon-CXP, Axion-CL, Claxon-CXP, MODE_OC_1 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OC_1. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_9 bitfield.
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Chapter 7 7.1 Introduction This section covers the encoder divider which supported on all of BitFlow’s modern frame grabber families. The purpose of Encoder Divider is to provide the ability to use an encoder running at one rate to drive a line scan camera at a different rate. This circuit is only useful for line scan cameras.
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Encoder Divider Details The Axion-CL 7.2 Encoder Divider Details 7.2.1 Formula The following formula shows the equation used to scale the encoming encoder rate into the camera’s line rate: ------- Fout = The frequency used to driver the camera or the NTG or the CTabs...
The board will stay in this state until Fin goes above 1.6 KHz. This is useful when the encoder is being driven by a stage that is traveling back and forth. At both ends of travel when the stage changes directions, the board will not acquire. Version A.3 BitFlow, Inc. AXN-7-3...
Encoder Divider Control Registers The Axion-CL 7.3 Encoder Divider Control Registers The following table summarizes the registers: Table 7-1 Encoder Divider Registers Name Purpose ENC_DIV_M This controls the M factor in the Encoder Divider equa- tion (see Section 7.2.1) ENC_DIV_N...
Introduction The Axion-CL 8.1.3 Interval Mode Often in situations when a stage is moving back and forth, acquisition is only required over a subsection of the total stage range. Interval mode has been designed for these situations. When the board is in interval mode, it only acquires lines when the encoder counter is between a lower limit and an upper limit.
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VFGx_ENCODERB+ VFGx_ENCODERB- Note: VFGx - refers to the VFG number that you wish to connect to. For example, if you want to connect a TLL A output to VFG 0, then you would use VFG0_ENCODERA_TTL. Version A.3 BitFlow, Inc. AXN-8-3...
Understanding Stage Movement vs. Quadrature Encoder Modes The Axion-CL 8.2 Understanding Stage Movement vs. Quadrature Encoder Modes The quadrature encoder system has many modes that can be used in various combi- nations. These combinations are easier to understand through a few simple illustra- tions.
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Quadrature Encoder Understanding Stage Movement vs. Quadrature Encoder Modes Figure 8-2 shows all of the major quadrature encoder modes. Acquisition Direction Positive Negative Both Not Valid Zoom In Figure 8-2 Quadrature Encoder Modes vs. Acquisition Version A.3 BitFlow, Inc. AXN-8-5...
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Understanding Stage Movement vs. Quadrature Encoder Modes The Axion-CL AXN-8-6 BitFlow, Inc. Version A.3...
Quadrature Encoder and Divider Registers Introduction Quadrature Encoder and Divider Registers Chapter 9 9.1 Introduction This section enumerates the registers used to control the boards quadrature encoder circuit and encoder divider circuit. Version A.3 BitFlow, Inc. AXN-9-1...
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Quadrature Encoder and Divider Registers CON65 Register SEL_ENCQ R/W, CON65[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit selects which quadrature encoder circuit output will be used on this VFG. SEL_ENCQ Meaning Select the output of this VFG’s quadrature circuit output Select the output of VFG0’s quadrature circuit output...
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Quadrature Encoder and Divider Registers CON66 Register QENC_INTRVL_ R/WR/W, CON66[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- This register contains the lower limit value that is used to start acquisition when the system is in interval mode (see QENC_INTRVL_MODE). QENC_DECODE R/W, CON66[24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit determines how often the quadrature counter is incremented.
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(also controlled by QENC_AQ_ DIR) SCAN_STEP_ R/W, CON66[30], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP TRIG The scan step circuit uses the encoder to generate a trigger to the system. The scan step trigger generates a trigger every N lines (N is set in the SCAN_STEP register).
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CON67 Register The Axion-CL QENC_INTRVL_ R/W, CON67[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This register contains the upper limit value that is used to start acquisition when the system is in interval mode (see QENC_INTRVL_MODE). QENC_RESET_ R/W, CON67[25..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-...
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Quadrature Encoder and Divider Registers CON67 Register ENC_DIV_ R/W, CON67[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OPEN_LOOP Setting this bit to 1 forces the encoder divider to run open loop. ENC_DIV_FCLK_ R/W, CON67[31..29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Reserved for future support for alternate Encoder Divider PLL Master clock frequen- cies.
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Quadrature Encoder and Divider Registers CON68 Register RD_ENCQ_ RO, CON68[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED This bit indicates the current state of selected quad encoder circuit output. RD_ENCDIV_ RO, CON68[1], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED This bit displays the current state of the selected encoder divider output.
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Quadrature Encoder and Divider Registers CON69 Register QENC_COUNT RO, CON69[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bitfield displays the current quadrature encoder count. QENC_PHASEA RO, CON69[24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit displays the current logic level of the A quadrature encoder phase.
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CON69 Register The Axion-CL QENC_NEW_ RO, CON69[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP LINES This bit indicates if the system is at an encoder count that corresponds to a new line. When QENC_NO_REAQ = 1, only lines that have not yet been scanned are acquired.
SP_STOP_LIMIT allows this START/STOP record sequence to be run over multiple iter- ations. Among other things, this is useful for supporting SP_COUNT_MODEs min and max. Example: Determine the maximum number of Camera Link clocks occurring between lines over the course of a complete frame. Version A.3 BitFlow, Inc. AXN-10-1...
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System Probe Constants The Axion-CL 10.2 System Probe Constants This subsection lists the constants that be used to program the System Probe. 10.2.1 List of System Probe Events Table 10-1 lists all the events the System Probe can count and can use as the start, stop or sync event.
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Table 10-2 System Probe Events Functions Event Constant Numeric Meaning Value SPF_RISE 0x00 The rising edge of the signal SPF_FALL 0x01 The falling edge of the signal SPF_HIGH 0x02 The signal is high SPF_LOW 0x03 The signal is low Version A.3 BitFlow, Inc. AXN-10-3...
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System Probe Constants The Axion-CL 10.2.3 List of System Probe Counting Modes Table 10-3 lists different modes that the System Probe can count events. These are used when programing the SP_COUNT_MODE registers. Note: The Event Constants in Table 10-3 are defined in the SDK in the file “Gen2Def.h”...
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Below is a list of how to set each register (this uses the constants from Table 10-1). SP_SYNC_EVENT = SPE_IMMEDIATE SP_SYNC_FUNC = SPF_RISE SP_START_EVENT = SPE_IMMEDIATE SP_START_FUNC = SPF_RISE SP_STOP_EVENT = SPE_100_NS SP_STOP_FUNC = SPF_RISE SP_TARGET_EVENT = SPE_FVAL_B SP_TARGET_FUNC = SPF_RISE Version A.3 BitFlow, Inc. AXN-10-5...
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System Probe Examples The Axion-CL SP_STOP_EVENT_LIMIT = 1000000 SP_COUNT_MODE = SPCM_ACC For this example, there is no sync or start event. The recorder starts immediately. The events being recorded are the rising edge of FVAL. The SP_STOP_EVENT_LIMIT con- trols how long the counter accumulates (in this case it is counting the number of 100 nanosecond clocks).
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Event is high 3 (11b) Event is low SP_STOP_EVENT R/W, SP_EVENTS[13..8], Axion-CL Specifies the event that will stop recording. See Table 10-1 for a list of events. Note: This register can only be writeen when SP_BUSY reads back 0. SP_STOP_FUNC R/W, SP_EVENTS[15..14], Axion-CL...
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System Probe SP_EVENTS SP_START_FUNC R/W, SP_EVENTS[23..22], Axion-CL Specifies the event function that will start recording. See Table 10-1 for a list of events. SP_START_FUNC Meaning 0 (00b) Rising edge of event 1 (01b) Falling edge of event 2 (10b) Event is high...
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System Probe SP_CON SP_COUNT_ R/W, SP_CON[1..0], Axion-CL MODE This register sets the mode of how the System Probe count (in register SP_COUNT) is updated. SP_COUNT_ Meaning MODE 0 (00b) Current: on each update SP_COUNT will reflect the current event capture.
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SP_CON The Axion-CL SP_RST WO, SP_CON[11], Axion-CL Reset the System Probe. Always writable. Always reads back 0. SP_COUNT_ RO, SP_CON[14], Axion-CL UPDATED SP_COUNT updates after each STOP event. SP_COUNT_UPDATED is set to 1 by hard- ware when the SP_COUNT is updated. In cases where SP_STOP_EVENT_LIMIT is > 0, there will be multiple updates to SP_COUNT.
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SP_STAT The Axion-CL SP_COUNT RO, SP_STAT[23..0], Axion-CL This register indicates the number of events that have occurred. This can be read at any time. When SP_BUSY is running, there may be several updates to SP_COUNT (it is updated after each STOP event). SP_STOP_EVENT_LIMIT controls how many stop events we require to end the capture.
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SP_LIMIT The Axion-CL SP_STOP_ R/W, SP_LIMIT[23..0], Axion-CL EVENT_LIMIT When collecting statistical data (i.e. SP_COUNT_MODE is not equal to 0), this register controls how many start/stop events should occur before the System Probe stops recording event data. Set this register to 1 for “single shot” event recording. Set it to the maximum number of event windows to count when using the System Probe for statistical calculations.
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This section contains definitions for registers that are only on the Axion-CL platform. The Cyton-CXP and the Axion-CL have many of the same registers, but some are only relevant to CXP and some are only used for Camera Link. This chapter contains the latter.
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Axion Camera Link Registers CL_IOBUF_CTL IOBUF_SETTING R/W, CL_IOBUF_CTL[4..0], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not be programmed directly by customers. IOBUF_LANE R/W, CL_IOBUF_CTL[10..8], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not be programmed directly by customers.
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Axion Camera Link Registers CL_CHAN_CONFIG PLL_PLL_ R/W, CL_CHAN_CONFIG[0], Axion-CL PHASE_DIR This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers. PLL_ADJUST_ R/W, CL_CHAN_CONFIG[1], Axion-CL PLL_PHASE This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers.
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CL_CHAN_CONFIG The Axion-CL ALIGN_AUTO_ R/W, CL_CHAN_CONFIG[8], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers. PLL_CHAN R/W, CL_CHAN_CONFIG[30..28], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers.
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UART_CON_BASE The Axion-CL RS232_TX_ R/W, UART_CON_BASE[7..0], Axion-CL DATA Data byte to be sent out the CL RS-232 link. RS232_TX_GO R/W, UART_CON_BASE[8], Axion-CL Cause the data byte to be sent out the CL RS-232 link. RS232_RX_INT_ R/W, UART_CON_BASE[9], Axion-CL ENABLE Enable the interrupt that is asserted whenever a byte is received on the CL RS-232 link.
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Axion Camera Link Registers UART_CON_BASE RS232_TX_ R/W, UART_CON_BASE[31], Axion-CL READY When this bitfield is 1 the UART is ready to send another byte. Version A.3 BitFlow, Inc. AXN-11-9...
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Axion Camera Link Registers UART_RDAT_BASE RS232_RX_ RO, UART_RDAT_BASE[7..0], Axion-CL DATA The top of the CL RS-232 receive FIFO. Ready this register removes this byte from the FIFO. Version A.3 BitFlow, Inc. AXN-11-11...
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Axion Camera Link Registers CL_CON_BASE CL_USE_FVAL R/W, CL_CON_BASE[0], Axion-CL Setting this bit to 1 will cause the CL front end to honor the FVAL (Frame Valid) signal. This should be set to 1 for area scan cameras and 0 for line scan cameras.
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Axion Camera Link Registers TAP_CON_BASE TAP_MODE R/W, TAP_CON_BASE[0], Axion-CL Reserved. TAP_FIXED_VAL R/W, TAP_CON_BASE[19..4], Axion-CL Reserved. TAP_OUTPUT_ R/W, TAP_CON_BASE[31], Axion-CL This bit should be set to 1 to output 10 to 16 bit pixels as 16-bit words. Version A.3 BitFlow, Inc.
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Axion Camera Link Registers TAP_TABLE_ADDR_BASE TAP_TABLE_ R/W, TAP_TABLE_ADDR_BASE[3..0], Axion-CL OFFS This register is used to program that Axion’s tap re-formatter. It should not be pro- grammed directly by users. TAP_TABLE_ R/W, TAP_TABLE_ADDR_BASE[19..16], Axion-CL INDEX This register is used to program that Axion’s tap re-formatter. It should not be pro- grammed directly by users.
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Axion Camera Link Registers TAP_TABLE_DAT_BASE TAP_DATA R/W, TAP_TABLE_DAT_BASE[31..0], Axion-CL This register is used to program that Axion’s tap re-formatter. It should not be pro- grammed directly by users. Version A.3 BitFlow, Inc. AXN-11-19...
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Axion Camera Link Registers FLASH_CON_BASE FLASH_CODE R/W, FLASH_CON_BASE[7..0], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. FLASH_WRITE R/W, FLASH_CON_BASE[8], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers.
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FLASH_CON_BASE The Axion-CL FLASH_EN4B_ R/W, FLASH_CON_BASE[15], Axion-CL ADDR This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. FLASH_EX4B_ R/W, FLASH_CON_BASE[16], Axion-CL ADDR This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers.
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FLASH_ADDR_BASE The Axion-CL FLASH_ADDR R/W, FLASH_ADDR_BASE[31..0], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. AXN-11-24 BitFlow, Inc. Version A.3...
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This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. FLASH_DATA_IN R/W, FLASH_DAT_BASE[15..8], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers.
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TAP_DIPR_CONTROL The Axion-CL DIPR_NUM_ R/W, TAP_DIPR_CONTROL[3..0], Axion-CL TAPS When the board is using the DIPR (Dedicated Interleaved Pixel Router), this register should be set to the number of taps the camera is putting out. DIPR_PIX_SIZE R/W, TAP_DIPR_CONTROL[11], Axion-CL When the board is using the DIPR, set this bit to indicate the pixels size. Set to 0 for 8- bit pixels, set to 1 for 10-bit to 16-bit pixels.
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CLMON_FVAL_EXP The Axion-CL FVAL_EXP_ R/W, CLMON_FVAL_EXP[23..0], Axion-CL COUNT The expected number of lines per frame (FVAL). FVAL_ERROR R/W, CLMON_FVAL_EXP[24], Axion-CL If the lines per FVAL is different from LFAL_EXP_COUNT, this bit will be set to 1. If a mismatch occurs, monitoring of the FVAL will stop. Set this bit to 0 and then set FVAL_ ENABLE to 1 to restart FVAL monitoring.
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Read LVAL_B/M/F_ERROR and FVAL_ERROR bits to determine the cause of the inter- rupt. LVAL_B_ENABLE R/W, CLMON_LVAL_EXP[28], Axion-CL Setting this bit to 1 to tells the board to monitor the CL Base LVAL. If this bit is 0, the CL Base LVAL will not be monitored.
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Axion Camera Link Registers CLMON_LVAL_EXP LVAL_F_ENABLE R/W, CLMON_LVAL_EXP[30], Axion-CL Setting this bit to 1 to tells the board to monitor the CL Full LVAL. If this bit is 0, the CL Full LVAL will not be monitored. LVAL_AUTO_ R/W, CLMON_LVAL_EXP[31], Axion-CL...
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Axion Camera Link Registers CLMON_FVAL_COUNT FVAL_COUNT R/W, CLMON_FVAL_COUNT[23..0], Axion-CL Displays the current number of lines per frame, updated every frame. If a mismatch occurs, this will display the number of lines per frame for the mismatching frame. Version A.3 BitFlow, Inc.
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Axion Camera Link Registers CLMON_LVAL_B_COUNT LVAL_B_COUNT R/W, CLMON_LVAL_B_COUNT[23..0], Axion-CL The current number of CL clocks per line for the CL Base input. This is updates every CL Base LVAL. If a mismatch occurs, this will display the number of CL clocks for the mismatching CL Base line.
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Axion Camera Link Registers CLMON_LVAL_M_COUNT LVAL_M_COUNT R/W, CLMON_LVAL_M_COUNT[23..0], Axion-CL The current number of CL clocks per line for the CL Medium input. This is updates every CL Medium LVAL. If a mismatch occurs, this will display the number of CL clocks for the mismatching CL Medium line.
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CLMON_LVAL_F_COUNT LVAL_F_COUNT R/W, CLMON_LVAL_F_COUNT[23..0], Axion-CL The current number of CL clocks per line for the CL Full input. This is updates every CL Full LVAL. If a mismatch occurs, this will display the number of CL clocks for the mis- matching CL Full line.
Axion Power and Miscellaneous Registers Introduction Axion Power and Miscellaneous Registers Chapter 12 12.1 Introduction This chapter contains details on the Axion PoCL registers as well as some other mis- cellaneous registers. Version A.3 BitFlow, Inc. AXN-12-1...
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Axion Power and Miscellaneous Registers CON104 0_POCL_EN_ RO, CON104[0], Axion-CL POWER PoCL power has been applied to the camera. 0_POCL_EN_ RO, CON104[2], Axion-CL CAM_SENSE PoCL sense is enabled. 0_POCL_HW_ RO, CON104[3], Axion-CL Describe 0_POCL_HW_DIS. 0_POCL_OPEN_ RO, CON104[5], Axion-CL DETECTED Open circuit detected.
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CON104 The Axion-CL 0_POCL_SENSE_ R/W, CON104[14], Axion-CL BYPASS Bypass the PoCL sense circuit and apply power. This register is for testing only, it should not be set by the user. 0_ENABLE_ R/W, CON104[15], Axion-CL POCL_SYSTEM Poking this bit to 1 enables the PoCL circuit for this connector.
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The Axion-CL 0_POCL_TIMER_ R/W, CON105[10..0], Axion-CL This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support. 0_POCL_TIMER_ R/W, CON105[26..16], Axion-CL STABLE This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support.
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The Axion-CL 0_POCL_TIMER_ R/W, CON106[10..0], Axion-CL This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support. 0_POCL_TIMER_ R/W, CON106[26..16], Axion-CL DISCONNECT This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support.
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CON136 The Axion-CL 1_POCL_EN_ RO, CON136[0], Axion-CL POWER See 0_POCL_EN_POWER. 1_POCL_EN_ RO, CON136[2], Axion-CL CAM_SENSE See 0_POCL_EN_CAM_SENSE. 1_POCL_HW_ RO, CON136[3], Axion-CL See 0_POCL_HW_DIS. 1_POCL_OPEN_ RO, CON136[5], Axion-CL DETECTED See 0_POCL_OPEN_DETECTED. 1_POCL_OVER_ RO, CON136[6], Axion-CL DETECTED See 0_POCL_OVER_DETECTED. 1_POCL_OVER_ RO, CON136[7], Axion-CL LATCH See 0_POCL_OVER_LATCH.
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Axion Power and Miscellaneous Registers CON136 1_POCL_SENSE_ R/W, CON136[14], Axion-CL BYPASS See 0_POCL_SENSE_BYPASS. 1_ENABLE_ R/W, CON136[15], Axion-CL POCL_SYSTEM See 0_ENABLE_POCL_SYSTEM. Version A.3 BitFlow, Inc. AXN-12-11...
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Axion Power and Miscellaneous Registers CON137 1_POCL_TIMER_ R/W, CON137[10..0], Axion-CL See 0_POCL_TIMER_OFF. 1_POCL_TIMER_ R/W, CON137[26..16], Axion-CL STABLE See 0_POCL_TIMER_STABLE. Version A.3 BitFlow, Inc. AXN-12-13...
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Axion Power and Miscellaneous Registers CON138 1_POCL_TIMER_ R/W, CON138[10..0], Axion-CL See 0_POCL_TIMER_ON. 1_POCL_TIMER_ R/W, CON138[26..16], Axion-CL DISCONNECT See 0_POCL_TIMER_DISCONNECT. Version A.3 BitFlow, Inc. AXN-12-15...
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Axion Power and Miscellaneous Registers CON168 2_POCL_EN_ RO, CON168[0], Axion-CL POWER See 0_POCL_EN_POWER. 2_POCL_EN_ RO, CON168[2], Axion-CL CAM_SENSE See 0_POCL_EN_CAM_SENSE. 2_POCL_HW_ RO, CON168[3], Axion-CL See 0_POCL_HW_DIS. 2_POCL_OPEN_ RO, CON168[5], Axion-CL DETECTED See 0_POCL_OPEN_DETECTED. 2_POCL_OVER_ RO, CON168[6], Axion-CL DETECTED See 0_POCL_OVER_DETECTED.
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CON168 The Axion-CL 2_POCL_SENSE_ R/W, CON168[14], Axion-CL BYPASS See 0_POCL_SENSE_BYPASS. 2_ENABLE_ R/W, CON168[15], Axion-CL POCL_SYSTEM See 0_ENABLE_POCL_SYSTEM. AXN-12-18 BitFlow, Inc. Version A.3...
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CON169 The Axion-CL 2_POCL_TIMER_ R/W, CON169[10..0], Axion-CL See 0_POCL_TIMER_OFF. 2_POCL_TIMER_ R/W, CON169[26..16], Axion-CL STABLE See 0_POCL_TIMER_STABLE. AXN-12-20 BitFlow, Inc. Version A.3...
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CON170 The Axion-CL 2_POCL_TIMER_ R/W, CON170[10..0], Axion-CL See 0_POCL_TIMER_ON. 2_POCL_TIMER_ R/W, CON170[26..16], Axion-CL DISCONNECT See 0_POCL_TIMER_DISCONNECT. AXN-12-22 BitFlow, Inc. Version A.3...
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CON200 The Axion-CL 3_POCL_EN_ RO, CON200[0], Axion-CL POWER See 0_POCL_EN_POWER. 3_POCL_EN_ RO, CON200[2], Axion-CL CAM_SENSE See 0_POCL_EN_CAM_SENSE. 3_POCL_HW_ RO, CON200[3], Axion-CL See 0_POCL_HW_DIS. 3_POCL_OPEN_ RO, CON200[5], Axion-CL DETECTED See 0_POCL_OPEN_DETECTED. 3_POCL_OVER_ RO, CON200[6], Axion-CL DETECTED See 0_POCL_OVER_DETECTED. 3_POCL_OVER_ RO, CON200[7], Axion-CL LATCH See 0_POCL_OVER_LATCH.
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Axion Power and Miscellaneous Registers CON200 3_POCL_SENSE_ R/W, CON200[14], Axion-CL BYPASS See 0_POCL_SENSE_BYPASS. 3_ENABLE_ R/W, CON200[15], Axion-CL POCL_SYSTEM See 0_ENABLE_POCL_SYSTEM. Version A.3 BitFlow, Inc. AXN-12-25...
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Axion Power and Miscellaneous Registers CON201 3_POCL_TIMER_ R/W, CON201[10..0], Axion-CL See 0_POCL_TIMER_OFF. 3_POCL_TIMER_ R/W, CON201[26..16], Axion-CL STABLE See 0_POCL_TIMER_STABLE. Version A.3 BitFlow, Inc. AXN-12-27...
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Axion Power and Miscellaneous Registers CON202 3_POCL_TIMER_ R/W, CON202[10..0], Axion-CL See 0_POCL_TIMER_ON. 3_POCL_TIMER_ R/W, CON202[26..16], Axion-CL DISCONNECT See 0_POCL_TIMER_DISCONNECT. Version A.3 BitFlow, Inc. AXN-12-29...
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Day that this firmware was compiled in BCD format. Example: 0x18 the 18th of the month. FW_BUILD_ RO, CON356[31..24], Karbon-CXP, Cyton-CXP MONTH Month that this firmware was compiled in BCD format. Example: 0x12 is december. Version A.3 BitFlow, Inc. AXN-12-31...
Chapter 13 13.1 Introduction This chapter describes the general specifications of the Axion-CL family. The numeri- cal values for he specifications are listed in Table 13-1. If more information is available for a given specification t will be an entry in the column marked “Details”.
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Introduction The Axion-CL Table 13-1 Axion-CL Specifications Specifications Value Units Details Mechanical dimensions 6.8 x 4.2 Inches Mechanical dimensions 17.4 x 10.6 Centimeters Maximum PoCL Power @12 Volts Watts Per CL Connector LVDS Drivers SN65LVDS31D LVDS Receivers SNLVDS3486 TTL Drivers...
13.2 PCI Express Compatibility The Axion-CL is a PCIe x4 Gen 2 board. However, it will work in any PCIe slot that it fits into. This means it will work in x4, x8 and x16 slots, however, it will also work in x1 slots if these slots are mechanically compatibility with an x4 board, though performance will be greatly degraded.
Maximum Pixels Per Line The Axion-CL 13.3 Maximum Pixels Per Line The maximum pixels per line depends on the camera’s output tap format and the pixel format. The board’s Tap Reformatter supports both interleaved (e.g. 1X4-1Y) and segmented (e.g. 4X1-1Y) tap formats. However, the maximum line lengths for inter- leaved cameras can be extended using a special Dedicated Interleaved Pixel Router (DIPR).
Maximum Lines Per Frame 13.4 Maximum Lines Per Frame This limitation is for area scan cameras. For line scan cameras, the number of lines per frame is essentially unlimited. Please contact BitFlow customer support for more infor- mation. Version A.3 BitFlow, Inc.
The Axion-CL power requirements listed inTable 13-1 are the requirements of the board’s circuitry only. In addition, the Axion-CL can provide up to 4 watts of power to each Camera Link connector. The 12 Volt rail of the PCIe bus cannot provide enough power if all CL connector links are drawing maximum power.
Chapter 14 14.1 Introduction This chapter describes the mechanical characteristics of the Axion-CL This includes description of all of the connectors on the board and pin-outs for these connectors. The mechanical layouts of the Axions are shown on the following pages. Please see the table for cross reference.
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Introduction The Axion-CL SW1.2 SW1.1 Pin 1 D3 D4 D5 D6 D7 D8 D8 D10 Pin 1 Pin 2 P3/P4 BASE MED/FULL Pin 59 Pin 60 TRILED2 End View PCI Express x4 Gen 2 Connector Figure 14-1 Axion-1xE Board Layout AXN-14-2 BitFlow, Inc.
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Introduction The Axion-CL Flex cable To Main Board P1 Figure 14-7 Axion-4xB Fourth CL Connector AXN-14-8 BitFlow, Inc. Version A.3...
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14.2.1 The CL Connectors The CL connectors are for connecting Camera Link cameras. The Axion-CL uses both MDR and SDR connectors. These connectors are fully compliant with the Camera Link version 1.1 and later specification.
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The Axion-CL Connectors The Axion-CL Table 14-4 Camera Link Connectors - Axion-1xE and Axion 2xE Camera(s) BASE0 MED/FULL0 BASE1 MED/FULL1 One Base CL Camera Camera 0 - CL1 One Medium CL Camera Camera 0 - CL1 Camera 0 - CL2...
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Switches 14.3 Switches There is one piano-type switch block, SW1, on the Axion-CL with two switches. These are used to identify individual boards when there is more than one board in a system. The idea is to set the switches differently on each board in the system. The switch set- tings can be read for each board from software (by reading the SW bitfield).
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BitFlow’s Customer Support team. 14.4.2 Jumper JP2 T is one user configurable jumper on the Axion-CL, it controls the source of the power that is provided to the Camera Link camera(s) connected to the Axion (PoCL power).
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VFG on the mulit-VFG Axions are ORed together. The following table show ena example for one LED on aboard with two VFGs. Table 14-8 LED control from two VFGs VFG0 VFG1 LED_BLUE LED_BLUE Version A.3 BitFlow, Inc. AXN-14-13...
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LEDs The Axion-CL 14.5.1 Camera Status LEDS The Camera Status LEDS change color and are blinking or steady depending on the status of the connected cameras and the camera. There is one status LED for each cameras. Cameras that are using two connectors still only get one status LED. See Table 14-9 for detailed information on the meaning of these LEDs.
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I/O problems. It can be used as a trigger, encoder, or I/O that is routed off the board. Please see Section 2.1 for more information on how the button can be routed. Note: The Axion Rev 2.x models do not have this button. Version A.3 BitFlow, Inc. AXN-14-15...
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PCs. This connector is also known as the “floppy connector”. For PCs that do have this type of connector, BitFlow offers an adapter cable that goes between P4 and a standard Molex 4-pin peripheral connector available in almost all PCs.
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Mechanical The BitBox Box Connector 14.8 The BitBox Box Connector This connector is for the BitBox, and I/O break out box that is available from BitFlow. Please contact BitFlow for more information. Version A.3 BitFlow, Inc. AXN-14-17...
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I/O Connector Pinout for the Axion-1xE, Axion-2xE and Axion-4xB The Axion-CL 14.9 I/O Connector Pinout for the Axion-1xE, Axion-2xE and Axion-4xB The pin-out for the I/O Connector for the Axion-1xE, Axion2xE and Axion-4xB are illustrated in the Table 14-11. Note: Signal names start with the Virtual Frame Grabber (VFG) that they are routed to.
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I/O Connector Pinout for the Axion-1xB The Axion-CL 14.10 I/O Connector Pinout for the Axion-1xB The pin-out for the I/O Connector for the Axion-1xB is illustrated in the Table 14-12. Table 14-12 I/O Connector for the Axion-1xB Signal Comment VFG0_TRIGGER+...
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I/O Connector Pinout for the Axion-2xB The Axion-CL Table 14-13 I/O Connector for the Axion-2xB Signal Comment VFG1_ENCODERB_TTL VFG1_CC2_TTL VFG1_CC4_TTL AXN-14-22 BitFlow, Inc. Version A.3...
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