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The Axion-CL
Hardware Reference Manual
BitFlow, Inc.
400 West Cummings Park, Suite 5050
Woburn, MA 01801
USA
Tel: 781-932-2900
Sales: sales@bitflow.com
Support: support@bitflow.com
Web: www.bitflow.com
Revision A.3

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Summary of Contents for BitFlow Axion-CL

  • Page 1 The Axion-CL Hardware Reference Manual BitFlow, Inc. 400 West Cummings Park, Suite 5050 Woburn, MA 01801 Tel: 781-932-2900 Sales: sales@bitflow.com Support: support@bitflow.com Web: www.bitflow.com Revision A.3...
  • Page 2 BitFlow, Inc. BitFlow, Inc. makes no implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document, nor does it make a commit- ment to update the information contained in.
  • Page 3: Table Of Contents

    Conventions AXN-P-2 Bitfield definitions AXN-P-3 Example Bitfield Definition AXN-P-3 Bitfield Definition Explanation. AXN-P-3 1 - General Description and Architecture The Axion-CL family AXN-1-1 Camera Link AXN-1-1 Virtual vs. Hardware AXN-1-1 The Virtual Frame Grabber (VFG) AXN-1-2 Axion Configuration Spaces AXN-1-2...
  • Page 4 Table of Contents Triggering the StreamSync Acquisition Engine AXN-2-9 Comparing the StreamSync Acquisition Engine to Other BitFlow products AXN-2-10 AE_CON AXN-2-11 AE_STATUS AXN-2-13 AE_STREAM_SEL AXN-2-15 V_WIN_DIM AXN-2-17 Z_WIN_CON AXN-2-19 Z_WIN_DIM AXN-2-23 Z_WIN_DIM_EXT AXN-2-25 Y_INT_DEC AXN-2-27 Y_WIN_CON AXN-2-29 Y_WIN_DIM AXN-2-33 Y_WIN_DIM_EXT AXN-2-35...
  • Page 5 CON64 AXN-6-16 TRIG_OPTS AXN-6-21 ENCA_OPTS AXN-6-23 ENCB_OPTS AXN-6-25 BOX_OUT_DYN_SEL_SET_A AXN-6-27 BOX_OUT_DYN_SEL_SET_B AXN-6-30 BOX_OUT_DYN_SEL_SET_C AXN-6-32 BOX_OUT_MODE_SET_A AXN-6-34 BOX_OUT_MODE_SET_B AXN-6-39 BOX_OUT_MODE_SET_C AXN-6-44 7 - Encoder Divider Introduction AXN-7-1 Encoder Divider Details AXN-7-2 Formula AXN-7-2 Example AXN-7-2 Restrictions AXN-7-2 PLL Locking AXN-7-3 BitFlow, Inc.
  • Page 6 List of System Probe Counting Modes AXN-10-4 System Probe Examples AXN-10-5 Example - Clocks per Line AXN-10-5 Example - Camera Frame Rate AXN-10-5 SP_EVENTS AXN-10-7 SP_CON AXN-10-10 SP_STAT AXN-10-13 SP_LIMIT AXN-10-15 11 - Axion Camera Link Registers Introduction AXN-11-1 CL_IOBUF_CTL AXN-11-2 CL_CHAN_CONFIG AXN-11-4 BitFlow, Inc.
  • Page 7 CON202 AXN-12-28 CON356 AXN-12-30 CON357 AXN-12-32 13 - Specifications Introduction AXN-13-1 PCI Express Compatibility AXN-13-3 Maximum Pixels Per Line AXN-13-4 Maximum Lines Per Frame AXN-13-5 Axion Power Requirements AXN-13-6 14 - Mechanical Introduction AXN-14-1 The Axion-CL Connectors AXN-14-9 BitFlow, Inc.
  • Page 8 Camera Status LEDS AXN-14-14 Button AXN-14-15 The Auxiliary Power Connector AXN-14-16 The BitBox Box Connector AXN-14-17 I/O Connector Pinout for the Axion-1xE, Axion-2xE and Axion-4xB AXN-14-18 I/O Connector Pinout for the Axion-1xB AXN-14-20 I/O Connector Pinout for the Axion-2xB AXN-14-21 BitFlow, Inc.
  • Page 9: Support Services Axn

    Second, it is a reference manual describing in detail the functionality of all of the board’s registers. P.1.1 Support Services BitFlow, Inc. provides both sales and technical support for the Axion family of prod- ucts. P.1.2 Technical Support Our web site is www.bitflow.com.
  • Page 10 Purpose The Axion-CL P.1.4 Conventions Table P-1 shows the conventions that are used for numerical notation in this manual. Table P-1 Base Abbreviations Base Designator Example Binary 1010b Decimal None 4223 Hexidecimal 12fah Table P-2 shows the numerical abbreviations that are used in this manual.
  • Page 11: Bitfield Definitions Axn

    Bitfield definitions P.2 Bitfield definitions P.2.1 Example Bitfield Definition is what each bitfield definition looks like: BITFIELD R/W, CON0[7..0], Axion-CL Bitfield discussion. P.2.2 Bitfield Definition Explanation. The definitions is broken into three sections (see Table P-3). Table P-3 Bitfield Sections.
  • Page 12 This bitfield is functional only the Alta family. Cyton-CXP This bitfield is functional only on the Cyton-CXP family Axion-CL This bitfield is functional only on the Axion-CL family Aon-CXP This bitfield is functional on the Aon-CXP family Claxon-CXP This bitfield is functional on the Axion-CXP family AXN-P-4 BitFlow, Inc.
  • Page 13: General Description And Architecture

    Chapter 1 1.1 The Axion-CL family The purpose of this chapter is to explain, at a block diagram level, how the Axion-CL works. Currently there are five main models in the Axion-CL family: AXN-PC2-1xE, support for one Base, Medium, Full or 80-bit camera...
  • Page 14: Axion Configuration Spaces Axn-1-2

    1.1.4 Axion Configuration Spaces The Axion-CL model supports up to four VFGs. Each VFG appears to operating sys- tem and your software as a separate device. The block diagrams for the different models are shown in the following section.
  • Page 15: General Description Axn-1-3

    General Description 1.2 General Description The Axion-CL is a x4 PCI Express Gen 2 board. It can work in any PCI Express slot that it can fit it. Usually this means an x4, x8 or x16 slot. However, some mother boards have x1 slots with x4 connectors.
  • Page 16 General Description The Axion-CL Physical Layer Physical Layer Camera Link Control Routing Physical Layer Acq. Acq. Physical Layer Control Control Logic Logic Power Virtual Virtual Connector Frame Frame Grabber Grabber PCI Express Bus Figure 1-2 The Axion-2xE Block Diagram AXN-1-4 BitFlow, Inc.
  • Page 17 General Description and Architecture General Description Camera Link Physical Control Layer Routing Power Acq. Control Logic Virtual Connector Frame Grabber PCI Express Bus Figure 1-3 The Axion-1xB Block Diagram Version A.3 BitFlow, Inc. AXN-1-5...
  • Page 18 General Description The Axion-CL Physical Layer Camera Link Control Routing Physical Layer Acq. Acq. Control Control Power Logic Logic Virtual Virtual Connector Frame Frame Grabber Grabber PCI Express Bus Figure 1-4 The Axion-2xB Block Diagram AXN-1-6 BitFlow, Inc. Version A.3...
  • Page 19: Video Data Axn-1-7

    This can be used to send and receive control data to/from the camera. The serial link is always synchronous. The camera does not send data without being requested from the host. Version A.3 BitFlow, Inc. AXN-1-7...
  • Page 20: Camera Link Trigger Support Axn-1-8

    Axion-CL. 1.2.4 Axion I/O system The Axion-CL has a sophisticated I/O system, which is extremely flexible. The system take in many inputs, routes them to a number of internal signals which can be further manipulate, then routes the results to a wide rand of outputs.
  • Page 21 General Description 1.2.7 The Volume Of Interest Acquisition Engine The Axion-CL introduces the concept of Volume of Interest (VOI) as part of its Stream- Sync Acquisition Engine. This has been designed from the ground up to satisfy the needs of real world machine vision application. The VOI provide robust and flexible...
  • Page 22 The Axion-CL 1.3 Firmware Unlike many of BitFlow’s previous models of frame grabbers, the Axion family does not swap firmware on the fly (this is similar to the Cyton). The Axion is shipped with firmware that supports the latest Camera Link Specification and has been tested with all known cameras at the time of the release.
  • Page 23: Axion Camera Configuration Files Axn-1-11

    Axion Camera Configuration Files 1.4 Axion Camera Configuration Files The Axion is the second member of BitFlow’s Gen 2 family. These frame grabber all use an XML based camera configuration file. This differs from previous models of Bit- Flow’s frame grabbers that have all used a binary proprietary file format (which mean they could only be edited using BitFlow’s tools).
  • Page 24: The Axion Models Axn-1-12

    The Axion Models The Axion-CL 1.5 The Axion Models There are five models of the Axion-CL. Table 1-1 illustrates the capabilities of each model. Table 1-1 The Axion Models Capability AXN-PC2- AXN-PC2- AXN-PC2- AXN-PC2- AXN-PC2- Number of Base CL cameras supported...
  • Page 25: The Streamsync Acquisition Engine

    The StreamSync system is a start- from-scratch complete redesign of the acquisition and DMA parts of a frame grabber. BitFlow used its years of experience in this area to design a next generation, super efficient capture system.
  • Page 26: The Streamsync Acquisition Engine World Axn-2-2

    The StreamSync Acquisition Engine World The Axion-CL 2.2 The StreamSync Acquisition Engine World We are used to the concept that images have an X and a Y dimension. The Acquisition Engine expands on this concept by adding two further dimension Z and V. The Z dimension controls a sequence of frames or “Volume”...
  • Page 27 Start Of Frame (SOF) packet (or FVAL from a CL camera) is sent from the camera, or it can be opened by a trigger (all SOF packets are ignored Version A.3 BitFlow, Inc. AXN-2-3...
  • Page 28: Observing The Streamsync Acquisition Engine Axn-2-4

    The StreamSync Acquisition Engine World The Axion-CL until the trigger condition is met) or it can just be opened immediately, as soon the Acquisition Engine level is inside the X window (i.e. the stat above). Table 2-1 enumer- ates all of these conditions..
  • Page 29: Regions Of Interest (Roi) With The Streamsync Acquisition Engine. Axn-2-5

    Figure 2-3 Acquisition Engine ROI Similarly there is a Z_OFFS register which if non-zero can cause the board to discard a certain number of frames before starting an acquisition of a sequence. This concept is illustrated in Figure 2-4. Version A.3 BitFlow, Inc. AXN-2-5...
  • Page 30 The StreamSync Acquisition Engine World The Axion-CL V Window Z_OFFS Z_SIZE Z Window Y Window X Window Camera Frames Figure 2-4 Z_OFFS Illustration AXN-2-6 BitFlow, Inc. Version A.3...
  • Page 31: Window Interrupts Axn-2-7

    V Window (hypervolume). Figure 2-5 Show the relationship between the interrupts and the acquisition Windows. Note: The labels in italics in Figure 2-5 are are the actual interrupt names that can be used with the BitFlow SDK function calls. Z_SIZE BFIntTypeZStart...
  • Page 32 AE State Machine The Axion-CL 2.4 AE State Machine Hypervolume Volume Frame Line V_ACQ_COUNT++ Idle Z_ACQ_COUNT++ Y_ACQ_COUNT++ X_ACQ_COUNT++ ZAq* EOD** Window Window Window Window INT_Z_ACQUIRED INT_Y_ACQUIRED Idle INT_X_ACQUIRED Idle Idle Idle Abort Abort Abort Abort Idle Z_SIZE Y_SIZE Z_CLOSE Y_CLOSE...
  • Page 33: Triggering The Streamsync Acquisition Engine Axn-2-9

    Please refer to Figure 2-2 for more information on how a trigger can be used to change the state of the Acquisition Engine. Version A.3 BitFlow, Inc. AXN-2-9...
  • Page 34: Comparing The Streamsync Acquisition Engine To Other Bitflow Products Axn-2-10

    While the Acquisition Engine might seem very complex, it is actually quite simple to use and has considerably more power than previous acquisition engines used on all previous BitFlow frame grabbers. From a software point of view, the BitFlow API hides the differences between the traditional acquisition systems and the newer Acquisition Engine.
  • Page 35 2.7 AE_CON Name AE_RUN_LEVEL AE_RUN_LEVEL AE_RUN_LEVEL AE_RUN_LEVEL Reserved Reserved Reserved Reserved Reserved CLR_ACQ_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-11...
  • Page 36 AE_CON The Axion-CL AE_RUN_LEVEL R/W, AE_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This is the main control for starting/aborting acquisition. Writing this register changes the current run level. Reading this register returns the current run level command (not the current status). The abort run levels exit acquisition on a clean boundary. V exits on a volume boundary, Z on a frame boundary, Y on a line boundary, X on a 128-byte data boundary.
  • Page 37 2.8 AE_STATUS Name AE_STATE AE_STATE AE_STATE Reserved AE_FIFO_OVERFLOW Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-13...
  • Page 38 AE_STATUS The Axion-CL AE_STATE RO, AE_STATUS[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- This register indicates the current run level of the acquisition engine. The following table shows the meanings of each state. AE_STATE Meaning 0 (000b) Idle - System is idle...
  • Page 39 2.9 AE_STREAM_SEL Name STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved USE_SYNTHETIC_FRAME Version A.3 BitFlow, Inc. AXN-2-15...
  • Page 40 Currently only the values 0 to 3 are supported. Generally this register should be programmed to correspond to the VFG number that is being used to access the acquisition engine. For example, for VFG1 set this register to 1. USE_ R/W, AE_STREAM_SEL[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- SYNTHETIC_ ton-CXP FRAME Use the Synthetic Frame generator instead of the camera.
  • Page 41 2.10 V_WIN_DIM Name V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-17...
  • Page 42 The Axion-CL V_SIZE R/W, V_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- This register defines size of the V window, that is, the number of volumes to acquire. A value of 0XFFFF means infinite. When set to infinite, the acquisition engine can be stopped by writing AE_RUN_LEVEL.
  • Page 43 2.11 Z_WIN_CON Name Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_SEL Z_CLOSE_TRIG_SEL Z_CLOSE_TRIG_SEL Z_CLOSE_TRIG_SEL Z_CLOSE Z_CLOSE Z_CLOSE Z_CLOSE Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_SEL Z_OPEN_TRIG_SEL Z_OPEN_TRIG_SEL Z_OPEN_TRIG_SEL Z_OPEN Z_OPEN Z_OPEN Z_OPEN Z_SYNC Z_SYNC Z_SYNC Z_SYNC Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-19...
  • Page 44 Z_WIN_CON The Axion-CL Z_CLOSE_TRIG_ R/W, Z_WIN_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- FUNC This register determines which trigger change (if any) will end the Z window. Z_CLOSE_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger 2 (0010b)
  • Page 45 The StreamSync Acquisition Engine Z_WIN_CON Z_OPEN_TRIG_ R/W, Z_WIN_CON[15..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- FUNC ton-CXP This register determines which trigger change (if any) will start Z window. Z_OPEN_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger...
  • Page 46 Z_WIN_CON The Axion-CL Z_SYNC R/W, Z_WIN_CON[27..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This field enforces the data-synchronization of streaming video to the acquisition engine for each individual frame in the z window. The following table shows explains this field. Z_SYNC Meaning No synchronization.
  • Page 47 2.12 Z_WIN_DIM Name Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Version A.3 BitFlow, Inc. AXN-2-23...
  • Page 48 Z_WIN_DIM The Axion-CL Z_SIZE R/W, Z_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Number of frames (Y windows) to acquire per sequence (Z windows). The acquisition of frames will only start after Z_OFFS frames have been skipped after the Z window is opened.
  • Page 49 2.13 Z_WIN_DIM_EXT Name Z_SIZE_MSB Z_SIZE_MSB Z_SIZE_MSB Z_SIZE_MSB Z_SIZE_MSB Z_SIZE_MSB Z_SIZE_MSB Z_SIZE_MSB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Z_OFFS_MSB Z_OFFS_MSB Z_OFFS_MSB Z_OFFS_MSB Z_OFFS_MSB Z_OFFS_MSB Z_OFFS_MSB Z_OFFS_MSB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-25...
  • Page 50 Z_WIN_DIM_EXT The Axion-CL Z_SIZE_MSB R/W, Z_WIN_DIM_EXT[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Z_SIZE register by 8 more bits. Z_OFFS_MSB R/W, Z_WIN_DIM_EXT[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Z_OFFS register by 8 more bits. AXN-2-26 BitFlow, Inc. Version A.3...
  • Page 51 2.14 Y_INT_DEC Name Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Y_INT_DEC_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Y_INT_DEC_RST Y_INT_DEC_RST Y_INT_DEC_MODE Y_INT_DEC_MODE Version A.3 BitFlow, Inc. AXN-2-27...
  • Page 52 Y_INT_DEC The Axion-CL Y_INT_DEC_ R/W, Y_INT_DEC[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- COUNT When Y interrupt decimate mode is enable, the register determines the decimation amount. In other words, Y_INT_DEC_COUNT interrupts must occur before the board emits a real interrupt. Y_INT_DEC_RST R/W, Y_INT_DEC[29..28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy-...
  • Page 53 2.15 Y_WIN_CON Name Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_SEL Y_CLOSE_TRIG_SEL Y_CLOSE_TRIG_SEL Y_CLOSE_TRIG_SEL Y_CLOSE Y_CLOSE Y_CLOSE Y_CLOSE Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_SEL Y_OPEN_TRIG_SEL Y_OPEN_TRIG_SEL Y_OPEN_TRIG_SEL Y_OPEN Y_OPEN Y_OPEN Y_OPEN Y_SYNC Y_SYNC Y_SYNC Y_SYNC Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-29...
  • Page 54 Y_WIN_CON The Axion-CL Y_CLOSE_TRIG_ R/W, Y_WIN_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- FUNC This register determines which trigger change (if any) will end the Y window. Y_CLOSE_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger 2 (0010b)
  • Page 55 (starts the frame) lines are acquired until either the trigger goes low, or Y_SIZE lines have been acquired (i.e. the maximum frame size has been reached). Y_OPEN_TRIG_ R/W, Y_WIN_CON[15..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- FUNC ton-CXP This register determines which trigger change (if any) will start Y window.
  • Page 56 Y window, then starts the setup of the X window. Y_SYNC R/W, Y_WIN_CON[27..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This field enforces the data-synchronization of streaming video to the acquisition engine for each individual line in the y window. The following table explains this field.
  • Page 57 2.16 Y_WIN_DIM Name Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Version A.3 BitFlow, Inc. AXN-2-33...
  • Page 58 Y_WIN_DIM The Axion-CL Y_SIZE R/W, Y_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Number of lines per frame (Y window) to acquire. This number is only acquired after the Y window is opened and after Y_OFFS lines have been skipped. Y_OFFS R/W, Y_WIN_DIM[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy-...
  • Page 59 2.17 Y_WIN_DIM_EXT Name Y_SIZE_MSB Y_SIZE_MSB Y_SIZE_MSB Y_SIZE_MSB Y_SIZE_MSB Y_SIZE_MSB Y_SIZE_MSB Y_SIZE_MSB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Y_OFFS_MSB Y_OFFS_MSB Y_OFFS_MSB Y_OFFS_MSB Y_OFFS_MSB Y_OFFS_MSB Y_OFFS_MSB Y_OFFS_MSB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-35...
  • Page 60 Y_WIN_DIM_EXT The Axion-CL Y_SIZE_MSB R/W, Y_WIN_DIM_EXT[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Y_SIZE register by 8 more bits. Y_OFFS_MSB R/W,Y_WIN_DIM_EXT[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the Y_OFFS register by 8 more bits. AXN-2-36 BitFlow, Inc. Version A.3...
  • Page 61 2.18 X_WIN_DIM Name X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS Version A.3 BitFlow, Inc. AXN-2-37...
  • Page 62 X_WIN_DIM The Axion-CL X_SIZE R/W, X_WIN_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Number of 16-byte words to acquired per line (X window). This number is only acquired after the X window is opened and after X_OFFS words have been skipped. X_OFFS R/W, X_WIN_DIM[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy-...
  • Page 63 2.19 X_WIN_DIM_EXT Name X_SIZE_MSB X_SIZE_MSB X_SIZE_MSB X_SIZE_MSB X_SIZE_MSB X_SIZE_MSB X_SIZE_MSB X_SIZE_MSB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved X_OFFS_MSB X_OFFS_MSB X_OFFS_MSB X_OFFS_MSB X_OFFS_MSB X_OFFS_MSB X_OFFS_MSB X_OFFS_MSB X_SHIFT X_SHIFT X_SHIFT X_SHIFT X_SHIFT X_SHIFT_DIR Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-39...
  • Page 64 X_WIN_DIM_EXT The Axion-CL X_SIZE_MSB R/W, X_WIN_DIM_EXT[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the X_SIZE register by 8 more bits. X_OFFS_MSB R/W,X_WIN_DIM_EXT[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Extends the X_OFFS register by 8 more bits. X_SHIFT R/W,X_WIN_DIM_EXT[24..18], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP,...
  • Page 65 V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT Reserved Reserved Reserved Reserved V_ACQ_COUNT_CLR_MODE V_ACQ_COUNT_CLR_MODE V_ACQ_COUNT_UPD_MODE V_ACQ_COUNT_UPD_MODE Note: The V_ACQUIRED register is not currently implemented Version A.3 BitFlow, Inc. AXN-2-41...
  • Page 66 V_ACQUIRED The Axion-CL V_ACQ_COUNT R/W, V_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of volumes (frame sequence) acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register V_ACQ_COUNT_CLEAR_MODE.
  • Page 67 2.21 Z_ACQUIRED Name Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Reserved Reserved Reserved Reserved Z_ACQ_COUNT_CLR_MODE Z_ACQ_COUNT_CLR_MODE Z_ACQ_COUNT_UPD_MODE Z_ACQ_COUNT_UPD_MODE Version A.3 BitFlow, Inc. AXN-2-43...
  • Page 68 Z_ACQUIRED The Axion-CL Z_ACQ_COUNT R/W, Z_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of frames acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register Z_ ACQ_COUNT_CLEAR_MODE.
  • Page 69 2.22 Y_ACQUIRED Name Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Reserved Reserved Reserved Reserved Y_ACQ_COUNT_CLR_MODE Y_ACQ_COUNT_CLR_MODE Y_ACQ_COUNT_UPD_MODE Y_ACQ_COUNT_UPD_MODE Version A.3 BitFlow, Inc. AXN-2-45...
  • Page 70 Y_ACQUIRED The Axion-CL Y_ACQ_COUNT R/W, Y_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of lines acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register Y_ ACQ_COUNT_CLEAR_MODE.
  • Page 71 2.23 X_ACQUIRED Name X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT Reserved Reserved Reserved Reserved X_ACQ_COUNT_CLR_MODE X_ACQ_COUNT_CLR_MODE X_ACQ_COUNT_UPD_MODE X_ACQ_COUNT_UPD_MODE Version A.3 BitFlow, Inc. AXN-2-47...
  • Page 72 X_ACQUIRED The Axion-CL X_ACQ_COUNT R/W, X_ACQUIRED[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP Returns the total number of 16-byte words acquired since the last reset of this regis- ter. The behavior of this register when it reaches it maximum value depends on the register X_ACQ_COUNT_CLEAR_MODE.
  • Page 73 2.24 CON489 Name INT_Y_ACQUIRED INT_X_ACQUIRED INT_Z_ACQUIRED Reserved INT_ENC_B INT_ENC_A INT_TRIG INT_Y_START INT_X_START INT_Z_START Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_BM_ERROR INT_AE_LOSS_OF_SYNC INT_PCIE_PKT_DROPPED INT_Y_ACQUIRED_LEGACY Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-49...
  • Page 74 CON489 The Axion-CL INT_Y_ R/W, CON489[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED Y window closed interrupt. INT_X_ R/W, CON489[1], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED X window closed interrupt. INT_Z_ R/W, CON489[2], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED Z window closed interrupt..
  • Page 75 The StreamSync Acquisition Engine CON489 INT_AE_LOSS_ R/W, CON489[27], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OF_SYNC Loss of sync in the Acquisition Engine interrupt. INT_PCIE_PKT_ R/W, CON489[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP DROPPED PCIe packet dropped interrupt. INT_Y_ R/W, CON489[29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP...
  • Page 76 CON490 The Axion-CL 2.25 CON490 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_ANY ENINT_ALL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-2-52 BitFlow, Inc.
  • Page 77 The StreamSync Acquisition Engine CON490 INT_ANY RO, CON490[7], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP T is at least on active interrupt on the board. ENINT_ALL R/W, CON490[8], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Set to 1 to enable board interrupts. Version A.3 BitFlow, Inc.
  • Page 78 CON548 The Axion-CL 2.26 CON548 Name INT_Y_ACQUIRED_M INT_X_ACQUIRED_M INT_Z_ACQUIRED_M Reserved INT_ENC_B_M INT_ENC_A_M INT_TRIG_M INT_Y_START_M INT_X_START_M INT_Z_START_M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_BM_ERROR_M INT_AE_LOSS_OF_SYNC_M INT_PCIE_PKT_DROPPED_M INT_Y_ACQUIRED_LEGACY_M Reserved Reserved AXN-2-54 BitFlow, Inc.
  • Page 79 R/W, CON548[6], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP INT_TRIG mask. INT_Y_START_M R/W, CON548[7], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP INT_Y_START mask. INT_X_START_M R/W, CON548[8], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP INT_X_START mask. INT_Z_START_M R/W, CON548[9], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP INT_Z_START mask. INT_BM_...
  • Page 80 CON548 The Axion-CL INT_AE_LOSS_ R/W, CON548[27], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OF_SYNC_M INT_AE_LOSS_OF_SYNC mask. INT_PCIE_PKT_ R/W, CON548[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP DROPPED_M INT_PCIE_PKT_DROPPED mask. INT_Y_ R/W, CON548[29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED_ LEGACY_M INT_Y_ACQUIRED_LEGACY mask. AXN-2-56 BitFlow, Inc.
  • Page 81 2.27 CON549 Name INT_Y_ACQUIRED_WP INT_X_ACQUIRED_WP INT_Z_ACQUIRED_WP Reserved INT_ENC_B_WP INT_ENC_A_WP INT_TRIG_WP INT_Y_START_WP INT_X_START_WP INT_Z_START_WP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_BM_ERROR_WP INT_AE_LOSS_OF_SYNC_WP INT_PCIE_PKT_DROPPED_WP INT_Y_ACQUIRED_LEGACY_WP Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-57...
  • Page 82 CON549 The Axion-CL INT_Y_ R/W, CON549[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED_WP INT_Y_ACQUIRED write protect. INT_X_ R/W, CON549[1], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED_WP INT_X_ACQUIRED write protect. INT_Z_ R/W, CON549[2], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED_WP INT_Z_ACQUIRED write protect. INT_ENC_B_WP R/W, CON549[4], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP INT_ENC_B write protect.
  • Page 83 The StreamSync Acquisition Engine CON549 INT_AE_LOSS_ R/W, CON549[27], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OF_SYNC_WP INT_AE_LOSS_OF_SYNC write protect. INT_PCIE_PKT_ R/W, CON549[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP DROPPED_WP INT_PCIE_PKT_DROPPED write protect. INT_Y_ R/W, CON549[29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ACQUIRED_ LEGACY_WP INT_Y_ACQUIRED_LEGACY write protect.
  • Page 84 SF_DIM The Axion-CL 2.28 SF_DIM Name SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH AXN-2-60 BitFlow, Inc.
  • Page 85 The StreamSync Acquisition Engine SF_DIM SF_HEIGHT R/W, SF_DIM[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP The height (in lines) of the Synthetic Frame (internally generated synthetic image). SF_WIDTH R/W, SF_DIM[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The width of the Synthetic frame. Units are 16 byte chunks.
  • Page 86 SF_CON The Axion-CL 2.29 SF_CON Name SF_RUN_LEVEL SF_RUN_LEVEL SF_STATE SF_STATE SF_MODE SF_MODE Reserved SF_LINE_SCAN SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_X_GAP SF_X_GAP SF_X_GAP SF_X_GAP SF_Y_GAP SF_Y_GAP SF_Y_GAP SF_Y_GAP SF_Z_GAP SF_Z_GAP SF_Z_GAP SF_Z_GAP SF_INC_X SF_INC_Y SF_INC_Z Reserved AXN-2-62 BitFlow, Inc.
  • Page 87 The StreamSync Acquisition Engine SF_CON SF_RUN_LEVEL R/W, SF_CON[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP The register controls the Synthetic Frame generator. SF_RUN_LEVEL Meaning/Command Idle Abort Reserved SF_STATE RO, SF_CON[3..2], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This register can be used to check the current state of the Synthetic Frame generator.
  • Page 88 SF_CON The Axion-CL SF_Y_GAP R/W, SF_CON[23..20], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The number of lines between frames. SF_Z_GAP R/W, SF_CON[27..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The number of frames between volumes. SF_INC_X R/W, SF_CON[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP The amount to increment the grey scale output value every pixel.
  • Page 89 2.30 IMAGE_STAMP_CTRL Name IS_ALL_LINES Reserved Reserved Reserved IS_MODE IS_MODE IS_MODE IS_MODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-2-65...
  • Page 90 IMAGE_STAMP_CTRL The Axion-CL IS_ALL_LINES R/W, IMAGE_STAMP_CTRL[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Set this bit to 1 to have image stamping on every line in the frame. If it is 0, then just the first line in the frame will be stamped.
  • Page 91: The Streamsync Buffer Manager

    BitFlow frame grabbers. The StreamSync system is a start-from-scratch complete redesign of the acquisition and DMA parts of a frame grabber. BitFlow used its years of experience in this area to design a next generation, super efficient capture system.
  • Page 92: The Buffer Manager Details Axn-3-2

    The Buffer Manager Details The Axion-CL 3.2 The Buffer Manager Details The Buffer Manager interacts with a remote, software managed, set of Scatter Gather DMA lists. A single Scatter Gather DMA list is called a QTab. A QTab is made of indi- vidual DMA instructions (descriptors) called Quads.
  • Page 93 3.3 CON485 Register Name FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO Version A.3 BitFlow, Inc. AXN-3-3...
  • Page 94 CON485 Register The Axion-CL FIRST_QUAD_ R/W, CON28[31..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP PTR_LO This is the low word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. AXN-3-4 BitFlow, Inc. Version A.3...
  • Page 95 3.4 CON486 Register Name FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI Version A.3 BitFlow, Inc. AXN-3-5...
  • Page 96 CON486 Register The Axion-CL FIRST_QUAD_ R/W, CON29[31..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP PTR_HI This is the high word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. AXN-3-6 BitFlow, Inc. Version A.3...
  • Page 97: Buf_Mgr_Con Axn-3-7

    3.5 BUF_MGR_CON Name BM_RUN_LEVEL BM_RUN_LEVEL BM_RUN_LEVEL BM_RUN_LEVEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CURR_FETCH_SIZE CURR_FETCH_SIZE CURR_FETCH_SIZE CURR_FETCH_SIZE MAX_FETCH_SIZE MAX_FETCH_SIZE MAX_FETCH_SIZE MAX_FETCH_SIZE Version A.3 BitFlow, Inc. AXN-3-7...
  • Page 98 BUF_MGR_CON The Axion-CL BM_RUN_LEVEL R/W, BUF_MGR_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This is the main control for starting/stopping the Buffer Manager. BM_RUN_LEVEL Meaning 0 (0000b) Idle - The Buffer Manager is not moving data 1 (0001b) Run - The Buffer Manger will start to move data...
  • Page 99: Buf_Mgr_Timeout Axn-3-9

    3.6 BUF_MGR_TIMEOUT Name QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DISABLE_TIMEOUT Version A.3 BitFlow, Inc. AXN-3-9...
  • Page 100 BUF_MGR_TIMEOUT The Axion-CL QUAD_ R/W, BUF_MGR_TIMEOUT[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- COMPLETE_ FXP, Cyton-CXP TIMEOUT The maximum amount of time to wait for a Quad completion. Units are 4 nanosec- onds. Writable only when BM_STATE is Idle. DISABLE_ R/W, BUF_MGR_TIMEOUT[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP,...
  • Page 101: Board_Config Axn-3-11

    The StreamSync Buffer Manager BOARD_CONFIG 3.7 BOARD_CONFIG Name Reserved Reserved CPLD_MODE CPLD_MODE CPLD_MODE CPLD_MODE Reserved Reserved Reserved Reserved CPLD_STRAP CPLD_STRAP CPLD_STRAP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-3-11...
  • Page 102 BOARD_CONFIG The Axion-CL RO, BOARD_CONFIG[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP The current value of the on board switch SW1. CPLD_MODE RO, BOARD_CONFIG[7..4], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP The current value of switch S3. This switch controls the firmware bank that the FPGA boots from.
  • Page 103 3.8 PACKETS_SENT_STATUS Name NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP Version A.3 BitFlow, Inc. AXN-3-13...
  • Page 104: Packets_Sent_Status Axn-3-13

    PACKETS_SENT_STATUS The Axion-CL NUM_PACKETS_ RO, PACKETS_SENT_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- SENT on-FXP, Cyton-CXP The register indicates the number of PCIe packets that the Buffer Manager has sent across the PCIe bus. This register rolls over to 0 at 0xffff. NUM_PACKETS_ RO, PACKETS_SENT_STATUS[31..16], Aon-CXP, Axion-CL, Claxon-CXP, Clax-...
  • Page 105 3.9 QUADS_USED_STATUS Name NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-3-15...
  • Page 106: Quads_Used_Status Axn-3-15

    QUADS_USED_STATUS The Axion-CL NUM_QUADS_ RO, QUADS_USED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- USED FXP, Cyton-CXP This register indicates the number of Quads that have been “consumed” by the Buffer Manager. This register rolls over to 0 at 0xffff. AXN-3-16 BitFlow, Inc. Version A.3...
  • Page 107 3.10 QTABS_USED_STATUS Name NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-3-17...
  • Page 108: Qtabs_Used_Status Axn-3-17

    QTABS_USED_STATUS The Axion-CL NUM_QTABS_ RO, QTABS_USED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- USED FXP, Cyton-CXP This register indicates the number of QTabs that have been “consumed” by the Buffer Manager. This register rolls over to 0 at 0xffff. AXN-3-18 BitFlow, Inc. Version A.3...
  • Page 109 3.11 PKT_STAT Name PKT_STATE PKT_STATE Reserved Reserved Reserved Reserved Reserved Reserved NO_QUAD_AVAIL VIDEO_DROPPED QUAD_DROPPED Reserved NEW_FRAME_RESYNC RD_ON_EMPTY WR_ON_FULL Reserved PKT_FLUSH_ENABLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-3-19...
  • Page 110 PKT_STAT The Axion-CL PKT_STATE RO, PKT_STAT[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Current state of the DMA engine. PKT_STATE Meaning 0 (00b) PKT_SYNC - Synchronizing DMA descriptors with video 1 (01b) PKT_HDR - Generating PCIe header 2 (10b)~ PKT_DAT - Placing data in PCIe packet...
  • Page 111 The StreamSync Buffer Manager PKT_STAT PKT_FLUSH_ R/W, PKT_STAT[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP ENABLE DMA tries to send as large as packets as possible for efficiency. Data is collected in a FIFO until certain size rules are met. However, sometimes no more data will be com- ing (end of frame).
  • Page 112: Quads_Loaded_Status Axn-3-22

    QUADS_LOADED_STATUS The Axion-CL 3.12 QUADS_LOADED_STATUS Name NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-3-22 BitFlow, Inc.
  • Page 113 The StreamSync Buffer Manager QUADS_LOADED_STATUS NUM_QUADS_ RO, QUADS_LOADED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- LOADED on-FXP, Cyton-CXP This register indicates the number of Quads that have been loaded by the Buffer Manager. This register will roll over to 0 at 0xffff. Version A.3 BitFlow, Inc.
  • Page 114: Qtabs_Loaded_Status Axn-3-24

    QTABS_LOADED_STATUS The Axion-CL 3.13 QTABS_LOADED_STATUS Name NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-3-24 BitFlow, Inc.
  • Page 115 The StreamSync Buffer Manager QTABS_LOADED_STATUS NUM_QTABS_ RO, QTABS_LOADED_STATUS[15..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- LOADED on-FXP, Cyton-CXP This register indicates the number of QTabs that have been loaded by the Buffer Man- ager. This register will roll over to 0 at 0xffff.
  • Page 116: Buf_Mgr_Status Axn-3-26

    BUF_MGR_STATUS The Axion-CL 3.14 BUF_MGR_STATUS Name BM_STATE BM_STATE BM_STATE Reserved CPL_STATUS CPL_STATUS CPL_STATUS Reserved BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED Reserved Reserved Reserved Reserved DST_ADDR_ERROR_LSB NEXT_ADDR_ERROR_LSB SIZE_ERROR_LSB SIZE_ERROR_MSB Reserved Reserved Reserved Reserved CPL_ERROR QUAD_NUM_MISMATCH QUAD_FIFO_OVERFLOW QUAD_TIMEOUT_DETECTED AXN-3-26 BitFlow, Inc.
  • Page 117 The StreamSync Buffer Manager BUF_MGR_STATUS BM_STATE RO, BUF_MGR_STATUS[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Returns the current state of the Buffer Manager. BM_STATE Meaning 0 (0000b) Idle - The buffer manager is not current active 1 (0001b) Active - The buffer manager is currently DMAing...
  • Page 118 BUF_MGR_STATUS The Axion-CL SIZE_ERROR_ RO, BUF_MGR_STATUS[23], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Quad size is > 4K. CPL_ERROR RO, BUF_MGR_STATUS[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Error code received as a result of fetching a Quad. Check CPL_STATUS. QUAD_NUM_ RO, BUF_MGR_STATUS[29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP,...
  • Page 119: Pkt_Con Axn-3-29

    3.15 PKT_CON Name MAX_PAYLOAD_USER MAX_PAYLOAD_USER MAX_PAYLOAD_USER MAX_PAYLOAD_USER MAX_PAYLOAD_PCIE MAX_PAYLOAD_PCIE MAX_PAYLOAD_PCIE MAX_PAYLOAD_PCIE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DISABLE_PKT_FLUSH_TIMER DISABLE_PKT_GEN Version A.3 BitFlow, Inc. AXN-3-29...
  • Page 120 PKT_CON The Axion-CL MAX_ RO, PKT_CON[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP PAYLOAD_USER This is the maximum sized PCIe packet that will be generated by the Buffer Manager. Writes to this register of values higher than MAX_PAYLOAD_PCIE will be ignored. The coding is shown in the following table.
  • Page 121: Timing Sequencer

    This section covers the Timing Sequencer (TS) which is available on the Aon, Axion, Claxon and Cyton. The TS is a sophisticated programmable pulse generator. The TS takes the place of the NTG on previous models of BitFlow frame grabbers. The TS improves on the NTG in the following ways: Driven by a “nice”...
  • Page 122 Introduction The Axion-CL Building Pulses The TS was designed to support a wide range of pulse lengths. At the same time, the TS was design to be able to create pulses of very accurate duration. The solution to these two opposing problems is to build up a pulse of a desired length via multiple sub-pulses, each sub-pulse programmed with a different granularity.
  • Page 123 This would be done by setting the Immediate Jump trigger to the End of Frame signal, and the TS_IDX_JUMP to the location of the first pulse that is waiting for the Start of Frame. Version A.3 BitFlow, Inc. AXN-4-3...
  • Page 124 TS_CONTROL The Axion-CL 4.2 TS_CONTROL Name TS_RUN_LEVEL TS_RUN_LEVEL TS_RUN_LEVEL Reserved TS_CT0_DEFAULT_STATE TS_CT1_DEFAULT_STATE TS_CT2_DEFAULT_STATE TS_CT3_DEFAULT_STATE TS_IMMDT_JUMP_SEL TS_IMMDT_JUMP_SEL TS_IMMDT_JUMP_SEL TS_IMMDT_JUMP_SEL TS_IMMDT_JUMP_COND TS_IMMDT_JUMP_EN Reserved Reserved TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_TRIG_SEL_1 TS_TRIG_SEL_1 TS_TRIG_SEL_1 TS_TRIG_SEL_1 TS_TRIG_SEL_0 TS_TRIG_SEL_0 TS_TRIG_SEL_0 TS_TRIG_SEL_0 AXN-4-4 BitFlow, Inc.
  • Page 125 Timing Sequencer TS_CONTROL TS_RUN_LEVEL R/W, TS_CONTROL[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP These bits control the operation of the TS. These bits are used to start and stop the sequencer. They can also be used to program the table to jump to a new section.
  • Page 126 TS_CONTROL The Axion-CL TS_IMMDT_ R/W, TS_CONTROL[8..11], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- JUMP_SEL ton-CXP These bits select the source of the Immediate Jump function. TS_IMMDT_ Meaning JUMP_SEL 0 (0000b) Selected trigger (VGFx_TRIG_SEL) 1 (0001b) Selected encoder A (VFGx_ENCA_SEL) 2 (0010b) Selected encoder B (VFGx_ENCB_SEL)
  • Page 127 Timing Sequencer TS_CONTROL TS_IMMDT_ R/W, TS_CONTROL[12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- JUMP_EN Set this bit to 1 to enable Immediate Jump function. TS_IDX_JUMP R/W, TS_CONTROL[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP This is the entry that the table will start from when the TS_RUN_LEVEL register is set to Run.
  • Page 128 TS_CONTROL The Axion-CL TS_TRIG_SEL_0 R/W, TS_CONTROL[31..28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP These bits select the source of the TS trigger 0. TS_TRIG_ Meaning SEL_0 0 (0000b) Selected trigger (VGFx_TRIG_SEL) 1 (0001b) Selected encoder A (VFGx_ENCA_SEL) 2 (0010b) Selected encoder B (VFGx_ENCB_SEL)
  • Page 129 4.3 TS_TABLE_CONTROL Name TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-4-9...
  • Page 130 TS_TABLE_CONTROL The Axion-CL TS_IDX_ACCESS R/W, TS_TABLE_CONTROL[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP Indirect access to the TS table. Set this bitfield to the index value that you wish to modify. Access is done through via TS_TABLE_ENTRY register. AXN-4-10 BitFlow, Inc.
  • Page 131 4.4 TS_TABLE_ENTRY Name TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT Reserved Reserved TS_RESOLUTION TS_RESOLUTION TS_STATE_CT0 TS_STATE_CT1 TS_STATE_CT2 TS_STATE_CT3 TS_TRIG_SEL_SEL TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_CONDITION TS_CONDITION TS_CONDITION TS_TERMINATE TS_END_OF_SEQUENCE Version A.3 BitFlow, Inc. AXN-4-11...
  • Page 132: Ts_Next

    R/W, TS_TABLE_ENTRY[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Index of next pulse. Only relevant if TS_TERMINATE = 0. TS_RESOLUTION R/W, TS_TABLE_ENTRY[11..10], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP The time units of this pulse. The length of this pulse is set in the register TS_COUNT.
  • Page 133: Ts_Trig_Sel_Sel

    Timing Sequencer TS_TABLE_ENTRY TS_TRIG_SEL_ R/W, TS_TABLE_ENTRY[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP If this pulse is triggered, this bit sets which trigger will be used. TS_TRIG_SEL_SEL Meaning The trigger selected by TS_TRIG_SEL_0 The trigger selected by TS_TRIG_SEL_1 TS_COUNT R/W, TS_TABLE_ENTRY[26..17], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP The length of this pulse.
  • Page 134 TS_TABLE_ENTRY The Axion-CL TS_END_OF_ R/W, TS_TABLE_ENTRY[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, SEQUENCE Cyton-CXP If this bit is set to 1 and TS_RUN_LEVEL is set to Jump, the TS will jump to the index set in the TS_INDX_JUMP bitfield after the current pulse is output. This bit allows for syn- chronous switching between one section of the table and another section.
  • Page 135 4.5 ATS_CONTROL Name ATS_RUN_LEVEL ATS_RUN_LEVEL ATS_RUN_LEVEL Reserved ATS_CT0_DEFAULT_STATE ATS_CT1_DEFAULT_STATE ATS_CT2_DEFAULT_STATE ATS_CT3_DEFAULT_STATE ATS_IMMDT_JUMP_SEL ATS_IMMDT_JUMP_SEL ATS_IMMDT_JUMP_SEL ATS_IMMDT_JUMP_SEL ATS_IMMDT_JUMP_COND ATS_IMMDT_JUMP_EN Reserved Reserved ATS_IDX_JUMP ATS_IDX_JUMP ATS_IDX_JUMP ATS_IDX_JUMP ATS_IDX_JUMP ATS_IDX_JUMP ATS_IDX_JUMP ATS_IDX_JUMP Reserved Reserved Reserved Reserved ATS_TRIG_SEL ATS_TRIG_SEL ATS_TRIG_SEL ATS_TRIG_SEL Version A.3 BitFlow, Inc. AXN-4-15...
  • Page 136 ATS_CONTROL The Axion-CL ATS_RUN_LEVEL R/W, ATS_CONTROL[2..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- ton-CXP These bits control the operation of the ATS. These bits are used to start and stop the sequencer. They can also be used to program the table to jump to a new section.
  • Page 137 14 (1110b) Reserved 15 (1111b) Reserved Note: * FVAL and LVAL triggers are only support on the Axion models ATS_IMMDT_ R/W, ATS_CONTROL[12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- JUMP_COND ton-CXP This controls the polarity of the Immediate Jump function. ATS_IMMDT_JUMP_ Meaning...
  • Page 138 ATS_CONTROL The Axion-CL ATS_IMMDT_ R/W, ATS_CONTROL[12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cy- JUMP_EN ton-CXP Set this bit to 1 to enable Immediate Jump function. ATS_IDX_JUMP R/W, ATS_CONTROL[23..16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This is the entry that the table will start from when the ATS_RUN_LEVEL register is set to Run.
  • Page 139 4.6 ATS_TABLE_CONTROL Name ATS_IDX_ACCESS ATS_IDX_ACCESS ATS_IDX_ACCESS ATS_IDX_ACCESS ATS_IDX_ACCESS ATS_IDX_ACCESS ATS_IDX_ACCESS ATS_IDX_ACCESS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-4-19...
  • Page 140 ATS_TABLE_CONTROL The Axion-CL ATS_IDX_ R/W, ATS_TABLE_CONTROL[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- ACCESS FXP, Cyton-CXP Indirect access to the TS table. Set this bitfield to the index value that you wish to modify. Access is done through via TS_TABLE_ENTRY register. AXN-4-20 BitFlow, Inc.
  • Page 141 4.7 ATS_TABLE_ENTRY Name ATS_NEXT ATS_NEXT ATS_NEXT ATS_NEXT ATS_NEXT ATS_NEXT ATS_NEXT ATS_NEXT Reserved Reserved ATS_RESOLUTION ATS_RESOLUTION ATS_STATE_CT0 ATS_STATE_CT1 ATS_STATE_CT2 ATS_STATE_CT3 ATS_TRIG_SEL_SEL ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_COUNT ATS_CONDITION ATS_CONDITION ATS_CONDITION ATS_TERMINATE ATS_END_OF_SEQUENCE Version A.3 BitFlow, Inc. AXN-4-21...
  • Page 142 ATS_TABLE_ENTRY The Axion-CL ATS_NEXT R/W, ATS_TABLE_ENTRY[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Index of next pulse. Only follow if ATS_TERMINATE = 0. ATS_ R/W, ATS_TABLE_ENTRY[11..10], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- RESOLUTION FXP, Cyton-CXP The time units of this pulse. The length of this pulse is set in the register ATS_COUNT.
  • Page 143 Timing Sequencer ATS_TABLE_ENTRY ATS_TRIG_SEL_ R/W, ATS_TABLE_ENTRY[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP If this pulse is triggered, this bit sets which trigger will be used. ATS_TRIG_SEL_SEL Meaning The trigger selected by ATS_TRIG_SEL_0 The trigger selected by ATS_TRIG_SEL_1 ATS_COUNT R/W, ATS_TABLE_ENTRY[26..17], Aon-CXP, Axion-CL, Claxon-CXP, Claxon- FXP, Cyton-CXP The length of this pulse.
  • Page 144 ATS_TABLE_ENTRY The Axion-CL ATS_END_OF_ R/W, ATS_TABLE_ENTRY[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, SEQUENCE Cyton-CXP If this bit is set to 1 and ATS_RUN_LEVEL is set to Jump, the ATS will jump to the index set in the ATS_INDX_JUMP bitfield after the current pulse is output. This bit allows for synchronous switching between one section of the table and another section.
  • Page 145 RD_XXX bit. 5.1.2 I/O Between Virtual Frame Grabbers Because BitFlow’s frame grabber can acquire from more than one camera, it has always been a contention between the desire to let each camera be independent, for example, each with its own trigger, and for them to be synchronized, i.e. all cameras using one trigger.
  • Page 146 Introduction The Axion-CL What this means is that one of the sources, the master VFG’s trigger can be the trigger for all of the VFGs. Thus whatever signal is triggering VFG0, can also trigger all the other VFGs on the board. Of course, each VFG can choose to use the master VFG’s trigger, or choose amongst its own sources.
  • Page 147 Selector Internal Signal B For Internal Signal Internal Internal Circuit M Circuit N External Selector for Output X External Selector for Output Y External Signal X External Signal Y Figure 5-1 Conceptual I/O System Routing Version A.3 BitFlow, Inc. AXN-5-3...
  • Page 148 Note: The signals BOX_IN_XXX are available via an external I/O Box, the BitFlow BitBox, which can be mounted on an external rail system. Contact BitFlow for more information on the BitBox. Note: Each VFG has a copy of the circuit shown in Figure 5-2. This is why the outputs do not specify the VFG number (e.g.
  • Page 149 Figure 5-4 shows the details of the encoder handler block that is part of Figure 5-3. The Filter is used to remove unwanted noise on the incoming signal. The filter is pro- grammable and it will “swallow” a pulse shorter than the programmed size. Version A.3 BitFlow, Inc. AXN-5-5...
  • Page 150 Internal Signals The Axion-CL VFGx_ENCDIV_SEL VFG0_ENCDIV_SEL VFG0_ENCQ_SEL Encoder Handler VFGx_ENCQ_SEL SEL_ENCB ENCB_FILTER VFGx_ENCB_SEL 64:1 Filter SEL_ENCA ENCA_FILTER VFGx_ENCA_SEL 64:1 Filter SEL_TRIG TRIG_FILTER VFGx_TRIG_SEL 64:1 Filter Timing Engine Sequen- Select Figure 5-3 Internal Signal Routing AXN-5-6 BitFlow, Inc. Version A.3...
  • Page 151 The Aon, Axion, Claxon and Cyton I/O System Internal Signals SEL_ENCDIV SEL_ENCDIV_INPUT TRG_DLY_TRIG_SEL Encoder VFGx_ENCDIV_SEL Divider Multiplier VFGx_TRIG_SEL VFG0_ENCDIV_SEL SCAN_STEP_TRIG SEL_ENCQ Quad Enc Out VFGx_ENCA_SEL Qaudrature Encoder VFGx_ENCQ_SEL Scan Step Out VFGx_ENCB_SEL Decoder VFG0_ENCQ_SEL Figure 5-4 Encoder Handler Version A.3 BitFlow, Inc. AXN-5-7...
  • Page 152 Output Signal Selection The Axion-CL 5.5 Output Signal Selection There are four dynamic output signals for each VFG: CC1, CC2, CC3 and CC4. These dynamic signals can be driven by a variety of sources as shown in Figure 5-5. VFGx_TRIG_SEL...
  • Page 153 Note: The signals VFGx_CC1 to VFGx_CC3 can also be routed to the BitBox, which is an externally mountable I/O Box. VFGx_CC1 VFGx_CXP_TRIG VFGx CXP Uplink VFGx_CC2 VFGx_CC2_TTL VFGx_CC3 VFGx_CC3_TTL Main I/O Connector VFGx_CC4 VFGx_CC4_TTL VFGx_CC3_DIF Figure 5-6 Output Signal Routing Version A.3 BitFlow, Inc. AXN-5-9...
  • Page 154 The Axion-CL 5.7 BitBox Output Signal Routing The BitFlow BitBox has 3 banks of 12 outputs. One bank is TTL, one bank is differen- tial and one bank is a mix of Optocoupled and Open Collector outputs. Each of the 36 outputs can be set to a static output level, or controlled by a dynamic source (waveform).
  • Page 155 The I/O System Registers Introduction The I/O System Registers Chapter 6 6.1 Introduction The registers documented in this section are used to control the I/O system on the Aon, Axion, Claxon and Cyton. Version A.3 BitFlow, Inc. AXN-6-1...
  • Page 156 CON60 The Axion-CL 6.2 CON60 Name RD_BOX_IN_TTL_0 RD_BOX_IN_TTL_1 RD_BOX_IN_TTL_2 RD_BOX_IN_TTL_3 RD_BOX_IN_TTL_4 RD_BOX_IN_TTL_5 RD_BOX_IN_TTL_6 RD_BOX_IN_TTL_7 RD_BOX_IN_TTL_8 RD_BOX_IN_TTL_9 RD_BOX_IN_TTL_10 RD_BOX_IN_TTL_11 RD_BOX_IN_DIF_0 RD_BOX_IN_DIF_1 RD_BOX_IN_DIF_2 RD_BOX_IN_DIF_3 RD_BOX_IN_DIF_4 RD_BOX_IN_DIF_5 RD_BOX_IN_DIF_6 RD_BOX_IN_DIF_7 RD_BOX_IN_DIF_8 RD_BOX_IN_DIF_9 RD_BOX_IN_DIF_10 RD_BOX_IN_DIF_11 ENINT_CXP INT_CXP Reserved Reserved Reserved SW_TRIG SW_ENCA SW_ENCB AXN-6-2 BitFlow, Inc.
  • Page 157 The I/O System Registers CON60 RD_BOX_IN_ RO, CON60[11..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP TTL_X These bits reflect the real-time state of the 12 TTL inputs on the BitBox. RD_BOX_IN_ RO, CON60[23..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP DIF_X These bits reflect the real-time state of the 12 differential inputs on the BitBox.
  • Page 158 CON61 The Axion-CL 6.3 CON61 Name RD_BOX_IN_OPTO_0 RD_BOX_IN_OPTO_1 RD_BOX_IN_OPTO_2 RD_BOX_IN_OPTO_3 RD_BOX_IN_OPTO_4 RD_BOX_IN_OPTO_5 RD_BOX_IN_OPTO_6 RD_BOX_IN_OPTO_7 RD_BOX_IN_24V_0 RD_BOX_IN_24V_1 RD_BOX_IN_24V_2 RD_BOX_IN_24V_3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RD_CXP_TRIG_OUT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-6-4 BitFlow, Inc.
  • Page 159 The I/O System Registers CON61 RD_BOX_IN_ RO, CON61[7..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OPTO_X These bits reflect the real-time state of the eight Opto-Isolated inputs on the BitBox. RD_BOX_IN_ RO, CON61[11..8], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP 24V_X These bits reflect the real-time state of the four 24V inputs on the BitBox.
  • Page 160 CON62 The Axion-CL 6.4 CON62 Name RD_TRIG_TTL RD_TRIG_DIF RD_TRIG_VFG0 RD_SCAN_STEP RD_SW_TRIG RD_ENCA_TTL RD_ENCA_DIF RD_ENCA_VFG0 RD_ENCA_SW RD_ENCB_TTL RD_ENCB_DIF RD_ENCB_VFG0 RD_ENCB_SW RD_BUTTON Reserved DIV_RESET_DISABLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RD_CXP_TRIG_IN EN_TRIG EN_ENCA EN_ENCB Reserved RD_ENCB_SELECTED RD_ENCA_SELECTED RD_TRIG_SELECTED AXN-6-6 BitFlow, Inc.
  • Page 161 The I/O System Registers CON62 RD_TRIG_TTL RO, CON62[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of the VFG’s TTL trigger input. RD_TRIG_DIF RO, CON62[1], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of the VFG’s differential trigger input.
  • Page 162 CON62 The Axion-CL RD_ENCB_DIF RO, CON62[10], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of the VFG’s differential encoder B input. RD_ENCB_VFG0 RO, CON62[11], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit reflects the real-time state of VFG0’s selected encoder B signal.
  • Page 163 The I/O System Registers CON62 RD_ENCA_ RO, CON62[30], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED The bit reflects the real-time status of the VFG’s selected encoder A input. RD_TRIG_ RO, CON62[31], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED The bit reflects the real-time status of the VFG’s selected trigger input.
  • Page 164 CON63 The Axion-CL 6.5 CON63 Name SEL_TRIG SEL_TRIG SEL_TRIG SEL_TRIG SEL_TRIG SEL_TRIG SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCB SEL_ENCB SEL_ENCB SEL_ENCB SEL_ENCB SEL_ENCB SEL_CC1 SEL_CC1 SEL_CC1 SEL_CC1 SEL_CC2 SEL_CC2 SEL_CC2 SEL_CC2 Reserved Reserved SEL_LED SEL_LED SEL_LED SEL_LED AXN-6-10 BitFlow, Inc.
  • Page 165 The I/O System Registers CON63 SEL_TRIG R/W, CON63[5..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Selects the VFG’s trigger source. SEL_TRIG Source 0 (000000b) Forced low 1 (000001b) Forced high 2 (000010b) This VFG’s differential trigger VFGx_TRIGGER+/- 3 (000011b) This VFG’s TTL trigger VFGx_TRIGGER_TTL...
  • Page 166 40 to 51 BOX_IN_DIF_0 to BOX_IN_DIF_11 52 to 59 BOX_IN_OPTO_0 to BOX_IN_OPTO_7 61 to 63 BOX_IN_24V_0 to BOX_IN_24V_3 SEL_ENCB R/W, CON63[17..12], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Selects the source of encoder B. SEL_ENCB Source 0 (000000b) Forced low 1 (000001b)
  • Page 167 The I/O System Registers CON63 SEL_CC1 R/W, CON63[21..18], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Selects the source of CC1. SEL_CC1 Source 0 (0000b) Forced low 1 (0001b) Forced high 2 (0010b) CT0 (from TS) 3 (0011b) CT1 (from TS) 4 (0100b)
  • Page 168 14 (1110b) VFGx_ENCQ_SEL 15 (111b) CT0 (from ATS) SEL_LED R/W, CON63[31..28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Selects the source of the VFG’s green LED. The LED receives a 1/2 second pulse every time the selected event occurs. SEL_LED Source 0 (0000b)
  • Page 169 The I/O System Registers CON63 SEL_LED Source 12 (1100b) VFG0_NTG or VFG0_TS 13 (1101b) AQSTAT[1] 14 (1110b) Overstep, OVS 15 (1111b) Reserved Version A.3 BitFlow, Inc. AXN-6-15...
  • Page 170 CON64 The Axion-CL 6.6 CON64 Name SEL_CC3 SEL_CC3 SEL_CC3 SEL_CC3 SEL_CC4 SEL_CC4 SEL_CC4 SEL_CC4 Reserved Reserved Reserved Reserved Reserved TRIGPOL ENCA_POL ENCB_POL RD_CC1 RD_CC2 RD_CC3 RD_CC4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved LED_RED LED_ORANGE LED_GREEN LED_BLUE AXN-6-16 BitFlow, Inc.
  • Page 171 The I/O System Registers CON64 SEL_CC3 R/W, CON64[3..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Selects the source of CC3. SEL_CC3 Source 0 (0000b) Forced low 1 (0001b) Forced high 2 (0010b) CT0 (from TS) 3 (0011b) CT1 (from TS) 4 (0100b)
  • Page 172: Trigpol

    14 (1110b) VFGx_ENCQ_SEL 15 (111b) CT0 (from ATS) TRIGPOL R/W, CON64[13], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Selects the edge of the trigger signal that corresponds to its assertion. TRIGPOL Meaning Trigger asserted on rising edge Trigger asserted on falling edge...
  • Page 173: Rd_Cc1

    The I/O System Registers CON64 RD_CC1 RO, CON64[16], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Returns the current state of the CC1 output. RD_CC1 Meaning Output is low Output is high RD_CC2 RO, CON64[17], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Returns the current state of the CC2 output.
  • Page 174: Led_Red

    The Axion-CL LED_RED R/W, CON64[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP Setting this bit to 1 turns the red LED on. Setting this bit to 1 on any VFG turns the LED on. This bit must be set to 0 on all VFGs in order to turn this LED off.
  • Page 175 6.7 TRIG_OPTS Name TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER TRIG_FILTER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-6-21...
  • Page 176 The Axion-CL TRIG_FILTER RO, TRIG_OPTS[17..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The trigger circuit includes a programmable noise filter. The value of this register con- trols the size of the noise pulse that will be considered noise and will be filtered out.
  • Page 177 6.8 ENCA_OPTS Name ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER ENCA_FILTER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-6-23...
  • Page 178 The Axion-CL ENCA_FILTER RO, ENCA_OPTS[17..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The encoder A circuit includes a programmable noise filter. The value of this register controls the size of the noise pulse that will be considered noise and will be filtered out.
  • Page 179 6.9 ENCB_OPTS Name ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER ENCB_FILTER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-6-25...
  • Page 180 The Axion-CL ENCB_FILTER RO, ENCB_OPTS[17..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- The encoder B circuit includes a programmable noise filter. The value of this register controls the size of the noise pulse that will be considered noise and will be filtered out.
  • Page 181 6.10 BOX_OUT_DYN_SEL_SET_A Name BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_0 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_1 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_2 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 BOX_OUT_DYN_SEL_3 Version A.3 BitFlow, Inc. AXN-6-27...
  • Page 182 BOX_OUT_DYN_SEL_SET_A The Axion-CL BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_A[7..0], Aon-CXP, Axion-CL, Claxon-CXP, SEL_0 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_0, BOX_OUT_TTL_0 and BOX_OUT_OPTO_0. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
  • Page 183 The I/O System Registers BOX_OUT_DYN_SEL_SET_A BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_A[15..8], Aon-CXP, Axion-CL, Claxon-CXP, SEL_1 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_1, BOX_OUT_TTL_1 and BOX_OUT_OPTO_1. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
  • Page 184 BOX_OUT_DYN_SEL_SET_B The Axion-CL 6.11 BOX_OUT_DYN_SEL_SET_B Name BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_4 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_5 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_6 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 BOX_OUT_DYN_SEL_7 AXN-6-30 BitFlow, Inc.
  • Page 185 The I/O System Registers BOX_OUT_DYN_SEL_SET_B BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_B[7..0], Aon-CXP, Axion-CL, Claxon-CXP, SEL_4 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_4, BOX_OUT_TTL_4 and BOX_OUT_OPTO_4. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
  • Page 186 BOX_OUT_DYN_SEL_SET_C The Axion-CL 6.12 BOX_OUT_DYN_SEL_SET_C Name BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_8 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_9 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_10 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 BOX_OUT_DYN_SEL_11 AXN-6-32 BitFlow, Inc.
  • Page 187 The I/O System Registers BOX_OUT_DYN_SEL_SET_C BOX_OUT_DYN_ R/W, BOX_OUT_DYN_SEL_SET_C[7..0], Aon-CXP, Axion-CL, Claxon-CXP, SEL_8 Claxon-FXP, Cyton-CXP This register controls the dynamic source for the three BitBox output signals BOX_ OUT_DIFF_8, BOX_OUT_TTL_8 and BOX_OUT_OC_0. These three outputs always have the same dynamic source (they can individually be set to static high or low value).
  • Page 188 BOX_OUT_MODE_SET_A The Axion-CL 6.13 BOX_OUT_MODE_SET_A Name BOX_OUT_MODE_TTL_0 BOX_OUT_MODE_TTL_0 BOX_OUT_MODE_TTL_1 BOX_OUT_MODE_TTL_1 BOX_OUT_MODE_TTL_2 BOX_OUT_MODE_TTL_2 BOX_OUT_MODE_TTL_3 BOX_OUT_MODE_TTL_3 BOX_OUT_MODE_TTL_4 BOX_OUT_MODE_TTL_4 BOX_OUT_MODE_TTL_5 BOX_OUT_MODE_TTL_5 BOX_OUT_MODE_TTL_6 BOX_OUT_MODE_TTL_6 BOX_OUT_MODE_TTL_7 BOX_OUT_MODE_TTL_7 BOX_OUT_MODE_TTL_8 BOX_OUT_MODE_TTL_8 BOX_OUT_MODE_TTL_9 BOX_OUT_MODE_TTL_9 BOX_OUT_MODE_TTL_10 BOX_OUT_MODE_TTL_10 BOX_OUT_MODE_TTL_11 BOX_OUT_MODE_TTL_11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-6-34 BitFlow, Inc.
  • Page 189 The I/O System Registers BOX_OUT_MODE_SET_A BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_TTL_0 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_0. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_0 bitfield.
  • Page 190 BOX_OUT_MODE_SET_A The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[7..6], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_TTL_3 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_3. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_3 bitfield.
  • Page 191 The I/O System Registers BOX_OUT_MODE_SET_A BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[13..12], Aon-CXP, Axion-CL, Claxon-CXP, MODE_TTL_6 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_6. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_6 bitfield.
  • Page 192 BOX_OUT_MODE_SET_A The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_A[19..18], Aon-CXP, Axion-CL, Claxon-CXP, MODE_TTL_9 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_TTL_9. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_9 bitfield.
  • Page 193 6.14 BOX_OUT_MODE_SET_B Name BOX_OUT_MODE_DIFF_0 BOX_OUT_MODE_DIFF_0 BOX_OUT_MODE_DIFF_1 BOX_OUT_MODE_DIFF_1 BOX_OUT_MODE_DIFF_2 BOX_OUT_MODE_DIFF_2 BOX_OUT_MODE_DIFF_3 BOX_OUT_MODE_DIFF_3 BOX_OUT_MODE_DIFF_4 BOX_OUT_MODE_DIFF_4 BOX_OUT_MODE_DIFF_5 BOX_OUT_MODE_DIFF_5 BOX_OUT_MODE_DIFF_6 BOX_OUT_MODE_DIFF_6 BOX_OUT_MODE_DIFF_7 BOX_OUT_MODE_DIFF_7 BOX_OUT_MODE_DIFF_8 BOX_OUT_MODE_DIFF_8 BOX_OUT_MODE_DIFF_9 BOX_OUT_MODE_DIFF_9 BOX_OUT_MODE_DIFF_10 BOX_OUT_MODE_DIFF_10 BOX_OUT_MODE_DIFF_11 BOX_OUT_MODE_DIFF_11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-6-39...
  • Page 194 BOX_OUT_MODE_SET_B The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_DIFF_0 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_0. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_0 bitfield.
  • Page 195 The I/O System Registers BOX_OUT_MODE_SET_B BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[7..6], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_DIFF_3 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_3 . This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_d bitfield.
  • Page 196 BOX_OUT_MODE_SET_B The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[13..12], Aon-CXP, Axion-CL, Claxon-CXP, MODE_DIFF_6 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_6. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_6 bitfield.
  • Page 197 The I/O System Registers BOX_OUT_MODE_SET_B BOX_OUT_ R/W, BOX_OUT_MODE_SET_B[19..18], Aon-CXP, Axion-CL, Claxon-CXP, MODE_DIFF_9 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_DIFF_9. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_9bitfield.
  • Page 198 BOX_OUT_MODE_SET_C The Axion-CL 6.15 BOX_OUT_MODE_SET_C Name BOX_OUT_MODE_OPTO_0 BOX_OUT_MODE_OPTO_0 BOX_OUT_MODE_OPTO_1 BOX_OUT_MODE_OPTO_1 BOX_OUT_MODE_OPTO_2 BOX_OUT_MODE_OPTO_2 BOX_OUT_MODE_OPTO_3 BOX_OUT_MODE_OPTO_3 BOX_OUT_MODE_OPTO_4 BOX_OUT_MODE_OPTO_4 BOX_OUT_MODE_OPTO_5 BOX_OUT_MODE_OPTO_5 BOX_OUT_MODE_OPTO_6 BOX_OUT_MODE_OPTO_6 BOX_OUT_MODE_OPTO_7 BOX_OUT_MODE_OPTO_7 BOX_OUT_MODE_OC_0 BOX_OUT_MODE_OC_0 BOX_OUT_MODE_OC_1 BOX_OUT_MODE_OC_1 BOX_OUT_MODE_OC_2 BOX_OUT_MODE_OC_2 BOX_OUT_MODE_OC_3 BOX_OUT_MODE_OC_3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-6-44 BitFlow, Inc.
  • Page 199 The I/O System Registers BOX_OUT_MODE_SET_C BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[1..0], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_OPTO_0 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OPTO_0. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_0 bitfield.
  • Page 200 BOX_OUT_MODE_SET_C The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[7..6], Aon-CXP, Axion-CL, Claxon-CXP, Clax- MODE_OPTO_3 on-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OPTO_3. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_3 bitfield.
  • Page 201 The I/O System Registers BOX_OUT_MODE_SET_C BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[13..12], Aon-CXP, Axion-CL, Claxon-CXP, MODE_OPTO_6 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OPTO_6. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is controlled by the associated BOX_OUT_DYN_SEL_6 bitfield.
  • Page 202 BOX_OUT_MODE_SET_C The Axion-CL BOX_OUT_ R/W, BOX_OUT_MODE_SET_C[19..18], Aon-CXP, Axion-CL, Claxon-CXP, MODE_OC_1 Claxon-FXP, Cyton-CXP This bit controls the BitBox output BOX_OUT_MODE_OC_1. This bit controls whether this output is static (high or low) or dynamic. If the bit is dynamic, the source is con- trolled by the associated BOX_OUT_DYN_SEL_9 bitfield.
  • Page 203 Chapter 7 7.1 Introduction This section covers the encoder divider which supported on all of BitFlow’s modern frame grabber families. The purpose of Encoder Divider is to provide the ability to use an encoder running at one rate to drive a line scan camera at a different rate. This circuit is only useful for line scan cameras.
  • Page 204 Encoder Divider Details The Axion-CL 7.2 Encoder Divider Details 7.2.1 Formula The following formula shows the equation used to scale the encoming encoder rate into the camera’s line rate: ------- Fout = The frequency used to driver the camera or the NTG or the CTabs...
  • Page 205: Handling Encoder Slow Down Or Stopping Axn-7-3

    The board will stay in this state until Fin goes above 1.6 KHz. This is useful when the encoder is being driven by a stage that is traveling back and forth. At both ends of travel when the stage changes directions, the board will not acquire. Version A.3 BitFlow, Inc. AXN-7-3...
  • Page 206: Encoder Divider Control Registers Axn-7-4

    Encoder Divider Control Registers The Axion-CL 7.3 Encoder Divider Control Registers The following table summarizes the registers: Table 7-1 Encoder Divider Registers Name Purpose ENC_DIV_M This controls the M factor in the Encoder Divider equa- tion (see Section 7.2.1) ENC_DIV_N...
  • Page 207: Quadrature Encoder

    The direction of acquisi- tion is controlled by the QENC_AQ_DIR register. Version A.3 BitFlow, Inc. AXN-8-1...
  • Page 208: Interval Mode Axn-8-2

    Introduction The Axion-CL 8.1.3 Interval Mode Often in situations when a stage is moving back and forth, acquisition is only required over a subsection of the total stage range. Interval mode has been designed for these situations. When the board is in interval mode, it only acquires lines when the encoder counter is between a lower limit and an upper limit.
  • Page 209 VFGx_ENCODERB+ VFGx_ENCODERB- Note: VFGx - refers to the VFG number that you wish to connect to. For example, if you want to connect a TLL A output to VFG 0, then you would use VFG0_ENCODERA_TTL. Version A.3 BitFlow, Inc. AXN-8-3...
  • Page 210: Understanding Stage Movement Vs. Quadrature Encoder Modes Axn-8-4

    Understanding Stage Movement vs. Quadrature Encoder Modes The Axion-CL 8.2 Understanding Stage Movement vs. Quadrature Encoder Modes The quadrature encoder system has many modes that can be used in various combi- nations. These combinations are easier to understand through a few simple illustra- tions.
  • Page 211 Quadrature Encoder Understanding Stage Movement vs. Quadrature Encoder Modes Figure 8-2 shows all of the major quadrature encoder modes. Acquisition Direction Positive Negative Both Not Valid Zoom In Figure 8-2 Quadrature Encoder Modes vs. Acquisition Version A.3 BitFlow, Inc. AXN-8-5...
  • Page 212 Understanding Stage Movement vs. Quadrature Encoder Modes The Axion-CL AXN-8-6 BitFlow, Inc. Version A.3...
  • Page 213: Quadrature Encoder And Divider Registers

    Quadrature Encoder and Divider Registers Introduction Quadrature Encoder and Divider Registers Chapter 9 9.1 Introduction This section enumerates the registers used to control the boards quadrature encoder circuit and encoder divider circuit. Version A.3 BitFlow, Inc. AXN-9-1...
  • Page 214: Con65 Register Axn-9-2

    CON65 Register The Axion-CL 9.2 CON65 Register Name SEL_ENCQ SEL_ENCDIV_INPUT SEL_ENCDIV ENC_DIV_N ENC_DIV_N ENC_DIV_N ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M ENC_DIV_M SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP AXN-9-2 BitFlow, Inc.
  • Page 215 Quadrature Encoder and Divider Registers CON65 Register SEL_ENCQ R/W, CON65[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit selects which quadrature encoder circuit output will be used on this VFG. SEL_ENCQ Meaning Select the output of this VFG’s quadrature circuit output Select the output of VFG0’s quadrature circuit output...
  • Page 216: Con66 Register Axn-9-4

    CON66 Register The Axion-CL 9.3 CON66 Register Name QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_DECODE QENC_AQ_DIR QENC_AQ_DIR QENC_INTRVL_MODE QENC_NO_REAQ Reserved SCAN_STEP_TRIG QENC_RESET AXN-9-4 BitFlow, Inc.
  • Page 217 Quadrature Encoder and Divider Registers CON66 Register QENC_INTRVL_ R/WR/W, CON66[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- This register contains the lower limit value that is used to start acquisition when the system is in interval mode (see QENC_INTRVL_MODE). QENC_DECODE R/W, CON66[24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit determines how often the quadrature counter is incremented.
  • Page 218 (also controlled by QENC_AQ_ DIR) SCAN_STEP_ R/W, CON66[30], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP TRIG The scan step circuit uses the encoder to generate a trigger to the system. The scan step trigger generates a trigger every N lines (N is set in the SCAN_STEP register).
  • Page 219: Con67 Register Axn-9-7

    9.4 CON67 Register Name QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_REAQ_MODE QENC_REAQ_MODE QENC_RESET_REAQ ENC_DIV_FOURCE_DC ENC_DIV_OPEN_LOOP ENC_DIV_FCLK_SEL ENC_DIV_FCLK_SEL ENC_DIV_FCLK_SEL Version A.3 BitFlow, Inc. AXN-9-7...
  • Page 220 CON67 Register The Axion-CL QENC_INTRVL_ R/W, CON67[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This register contains the upper limit value that is used to start acquisition when the system is in interval mode (see QENC_INTRVL_MODE). QENC_RESET_ R/W, CON67[25..24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-...
  • Page 221 Quadrature Encoder and Divider Registers CON67 Register ENC_DIV_ R/W, CON67[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP OPEN_LOOP Setting this bit to 1 forces the encoder divider to run open loop. ENC_DIV_FCLK_ R/W, CON67[31..29], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton- Reserved for future support for alternate Encoder Divider PLL Master clock frequen- cies.
  • Page 222: Con68 Register Axn-9-10

    CON68 Register The Axion-CL 9.5 CON68 Register Name RD_ENCQ_SELECTED RD_ENCDIV_SELECTED ENC_DIV_RESET ENC_DIV_AUTO_RESET_DISABLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-9-10 BitFlow, Inc.
  • Page 223 Quadrature Encoder and Divider Registers CON68 Register RD_ENCQ_ RO, CON68[0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED This bit indicates the current state of selected quad encoder circuit output. RD_ENCDIV_ RO, CON68[1], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP SELECTED This bit displays the current state of the selected encoder divider output.
  • Page 224 CON69 Register The Axion-CL 9.6 CON69 Register Name QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_PHASEA QENC_PHASEB QENC_DIR QENC_INTRVL_IN QENC_NEW_LINES Reserved QENC_FREQ QENC_FREQ AXN-9-12 BitFlow, Inc.
  • Page 225 Quadrature Encoder and Divider Registers CON69 Register QENC_COUNT RO, CON69[23..0], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bitfield displays the current quadrature encoder count. QENC_PHASEA RO, CON69[24], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP This bit displays the current logic level of the A quadrature encoder phase.
  • Page 226 CON69 Register The Axion-CL QENC_NEW_ RO, CON69[28], Aon-CXP, Axion-CL, Claxon-CXP, Claxon-FXP, Cyton-CXP LINES This bit indicates if the system is at an encoder count that corresponds to a new line. When QENC_NO_REAQ = 1, only lines that have not yet been scanned are acquired.
  • Page 227: System Probe

    SP_STOP_LIMIT allows this START/STOP record sequence to be run over multiple iter- ations. Among other things, this is useful for supporting SP_COUNT_MODEs min and max. Example: Determine the maximum number of Camera Link clocks occurring between lines over the course of a complete frame. Version A.3 BitFlow, Inc. AXN-10-1...
  • Page 228 System Probe Constants The Axion-CL 10.2 System Probe Constants This subsection lists the constants that be used to program the System Probe. 10.2.1 List of System Probe Events Table 10-1 lists all the events the System Probe can count and can use as the start, stop or sync event.
  • Page 229 Table 10-2 System Probe Events Functions Event Constant Numeric Meaning Value SPF_RISE 0x00 The rising edge of the signal SPF_FALL 0x01 The falling edge of the signal SPF_HIGH 0x02 The signal is high SPF_LOW 0x03 The signal is low Version A.3 BitFlow, Inc. AXN-10-3...
  • Page 230 System Probe Constants The Axion-CL 10.2.3 List of System Probe Counting Modes Table 10-3 lists different modes that the System Probe can count events. These are used when programing the SP_COUNT_MODE registers. Note: The Event Constants in Table 10-3 are defined in the SDK in the file “Gen2Def.h”...
  • Page 231 Below is a list of how to set each register (this uses the constants from Table 10-1). SP_SYNC_EVENT = SPE_IMMEDIATE SP_SYNC_FUNC = SPF_RISE SP_START_EVENT = SPE_IMMEDIATE SP_START_FUNC = SPF_RISE SP_STOP_EVENT = SPE_100_NS SP_STOP_FUNC = SPF_RISE SP_TARGET_EVENT = SPE_FVAL_B SP_TARGET_FUNC = SPF_RISE Version A.3 BitFlow, Inc. AXN-10-5...
  • Page 232 System Probe Examples The Axion-CL SP_STOP_EVENT_LIMIT = 1000000 SP_COUNT_MODE = SPCM_ACC For this example, there is no sync or start event. The recorder starts immediately. The events being recorded are the rising edge of FVAL. The SP_STOP_EVENT_LIMIT con- trols how long the counter accumulates (in this case it is counting the number of 100 nanosecond clocks).
  • Page 233 10.4 SP_EVENTS Name SP_TARGET_EVENT SP_TARGET_EVENT SP_TARGET_EVENT SP_TARGET_EVENT SP_TARGET_EVENT SP_TARGET_EVENT SP_TARGET_FUNC SP_TARGET_FUNC SP_STOP_EVENT SP_STOP_EVENT SP_STOP_EVENT SP_STOP_EVENT SP_STOP_EVENT SP_STOP_EVENT SP_STOP_FUNC SP_STOP_FUNC SP_START_EVENT SP_START_EVENT SP_START_EVENT SP_START_EVENT SP_START_EVENT SP_START_EVENT SP_START_FUNC SP_START_FUNC SP_SYNC_EVENT SP_SYNC_EVENT SP_SYNC_EVENT SP_SYNC_EVENT SP_SYNC_EVENT SP_SYNC_EVENT SP_SYNC_FUNC SP_SYNC_FUNC Version A.3 BitFlow, Inc. AXN-10-7...
  • Page 234 Event is high 3 (11b) Event is low SP_STOP_EVENT R/W, SP_EVENTS[13..8], Axion-CL Specifies the event that will stop recording. See Table 10-1 for a list of events. Note: This register can only be writeen when SP_BUSY reads back 0. SP_STOP_FUNC R/W, SP_EVENTS[15..14], Axion-CL...
  • Page 235 System Probe SP_EVENTS SP_START_FUNC R/W, SP_EVENTS[23..22], Axion-CL Specifies the event function that will start recording. See Table 10-1 for a list of events. SP_START_FUNC Meaning 0 (00b) Rising edge of event 1 (01b) Falling edge of event 2 (10b) Event is high...
  • Page 236 SP_CON The Axion-CL 10.5 SP_CON Name SP_COUNT_MODE SP_COUNT_MODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved SP_WRAP_COUNT SP_ARM SP_RST Reserved Reserved SP_COUNT_UPDATED SP_BUSY Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-10-10 BitFlow, Inc.
  • Page 237 System Probe SP_CON SP_COUNT_ R/W, SP_CON[1..0], Axion-CL MODE This register sets the mode of how the System Probe count (in register SP_COUNT) is updated. SP_COUNT_ Meaning MODE 0 (00b) Current: on each update SP_COUNT will reflect the current event capture.
  • Page 238 SP_CON The Axion-CL SP_RST WO, SP_CON[11], Axion-CL Reset the System Probe. Always writable. Always reads back 0. SP_COUNT_ RO, SP_CON[14], Axion-CL UPDATED SP_COUNT updates after each STOP event. SP_COUNT_UPDATED is set to 1 by hard- ware when the SP_COUNT is updated. In cases where SP_STOP_EVENT_LIMIT is > 0, there will be multiple updates to SP_COUNT.
  • Page 239 10.6 SP_STAT Name SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT SP_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-10-13...
  • Page 240 SP_STAT The Axion-CL SP_COUNT RO, SP_STAT[23..0], Axion-CL This register indicates the number of events that have occurred. This can be read at any time. When SP_BUSY is running, there may be several updates to SP_COUNT (it is updated after each STOP event). SP_STOP_EVENT_LIMIT controls how many stop events we require to end the capture.
  • Page 241 10.7 SP_LIMIT Name SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT SP_STOP_EVENT_LIMIT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-10-15...
  • Page 242 SP_LIMIT The Axion-CL SP_STOP_ R/W, SP_LIMIT[23..0], Axion-CL EVENT_LIMIT When collecting statistical data (i.e. SP_COUNT_MODE is not equal to 0), this register controls how many start/stop events should occur before the System Probe stops recording event data. Set this register to 1 for “single shot” event recording. Set it to the maximum number of event windows to count when using the System Probe for statistical calculations.
  • Page 243 This section contains definitions for registers that are only on the Axion-CL platform. The Cyton-CXP and the Axion-CL have many of the same registers, but some are only relevant to CXP and some are only used for Camera Link. This chapter contains the latter.
  • Page 244 CL_IOBUF_CTL The Axion-CL 11.2 CL_IOBUF_CTL Name IOBUF_SETTING IOBUF_SETTING IOBUF_SETTING IOBUF_SETTING IOBUF_SETTING Reserved Reserved Reserved IOBUF_LANE IOBUF_LANE IOBUF_LANE Reserved IOBUF_CHAN IOBUF_CHAN IOBUF_CHAN IOBUF_CHAN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IOBUF_WRITE IOBUF_BUSY AXN-11-2 BitFlow, Inc.
  • Page 245 Axion Camera Link Registers CL_IOBUF_CTL IOBUF_SETTING R/W, CL_IOBUF_CTL[4..0], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not be programmed directly by customers. IOBUF_LANE R/W, CL_IOBUF_CTL[10..8], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not be programmed directly by customers.
  • Page 246 CL_CHAN_CONFIG The Axion-CL 11.3 CL_CHAN_CONFIG Name PLL_PLL_PHASE_DIR PLL_ADJUST_PLL_PHASE PLL_CONFIG_ERROR PLL_RST ALIGN_MANUAL_RST ALIGN_MANUAL_DELAY ALIGN_MANUAL_LOCK ALIGN_MANUAL_EN ALIGN_AUTO_EN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PLL_CHAN PLL_CHAN PLL_CHAN PLL_CONFIG_BUSY AXN-11-4 BitFlow, Inc.
  • Page 247 Axion Camera Link Registers CL_CHAN_CONFIG PLL_PLL_ R/W, CL_CHAN_CONFIG[0], Axion-CL PHASE_DIR This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers. PLL_ADJUST_ R/W, CL_CHAN_CONFIG[1], Axion-CL PLL_PHASE This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers.
  • Page 248 CL_CHAN_CONFIG The Axion-CL ALIGN_AUTO_ R/W, CL_CHAN_CONFIG[8], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers. PLL_CHAN R/W, CL_CHAN_CONFIG[30..28], Axion-CL This Bitfield is used to program the Camera Link receiver settings. It should not but programmed directly by customers.
  • Page 249: Uart_Con_Base Axn-11-7

    11.4 UART_CON_BASE Name RS232_TX_DATA RS232_TX_DATA RS232_TX_DATA RS232_TX_DATA RS232_TX_DATA RS232_TX_DATA RS232_TX_DATA RS232_TX_DATA RS232_TX_GO RS232_RX_INT_ENABLE RS232_RX_FIFO_CLEAR RS232_RX_INVERT RS232_TX_INVERT Reserved Reserved Reserved RS232_BAUD_RATE RS232_BAUD_RATE RS232_BAUD_RATE RS232_BAUD_RATE RS232_BAUD_RATE RS232_BAUD_RATE RS232_BAUD_RATE RS232_BAUD_RATE RS232_RX_LEVEL RS232_RX_LEVEL RS232_RX_LEVEL RS232_RX_LEVEL Reserved RS232_RX_OVERFLOW RS232_RX_REQ RS232_TX_READY Version A.3 BitFlow, Inc. AXN-11-7...
  • Page 250 UART_CON_BASE The Axion-CL RS232_TX_ R/W, UART_CON_BASE[7..0], Axion-CL DATA Data byte to be sent out the CL RS-232 link. RS232_TX_GO R/W, UART_CON_BASE[8], Axion-CL Cause the data byte to be sent out the CL RS-232 link. RS232_RX_INT_ R/W, UART_CON_BASE[9], Axion-CL ENABLE Enable the interrupt that is asserted whenever a byte is received on the CL RS-232 link.
  • Page 251 Axion Camera Link Registers UART_CON_BASE RS232_TX_ R/W, UART_CON_BASE[31], Axion-CL READY When this bitfield is 1 the UART is ready to send another byte. Version A.3 BitFlow, Inc. AXN-11-9...
  • Page 252: Uart_Rdat_Base Axn-11-10

    UART_RDAT_BASE The Axion-CL 11.5 UART_RDAT_BASE Name RS232_RX_DATA RS232_RX_DATA RS232_RX_DATA RS232_RX_DATA RS232_RX_DATA RS232_RX_DATA RS232_RX_DATA RS232_RX_DATA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-10 BitFlow, Inc.
  • Page 253 Axion Camera Link Registers UART_RDAT_BASE RS232_RX_ RO, UART_RDAT_BASE[7..0], Axion-CL DATA The top of the CL RS-232 receive FIFO. Ready this register removes this byte from the FIFO. Version A.3 BitFlow, Inc. AXN-11-11...
  • Page 254 CL_CON_BASE The Axion-CL 11.6 CL_CON_BASE Name CL_USE_FVAL CL_USE_DVAL Reserved Reserved CL_CHAN_EN CL_CHAN_EN CL_CHAN_EN Reserved CL_LVAL_POS CL_LVAL_POS CL_LVAL_POS Reserved CL_MODE CL_MODE CL_MODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-12 BitFlow, Inc.
  • Page 255 Axion Camera Link Registers CL_CON_BASE CL_USE_FVAL R/W, CL_CON_BASE[0], Axion-CL Setting this bit to 1 will cause the CL front end to honor the FVAL (Frame Valid) signal. This should be set to 1 for area scan cameras and 0 for line scan cameras.
  • Page 256 TAP_CON_BASE The Axion-CL 11.7 TAP_CON_BASE Name TAP_MODE Reserved Reserved Reserved TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL TAP_FIXED_VAL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TAP_OUTPUT_16 AXN-11-14 BitFlow, Inc.
  • Page 257 Axion Camera Link Registers TAP_CON_BASE TAP_MODE R/W, TAP_CON_BASE[0], Axion-CL Reserved. TAP_FIXED_VAL R/W, TAP_CON_BASE[19..4], Axion-CL Reserved. TAP_OUTPUT_ R/W, TAP_CON_BASE[31], Axion-CL This bit should be set to 1 to output 10 to 16 bit pixels as 16-bit words. Version A.3 BitFlow, Inc.
  • Page 258: Tap_Table_Addr_Base Axn-11-16

    TAP_TABLE_ADDR_BASE The Axion-CL 11.8 TAP_TABLE_ADDR_BASE Name TAP_TABLE_OFFS TAP_TABLE_OFFS TAP_TABLE_OFFS TAP_TABLE_OFFS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TAP_TABLE_INDEX TAP_TABLE_INDEX TAP_TABLE_INDEX TAP_TABLE_INDEX Reserved Reserved Reserved Reserved TAP_TABLE_TYPE TAP_TABLE_TYPE Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-16 BitFlow, Inc.
  • Page 259 Axion Camera Link Registers TAP_TABLE_ADDR_BASE TAP_TABLE_ R/W, TAP_TABLE_ADDR_BASE[3..0], Axion-CL OFFS This register is used to program that Axion’s tap re-formatter. It should not be pro- grammed directly by users. TAP_TABLE_ R/W, TAP_TABLE_ADDR_BASE[19..16], Axion-CL INDEX This register is used to program that Axion’s tap re-formatter. It should not be pro- grammed directly by users.
  • Page 260: Tap_Table_Dat_Base Axn-11-18

    TAP_TABLE_DAT_BASE The Axion-CL 11.9 TAP_TABLE_DAT_BASE Name TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA TAP_DATA AXN-11-18 BitFlow, Inc.
  • Page 261 Axion Camera Link Registers TAP_TABLE_DAT_BASE TAP_DATA R/W, TAP_TABLE_DAT_BASE[31..0], Axion-CL This register is used to program that Axion’s tap re-formatter. It should not be pro- grammed directly by users. Version A.3 BitFlow, Inc. AXN-11-19...
  • Page 262: Flash_Con_Base Axn-11-20

    FLASH_CON_BASE The Axion-CL 11.10 FLASH_CON_BASE Name FLASH_CODE FLASH_CODE FLASH_CODE FLASH_CODE FLASH_CODE FLASH_CODE FLASH_CODE FLASH_CODE FLASH_WRITE FLASH_SHIFTBYTE FLASH_READ FLASH_RESET FLASH_BULK_ERASE FLASH_SECTOR_ERASE FLASH_SECTOR_PROTECT FLASH_EN4B_ADDR FLASH_EX4B_ADDR FLASH_READ_RDID FLASH_READ_STATUS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FLASH_ILLEGAL_WRITE FLASH_ILLEGAL_ERASE FLASH_DATA_VALID FLASH_BUSY AXN-11-20 BitFlow, Inc.
  • Page 263 Axion Camera Link Registers FLASH_CON_BASE FLASH_CODE R/W, FLASH_CON_BASE[7..0], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. FLASH_WRITE R/W, FLASH_CON_BASE[8], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers.
  • Page 264 FLASH_CON_BASE The Axion-CL FLASH_EN4B_ R/W, FLASH_CON_BASE[15], Axion-CL ADDR This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. FLASH_EX4B_ R/W, FLASH_CON_BASE[16], Axion-CL ADDR This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers.
  • Page 265: Flash_Addr_Base Axn-11-23

    11.11 FLASH_ADDR_BASE Name FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR Version A.3 BitFlow, Inc. AXN-11-23...
  • Page 266 FLASH_ADDR_BASE The Axion-CL FLASH_ADDR R/W, FLASH_ADDR_BASE[31..0], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. AXN-11-24 BitFlow, Inc. Version A.3...
  • Page 267: Flash_Dat_Base Axn-11-25

    11.12 FLASH_DAT_BASE Name FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_OUT FLASH_DATA_IN FLASH_DATA_IN FLASH_DATA_IN FLASH_DATA_IN FLASH_DATA_IN FLASH_DATA_IN FLASH_DATA_IN FLASH_DATA_IN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-11-25...
  • Page 268 This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers. FLASH_DATA_IN R/W, FLASH_DAT_BASE[15..8], Axion-CL This bitfield is used to program the boards flash memory. It should not be pro- grammed directly by customers.
  • Page 269: Tap_Dipr_Control Axn-11-27

    11.13 TAP_DIPR_CONTROL Name DIPR_NUM_TAPS DIPR_NUM_TAPS DIPR_NUM_TAPS DIPR_NUM_TAPS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DIPR_PIX_SIZE Reserved Reserved DIPR_EN DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK DIPR_MASK Version A.3 BitFlow, Inc. AXN-11-27...
  • Page 270 TAP_DIPR_CONTROL The Axion-CL DIPR_NUM_ R/W, TAP_DIPR_CONTROL[3..0], Axion-CL TAPS When the board is using the DIPR (Dedicated Interleaved Pixel Router), this register should be set to the number of taps the camera is putting out. DIPR_PIX_SIZE R/W, TAP_DIPR_CONTROL[11], Axion-CL When the board is using the DIPR, set this bit to indicate the pixels size. Set to 0 for 8- bit pixels, set to 1 for 10-bit to 16-bit pixels.
  • Page 271 11.14 CLMON_FVAL_EXP Name FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_EXP_COUNT FVAL_ERROR Reserved Reserved Reserved FVAL_ENABLE Reserved Reserved FVAL_AUTO_LEARN Version A.3 BitFlow, Inc. AXN-11-29...
  • Page 272 CLMON_FVAL_EXP The Axion-CL FVAL_EXP_ R/W, CLMON_FVAL_EXP[23..0], Axion-CL COUNT The expected number of lines per frame (FVAL). FVAL_ERROR R/W, CLMON_FVAL_EXP[24], Axion-CL If the lines per FVAL is different from LFAL_EXP_COUNT, this bit will be set to 1. If a mismatch occurs, monitoring of the FVAL will stop. Set this bit to 0 and then set FVAL_ ENABLE to 1 to restart FVAL monitoring.
  • Page 273 11.15 CLMON_LVAL_EXP Name LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_EXP_COUNT LVAL_B_ERROR LVAL_M_ERROR LVAL_F_ERROR Reserved LVAL_B_ENABLE LVAL_M_ENABLE LVAL_F_ENABLE LVAL_AUTO_LEARN Version A.3 BitFlow, Inc. AXN-11-31...
  • Page 274 Read LVAL_B/M/F_ERROR and FVAL_ERROR bits to determine the cause of the inter- rupt. LVAL_B_ENABLE R/W, CLMON_LVAL_EXP[28], Axion-CL Setting this bit to 1 to tells the board to monitor the CL Base LVAL. If this bit is 0, the CL Base LVAL will not be monitored.
  • Page 275 Axion Camera Link Registers CLMON_LVAL_EXP LVAL_F_ENABLE R/W, CLMON_LVAL_EXP[30], Axion-CL Setting this bit to 1 to tells the board to monitor the CL Full LVAL. If this bit is 0, the CL Full LVAL will not be monitored. LVAL_AUTO_ R/W, CLMON_LVAL_EXP[31], Axion-CL...
  • Page 276 CLMON_FVAL_COUNT The Axion-CL 11.16 CLMON_FVAL_COUNT Name FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT FVAL_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-34 BitFlow, Inc.
  • Page 277 Axion Camera Link Registers CLMON_FVAL_COUNT FVAL_COUNT R/W, CLMON_FVAL_COUNT[23..0], Axion-CL Displays the current number of lines per frame, updated every frame. If a mismatch occurs, this will display the number of lines per frame for the mismatching frame. Version A.3 BitFlow, Inc.
  • Page 278 CLMON_LVAL_B_COUNT The Axion-CL 11.17 CLMON_LVAL_B_COUNT Name LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT LVAL_B_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-36 BitFlow, Inc.
  • Page 279 Axion Camera Link Registers CLMON_LVAL_B_COUNT LVAL_B_COUNT R/W, CLMON_LVAL_B_COUNT[23..0], Axion-CL The current number of CL clocks per line for the CL Base input. This is updates every CL Base LVAL. If a mismatch occurs, this will display the number of CL clocks for the mismatching CL Base line.
  • Page 280 CLMON_LVAL_M_COUNT The Axion-CL 11.18 CLMON_LVAL_M_COUNT Name LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT LVAL_M_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-38 BitFlow, Inc.
  • Page 281 Axion Camera Link Registers CLMON_LVAL_M_COUNT LVAL_M_COUNT R/W, CLMON_LVAL_M_COUNT[23..0], Axion-CL The current number of CL clocks per line for the CL Medium input. This is updates every CL Medium LVAL. If a mismatch occurs, this will display the number of CL clocks for the mismatching CL Medium line.
  • Page 282 CLMON_LVAL_F_COUNT The Axion-CL 11.19 CLMON_LVAL_F_COUNT Name LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT LVAL_F_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-11-40 BitFlow, Inc.
  • Page 283 CLMON_LVAL_F_COUNT LVAL_F_COUNT R/W, CLMON_LVAL_F_COUNT[23..0], Axion-CL The current number of CL clocks per line for the CL Full input. This is updates every CL Full LVAL. If a mismatch occurs, this will display the number of CL clocks for the mis- matching CL Full line.
  • Page 284: Clmon_Lval_B_Count Axn-11-36

    CLMON_LVAL_F_COUNT The Axion-CL AXN-11-42 BitFlow, Inc. Version A.3...
  • Page 285: Axion Power And Miscellaneous Registers

    Axion Power and Miscellaneous Registers Introduction Axion Power and Miscellaneous Registers Chapter 12 12.1 Introduction This chapter contains details on the Axion PoCL registers as well as some other mis- cellaneous registers. Version A.3 BitFlow, Inc. AXN-12-1...
  • Page 286 CON104 The Axion-CL 12.2 CON104 Name 0_POCL_EN_POWER Reserved 0_POCL_EN_CAM_SENSE 0_POCL_HW_DIS Reserved 0_POCL_OPEN_DETECTED 0_POCL_OVER_DETECTED 0_POCL_OVER_LATCH Reserved 0_CL_CLOCK_LOST_LATCH 0_CL_CLOCK_DETECTED 0_POCL_STATE 0_POCL_STATE 0_POCL_OVR_AUTO_RESTART 0_POCL_SENSE_BYPASS 0_ENABLE_POCL_SYSTEM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-12-2 BitFlow, Inc.
  • Page 287 Axion Power and Miscellaneous Registers CON104 0_POCL_EN_ RO, CON104[0], Axion-CL POWER PoCL power has been applied to the camera. 0_POCL_EN_ RO, CON104[2], Axion-CL CAM_SENSE PoCL sense is enabled. 0_POCL_HW_ RO, CON104[3], Axion-CL Describe 0_POCL_HW_DIS. 0_POCL_OPEN_ RO, CON104[5], Axion-CL DETECTED Open circuit detected.
  • Page 288 CON104 The Axion-CL 0_POCL_SENSE_ R/W, CON104[14], Axion-CL BYPASS Bypass the PoCL sense circuit and apply power. This register is for testing only, it should not be set by the user. 0_ENABLE_ R/W, CON104[15], Axion-CL POCL_SYSTEM Poking this bit to 1 enables the PoCL circuit for this connector.
  • Page 289 12.3 CON105 Name 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF 0_POCL_TIMER_OFF Reserved Reserved Reserved Reserved Reserved 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE 0_POCL_TIMER_STABLE Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-12-5...
  • Page 290 The Axion-CL 0_POCL_TIMER_ R/W, CON105[10..0], Axion-CL This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support. 0_POCL_TIMER_ R/W, CON105[26..16], Axion-CL STABLE This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support.
  • Page 291 12.4 CON106 Name 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON 0_POCL_TIMER_ON Reserved Reserved Reserved Reserved Reserved 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT 0_POCL_TIMER_DISCONNECT Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-12-7...
  • Page 292 The Axion-CL 0_POCL_TIMER_ R/W, CON106[10..0], Axion-CL This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support. 0_POCL_TIMER_ R/W, CON106[26..16], Axion-CL DISCONNECT This bitfield controls the timing of the PoCL state machine. It should not be changed by the user unless instructed by BitFlow Customer Support.
  • Page 293 12.5 CON136 Name 1_POCL_EN_POWER Reserved 1_POCL_EN_CAM_SENSE 1_POCL_HW_DIS Reserved 1_POCL_OPEN_DETECTED 1_POCL_OVER_DETECTED 1_POCL_OVER_LATCH Reserved 1_CL_CLOCK_LOST_LATCH 1_CL_CLOCK_DETECTED 1_POCL_STATE 1_POCL_STATE 1_POCL_OVR_AUTO_RESTART 1_POCL_SENSE_BYPASS 1_ENABLE_POCL_SYSTEM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-12-9...
  • Page 294 CON136 The Axion-CL 1_POCL_EN_ RO, CON136[0], Axion-CL POWER See 0_POCL_EN_POWER. 1_POCL_EN_ RO, CON136[2], Axion-CL CAM_SENSE See 0_POCL_EN_CAM_SENSE. 1_POCL_HW_ RO, CON136[3], Axion-CL See 0_POCL_HW_DIS. 1_POCL_OPEN_ RO, CON136[5], Axion-CL DETECTED See 0_POCL_OPEN_DETECTED. 1_POCL_OVER_ RO, CON136[6], Axion-CL DETECTED See 0_POCL_OVER_DETECTED. 1_POCL_OVER_ RO, CON136[7], Axion-CL LATCH See 0_POCL_OVER_LATCH.
  • Page 295 Axion Power and Miscellaneous Registers CON136 1_POCL_SENSE_ R/W, CON136[14], Axion-CL BYPASS See 0_POCL_SENSE_BYPASS. 1_ENABLE_ R/W, CON136[15], Axion-CL POCL_SYSTEM See 0_ENABLE_POCL_SYSTEM. Version A.3 BitFlow, Inc. AXN-12-11...
  • Page 296 CON137 The Axion-CL 12.6 CON137 Name 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF 1_POCL_TIMER_OFF Reserved Reserved Reserved Reserved Reserved 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE 1_POCL_TIMER_STABLE Reserved Reserved Reserved Reserved Reserved AXN-12-12 BitFlow, Inc.
  • Page 297 Axion Power and Miscellaneous Registers CON137 1_POCL_TIMER_ R/W, CON137[10..0], Axion-CL See 0_POCL_TIMER_OFF. 1_POCL_TIMER_ R/W, CON137[26..16], Axion-CL STABLE See 0_POCL_TIMER_STABLE. Version A.3 BitFlow, Inc. AXN-12-13...
  • Page 298 CON138 The Axion-CL 12.7 CON138 Name 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON 1_POCL_TIMER_ON Reserved Reserved Reserved Reserved Reserved 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT 1_POCL_TIMER_DISCONNECT Reserved Reserved Reserved Reserved Reserved AXN-12-14 BitFlow, Inc.
  • Page 299 Axion Power and Miscellaneous Registers CON138 1_POCL_TIMER_ R/W, CON138[10..0], Axion-CL See 0_POCL_TIMER_ON. 1_POCL_TIMER_ R/W, CON138[26..16], Axion-CL DISCONNECT See 0_POCL_TIMER_DISCONNECT. Version A.3 BitFlow, Inc. AXN-12-15...
  • Page 300 CON168 The Axion-CL 12.8 CON168 Name 2_POCL_EN_POWER Reserved 2_POCL_EN_CAM_SENSE 2_POCL_HW_DIS Reserved 2_POCL_OPEN_DETECTED 2_POCL_OVER_DETECTED 2_POCL_OVER_LATCH Reserved 2_CL_CLOCK_LOST_LATCH 2_CL_CLOCK_DETECTED 2_POCL_STATE 2_POCL_STATE 2_POCL_OVR_AUTO_RESTART 2_POCL_SENSE_BYPASS 2_ENABLE_POCL_SYSTEM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AXN-12-16 BitFlow, Inc.
  • Page 301 Axion Power and Miscellaneous Registers CON168 2_POCL_EN_ RO, CON168[0], Axion-CL POWER See 0_POCL_EN_POWER. 2_POCL_EN_ RO, CON168[2], Axion-CL CAM_SENSE See 0_POCL_EN_CAM_SENSE. 2_POCL_HW_ RO, CON168[3], Axion-CL See 0_POCL_HW_DIS. 2_POCL_OPEN_ RO, CON168[5], Axion-CL DETECTED See 0_POCL_OPEN_DETECTED. 2_POCL_OVER_ RO, CON168[6], Axion-CL DETECTED See 0_POCL_OVER_DETECTED.
  • Page 302 CON168 The Axion-CL 2_POCL_SENSE_ R/W, CON168[14], Axion-CL BYPASS See 0_POCL_SENSE_BYPASS. 2_ENABLE_ R/W, CON168[15], Axion-CL POCL_SYSTEM See 0_ENABLE_POCL_SYSTEM. AXN-12-18 BitFlow, Inc. Version A.3...
  • Page 303 12.9 CON169 Name 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF 2_POCL_TIMER_OFF Reserved Reserved Reserved Reserved Reserved 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE 2_POCL_TIMER_STABLE Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-12-19...
  • Page 304 CON169 The Axion-CL 2_POCL_TIMER_ R/W, CON169[10..0], Axion-CL See 0_POCL_TIMER_OFF. 2_POCL_TIMER_ R/W, CON169[26..16], Axion-CL STABLE See 0_POCL_TIMER_STABLE. AXN-12-20 BitFlow, Inc. Version A.3...
  • Page 305 12.10 CON170 Name 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON 2_POCL_TIMER_ON Reserved Reserved Reserved Reserved Reserved 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT 2_POCL_TIMER_DISCONNECT Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-12-21...
  • Page 306 CON170 The Axion-CL 2_POCL_TIMER_ R/W, CON170[10..0], Axion-CL See 0_POCL_TIMER_ON. 2_POCL_TIMER_ R/W, CON170[26..16], Axion-CL DISCONNECT See 0_POCL_TIMER_DISCONNECT. AXN-12-22 BitFlow, Inc. Version A.3...
  • Page 307 12.11 CON200 Name 3_POCL_EN_POWER Reserved 3_POCL_EN_CAM_SENSE 3_POCL_HW_DIS Reserved 3_POCL_OPEN_DETECTED 3_POCL_OVER_DETECTED 3_POCL_OVER_LATCH Reserved 3_CL_CLOCK_LOST_LATCH 3_CL_CLOCK_DETECTED 3_POCL_STATE 3_POCL_STATE 3_POCL_OVR_AUTO_RESTART 3_POCL_SENSE_BYPASS 3_ENABLE_POCL_SYSTEM Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.3 BitFlow, Inc. AXN-12-23...
  • Page 308 CON200 The Axion-CL 3_POCL_EN_ RO, CON200[0], Axion-CL POWER See 0_POCL_EN_POWER. 3_POCL_EN_ RO, CON200[2], Axion-CL CAM_SENSE See 0_POCL_EN_CAM_SENSE. 3_POCL_HW_ RO, CON200[3], Axion-CL See 0_POCL_HW_DIS. 3_POCL_OPEN_ RO, CON200[5], Axion-CL DETECTED See 0_POCL_OPEN_DETECTED. 3_POCL_OVER_ RO, CON200[6], Axion-CL DETECTED See 0_POCL_OVER_DETECTED. 3_POCL_OVER_ RO, CON200[7], Axion-CL LATCH See 0_POCL_OVER_LATCH.
  • Page 309 Axion Power and Miscellaneous Registers CON200 3_POCL_SENSE_ R/W, CON200[14], Axion-CL BYPASS See 0_POCL_SENSE_BYPASS. 3_ENABLE_ R/W, CON200[15], Axion-CL POCL_SYSTEM See 0_ENABLE_POCL_SYSTEM. Version A.3 BitFlow, Inc. AXN-12-25...
  • Page 310 CON201 The Axion-CL 12.12 CON201 Name 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF 3_POCL_TIMER_OFF Reserved Reserved Reserved Reserved Reserved 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE 3_POCL_TIMER_STABLE Reserved Reserved Reserved Reserved Reserved AXN-12-26 BitFlow, Inc.
  • Page 311 Axion Power and Miscellaneous Registers CON201 3_POCL_TIMER_ R/W, CON201[10..0], Axion-CL See 0_POCL_TIMER_OFF. 3_POCL_TIMER_ R/W, CON201[26..16], Axion-CL STABLE See 0_POCL_TIMER_STABLE. Version A.3 BitFlow, Inc. AXN-12-27...
  • Page 312 CON202 The Axion-CL 12.13 CON202 Name 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON 3_POCL_TIMER_ON Reserved Reserved Reserved Reserved Reserved 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT 3_POCL_TIMER_DISCONNECT Reserved Reserved Reserved Reserved Reserved AXN-12-28 BitFlow, Inc.
  • Page 313 Axion Power and Miscellaneous Registers CON202 3_POCL_TIMER_ R/W, CON202[10..0], Axion-CL See 0_POCL_TIMER_ON. 3_POCL_TIMER_ R/W, CON202[26..16], Axion-CL DISCONNECT See 0_POCL_TIMER_DISCONNECT. Version A.3 BitFlow, Inc. AXN-12-29...
  • Page 314 CON356 The Axion-CL 12.14 CON356 Name FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR Reserved FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH AXN-12-30 BitFlow, Inc.
  • Page 315 Day that this firmware was compiled in BCD format. Example: 0x18 the 18th of the month. FW_BUILD_ RO, CON356[31..24], Karbon-CXP, Cyton-CXP MONTH Month that this firmware was compiled in BCD format. Example: 0x12 is december. Version A.3 BitFlow, Inc. AXN-12-31...
  • Page 316 CON357 The Axion-CL 12.15 CON357 Name FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL AXN-12-32 BitFlow, Inc.
  • Page 317 HOUR Hour that this firmware was compiled. Example: 0x23 is 11pm (23rd hour). FPGA_ID RO, CON357[23..16], Karbon-CXP, Cyton-CXP FPGA Identifier FW_CMPTBL RO, CON357[31..24], Karbon-CXP, Cyton-CXP Firmware compatibility version (must match SDK driver internal firmware version). Version A.3 BitFlow, Inc. AXN-12-33...
  • Page 318 CON357 The Axion-CL AXN-12-34 BitFlow, Inc. Version A.3...
  • Page 319: Specifications

    Chapter 13 13.1 Introduction This chapter describes the general specifications of the Axion-CL family. The numeri- cal values for he specifications are listed in Table 13-1. If more information is available for a given specification t will be an entry in the column marked “Details”.
  • Page 320 Introduction The Axion-CL Table 13-1 Axion-CL Specifications Specifications Value Units Details Mechanical dimensions 6.8 x 4.2 Inches Mechanical dimensions 17.4 x 10.6 Centimeters Maximum PoCL Power @12 Volts Watts Per CL Connector LVDS Drivers SN65LVDS31D LVDS Receivers SNLVDS3486 TTL Drivers...
  • Page 321: Pci Express Compatibility Axn-13-3

    13.2 PCI Express Compatibility The Axion-CL is a PCIe x4 Gen 2 board. However, it will work in any PCIe slot that it fits into. This means it will work in x4, x8 and x16 slots, however, it will also work in x1 slots if these slots are mechanically compatibility with an x4 board, though performance will be greatly degraded.
  • Page 322: Maximum Pixels Per Line Axn-13-4

    Maximum Pixels Per Line The Axion-CL 13.3 Maximum Pixels Per Line The maximum pixels per line depends on the camera’s output tap format and the pixel format. The board’s Tap Reformatter supports both interleaved (e.g. 1X4-1Y) and segmented (e.g. 4X1-1Y) tap formats. However, the maximum line lengths for inter- leaved cameras can be extended using a special Dedicated Interleaved Pixel Router (DIPR).
  • Page 323: Maximum Lines Per Frame Axn-13-5

    Maximum Lines Per Frame 13.4 Maximum Lines Per Frame This limitation is for area scan cameras. For line scan cameras, the number of lines per frame is essentially unlimited. Please contact BitFlow customer support for more infor- mation. Version A.3 BitFlow, Inc.
  • Page 324: Axion Power Requirements Axn-13-6

    The Axion-CL power requirements listed inTable 13-1 are the requirements of the board’s circuitry only. In addition, the Axion-CL can provide up to 4 watts of power to each Camera Link connector. The 12 Volt rail of the PCIe bus cannot provide enough power if all CL connector links are drawing maximum power.
  • Page 325: Mechanical

    Chapter 14 14.1 Introduction This chapter describes the mechanical characteristics of the Axion-CL This includes description of all of the connectors on the board and pin-outs for these connectors. The mechanical layouts of the Axions are shown on the following pages. Please see the table for cross reference.
  • Page 326 Introduction The Axion-CL SW1.2 SW1.1 Pin 1 D3 D4 D5 D6 D7 D8 D8 D10 Pin 1 Pin 2 P3/P4 BASE MED/FULL Pin 59 Pin 60 TRILED2 End View PCI Express x4 Gen 2 Connector Figure 14-1 Axion-1xE Board Layout AXN-14-2 BitFlow, Inc.
  • Page 327 Pin 1 D4 D5 D6 D7 D8 D8 D10 Pin 1 Pin 2 P3/P4 TRILED1 MED/FULL1 BASE0 MED/FULL0 Pin 59 Pin 60 TRILED2 End View PCI Express x4 Gen 2 Connector Figure 14-2 Axion-2xE Board Layout Version A.3 BitFlow, Inc. AXN-14-3...
  • Page 328 Introduction The Axion-CL Flex cable To Main Board P1 BASE1 Figure 14-3 Axion-2xE Fourth CL Connector AXN-14-4 BitFlow, Inc. Version A.3...
  • Page 329 Mechanical Introduction SW1.2 SW1.1 TRILED1 D4 D5 D6 PCI Express x4 Gen 2 Connector Figure 14-4 Axion-1xB Board Layout Version A.3 BitFlow, Inc. AXN-14-5...
  • Page 330 Introduction The Axion-CL Top View Pin 2 Pin 40t SW1.2 SW1.1 D1 D2 Pin 1 Pin 39 TRILED1 D4 D5 D6 TRILED2 PCI Express x4 Gen 2 Connector Figure 14-5 Axion-2xB Board Layout AXN-14-6 BitFlow, Inc. Version A.3...
  • Page 331 Introduction SW1.2 SW1.1 D3 D4 D5 D6 D7 D8 D9 Pin 1 Pin 2 TRILED1 TRILED2 TRILED3 Pin 59 Pin 60 TRILED4 End View PCI Express x4 Gen 2 Connector Figure 14-6 Axion-4xB Board Layout Version A.3 BitFlow, Inc. AXN-14-7...
  • Page 332 Introduction The Axion-CL Flex cable To Main Board P1 Figure 14-7 Axion-4xB Fourth CL Connector AXN-14-8 BitFlow, Inc. Version A.3...
  • Page 333 14.2.1 The CL Connectors The CL connectors are for connecting Camera Link cameras. The Axion-CL uses both MDR and SDR connectors. These connectors are fully compliant with the Camera Link version 1.1 and later specification.
  • Page 334 The Axion-CL Connectors The Axion-CL Table 14-4 Camera Link Connectors - Axion-1xE and Axion 2xE Camera(s) BASE0 MED/FULL0 BASE1 MED/FULL1 One Base CL Camera Camera 0 - CL1 One Medium CL Camera Camera 0 - CL1 Camera 0 - CL2...
  • Page 335 Switches 14.3 Switches There is one piano-type switch block, SW1, on the Axion-CL with two switches. These are used to identify individual boards when there is more than one board in a system. The idea is to set the switches differently on each board in the system. The switch set- tings can be read for each board from software (by reading the SW bitfield).
  • Page 336 BitFlow’s Customer Support team. 14.4.2 Jumper JP2 T is one user configurable jumper on the Axion-CL, it controls the source of the power that is provided to the Camera Link camera(s) connected to the Axion (PoCL power).
  • Page 337 VFG on the mulit-VFG Axions are ORed together. The following table show ena example for one LED on aboard with two VFGs. Table 14-8 LED control from two VFGs VFG0 VFG1 LED_BLUE LED_BLUE Version A.3 BitFlow, Inc. AXN-14-13...
  • Page 338 LEDs The Axion-CL 14.5.1 Camera Status LEDS The Camera Status LEDS change color and are blinking or steady depending on the status of the connected cameras and the camera. There is one status LED for each cameras. Cameras that are using two connectors still only get one status LED. See Table 14-9 for detailed information on the meaning of these LEDs.
  • Page 339 I/O problems. It can be used as a trigger, encoder, or I/O that is routed off the board. Please see Section 2.1 for more information on how the button can be routed. Note: The Axion Rev 2.x models do not have this button. Version A.3 BitFlow, Inc. AXN-14-15...
  • Page 340 PCs. This connector is also known as the “floppy connector”. For PCs that do have this type of connector, BitFlow offers an adapter cable that goes between P4 and a standard Molex 4-pin peripheral connector available in almost all PCs.
  • Page 341 Mechanical The BitBox Box Connector 14.8 The BitBox Box Connector This connector is for the BitBox, and I/O break out box that is available from BitFlow. Please contact BitFlow for more information. Version A.3 BitFlow, Inc. AXN-14-17...
  • Page 342 I/O Connector Pinout for the Axion-1xE, Axion-2xE and Axion-4xB The Axion-CL 14.9 I/O Connector Pinout for the Axion-1xE, Axion-2xE and Axion-4xB The pin-out for the I/O Connector for the Axion-1xE, Axion2xE and Axion-4xB are illustrated in the Table 14-11. Note: Signal names start with the Virtual Frame Grabber (VFG) that they are routed to.
  • Page 343 Signal Comment VFG2_CC3+ LVDS VFG2_CC3- LVDS VFG3_CC3+ LVDS VFG3_CC3- LVDS VFG0_TRIGGER_TTL VFG0_ENCODERA_TTL VFG0_ENCODERB_TTL VFG1_TRIGGER_TTL VFG1_ENCODERA_TTL VFG1_ENCODERB_TTL VFG2_TRIGGER_TTL VFG2_ENCODERA_TTL VFG2_ENCODERB_TTL VFG3_TRIGGER_TTL VFG3_ENCODERA_TTL VFG3_ENCODERB_TTL Reserved VFG0_CC3_TTL VFG0_CC4_TTL VFG0_CC2_TTL VFG1_CC3_TTL VFG1_CC4_TTL VFG1_CC2_TTL VFG2_CC3_TTL VFG2_CC4_TTL VFG2_CC2_TTL VFG3_CC3_TTL VFG3_CC4_TTL VFG3_CC2_TTL Version A.3 BitFlow, Inc. AXN-14-19...
  • Page 344 I/O Connector Pinout for the Axion-1xB The Axion-CL 14.10 I/O Connector Pinout for the Axion-1xB The pin-out for the I/O Connector for the Axion-1xB is illustrated in the Table 14-12. Table 14-12 I/O Connector for the Axion-1xB Signal Comment VFG0_TRIGGER+...
  • Page 345 VFG0_ENCODERA- LVDS VFG0_ENCODERB+ LVDS VFG0_ENCODERB- LVDS VFG0_CC3+ LVDS VFG0_CC3- LVDS VFG0_ENCODERA_TTL VFG0_TRIGGER_TTL VFG0_ENCODERB_TTL VFG0_CC3_TTL VFG0_CC4_TTL VFG0_CC2_TTL VFG1_TRIGGER+ LVDS VFG1_TRIGGER- LVDS VFG1_ENCODERA+ LVDS VFG1_ENCODERA- LVDS VFG1_ENCODERB+ LVDS VFG1_ENCODERB- LVDS VFG1_CC3+ LVDS VFG1_CC3- LVDS VFG1_TRIGGER_TTL VFG1_ENCODERA_TTL VFG1_CC3_TTL Version A.3 BitFlow, Inc. AXN-14-21...
  • Page 346 I/O Connector Pinout for the Axion-2xB The Axion-CL Table 14-13 I/O Connector for the Axion-2xB Signal Comment VFG1_ENCODERB_TTL VFG1_CC2_TTL VFG1_CC4_TTL AXN-14-22 BitFlow, Inc. Version A.3...
  • Page 347 ATS_CONDITION AXN-4-23 2_POCL_EN_CAM_SENSE AXN-12-17 ATS_CONTROL AXN-4-15 2_POCL_EN_POWER AXN-12-17 ATS_COUNT AXN-4-23 2_POCL_HW_DIS AXN-12-17 ATS_CT0_DEFAULT_STATE AXN-4-16 2_POCL_OPEN_DETECTED AXN-12-17 ATS_CT1_DEFAULT_STATE AXN-4-16 2_POCL_OVER_DETECTED AXN-12-17 ATS_CT2_DEFAULT_STATE AXN-4-16 2_POCL_OVER_LATCH AXN-12-17 ATS_CT3_DEFAULT_STATE AXN-4-16 2_POCL_OVR_AUTO_RESTART AXN-12-17 ATS_END_OF_SEQUENCE AXN-4-24 2_POCL_SENSE_BYPASS AXN-12-18 ATS_IDX_ACCESS AXN-4-20 2_POCL_STATE AXN-12-17 ATS_IDX_JUMP AXN-4-18 BitFlow, Inc.
  • Page 348 Camera Link Camera Power (PoCL) AXN-1-9 BOX_OUT_DYN_SEL_SET_B AXN-6-30 CL Connectors AXN-14-9 BOX_OUT_DYN_SEL_SET_C AXN-6-32 CL_CHAN_CONFIG AXN-11-4 BOX_OUT_MODE_DIFF_0 AXN-6-40 CL_CHAN_EN AXN-11-13 BOX_OUT_MODE_DIFF_1 AXN-6-40 CL_CON_BASE AXN-11-12 BOX_OUT_MODE_DIFF_10 AXN-6-43 CL_IOBUF_CTL AXN-11-2 BOX_OUT_MODE_DIFF_11 AXN-6-43 CL_LVAL_POS AXN-11-13 BOX_OUT_MODE_DIFF_2 AXN-6-40 CL_MODE AXN-11-13 BOX_OUT_MODE_DIFF_3 AXN-6-41 CL_USE_DVAL AXN-11-13 BOX_OUT_MODE_DIFF_4 AXN-6-41 CL_USE_FVAL AXN-11-13 BitFlow, Inc.
  • Page 349 FLASH_DATA_VALID AXN-11-22 CPLD_MODE AXN-3-12 FLASH_EN4B_ADDR AXN-11-22 CPLD_STRAP AXN-3-12 FLASH_EX4B_ADDR AXN-11-22 CURR_FETCH_SIZE AXN-3-8 FLASH_ILLEGAL_ERASE AXN-11-22 FLASH_ILLEGAL_WRITE AXN-11-22 FLASH_READ AXN-11-21 FLASH_READ_RDID AXN-11-22 DIPR_MASK AXN-11-28 FLASH_READ_STATUS AXN-11-22 DIPR_NUM_TAPS AXN-11-28 FLASH_RESET AXN-11-21 DIPR_PIX_EN AXN-11-28 FLASH_SECTOR_ERASE AXN-11-21 DIPR_PIX_SIZE AXN-11-28 FLASH_SECTOR_PROTECT AXN-11-21 DISABLE_PKT_FLUSH_TIMER AXN-3-30 BitFlow, Inc.
  • Page 350 LVAL_EXP_COUNT AXN-11-32 INT_PCIE_PKT_DROPPED_M AXN-2-56 LVAL_F_COUNT AXN-11-41 INT_PCIE_PKT_DROPPED_WP AXN-2-59 LVAL_F_ENABLE AXN-11-33 INT_TRIG AXN-2-50 LVAL_F_ERROR AXN-11-32 INT_TRIG_M AXN-2-55 LVAL_M_COUNT AXN-11-39 INT_TRIG_WP AXN-2-58 LVAL_M_ENABLE AXN-11-32 INT_X_ACQUIRED AXN-2-50 LVAL_M_ERROR AXN-11-32 INT_X_ACQUIRED_M AXN-2-55 INT_X_ACQUIRED_WP AXN-2-58 INT_X_START AXN-2-50 INT_X_START_M AXN-2-55 MAX_FETCH_SIZE AXN-3-8 INT_X_START_WP AXN-2-58 BitFlow, Inc.
  • Page 351 QENC_NEW_LINES AXN-9-14 RS232_RX_DATA AXN-11-11 QENC_NO_REAQ AXN-9-5 RS232_RX_FIFO_CLEAR AXN-11-8 QENC_PHASEA AXN-9-11, AXN-9-13 RS232_RX_INT_ENABLE AXN-11-8 QENC_PHASEB AXN-9-13, AXN-9-14 RS232_RX_INVERT AXN-11-8 QENC_RESET AXN-9-6 RS232_RX_LEVEL AXN-11-8 QENC_RESET_MODE AXN-9-8 RS232_RX_OVERFLOW AXN-11-8 QENC_RESET_REAQ AXN-9-8 RS232_RX_REQ AXN-11-8 QTABS_LOADED_STATUS AXN-3-24 RS232_TX_DATA AXN-11-8 QTABS_USED_STATUS AXN-3-17 RS232_TX_GO AXN-11-8 BitFlow, Inc.
  • Page 352 TS_CT2_DEFAULT_STATE AXN-4-5 SP_EVENTS AXN-10-7 TS_CT3_DEFAULT_STATE AXN-4-5 SP_LIMIT AXN-10-15 TS_END_OF_SEQUENCE AXN-4-14 SP_RST AXN-10-12 TS_IDX_ACCESS AXN-4-10 SP_START_EVENT AXN-10-8 TS_IDX_JUMP AXN-4-7 SP_START_FUNC AXN-10-9 TS_IMMDT_JUMP_COND AXN-4-6 SP_STAT AXN-10-13 TS_IMMDT_JUMP_EN AXN-4-7 SP_STOP_EVENT AXN-10-8 TS_IMMDT_JUMP_SEL AXN-4-6 SP_STOP_EVENT_LIMIT AXN-10-16 TS_NEXT AXN-4-12 SP_STOP_FUNC AXN-10-8 TS_RESOLUTION AXN-4-12 BitFlow, Inc.
  • Page 353 WR_ON_FULL AXN-3-20 Z_OPEN_TRIG_SEL AXN-2-21 Z_SIZE AXN-2-24 Z_SIZE_MSB AXN-2-26 Z_SYNC AXN-2-22 X_ACQ_COUNT AXN-2-48 Z_WIN_CON AXN-2-19 X_ACQ_COUNT_CLR_MODE AXN-2-48 Z_WIN_DIM AXN-2-23 X_ACQ_COUNT_UPD_MODE AXN-2-48 Z_WIN_DIM_EX AXN-2-25 X_ACQUIRED AXN-2-47 X_OFFS AXN-2-38 X_SHIFT AXN-2-40 X_SHIFT_DIR AXN-2-40 X_SIZE AXN-2-38 X_SIZE_MSB AXN-2-40 X_WIN_DIM AXN-2-37 X_WIN_DIM_EX AXN-2-39 BitFlow, Inc.
  • Page 354 The Cyton-CXP CYT-IX-8 BitFlow, Inc. Version Pre...

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