Subscribe to Our Youtube Channel
Related Manuals for AMCC UDTech Taishan440GX
Summary of Contents for AMCC UDTech Taishan440GX
- Page 1 Evaluation Board UDTech Taishan440GX User’s Manual Technical Support: taishansupport@amcc.com Document Issue 1.04 August, 2007...
- Page 2 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual...
- Page 3 UDTech is trademark of Beijing UD Technology Co., Ltd. PowerPC is a trademark of International Business Machines, Inc. AMCC is a registered trademark of Applied Micro Circuits Corporation. Spansion is trademarks of Spansion, LLC. All other names and trademarks are the property of their respective owners and are hereby acknowledged.
- Page 4 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Revision History Revision Date Comment 2006-07-18 Generated Document. 2007-07-18 Modified PLB clock to 200MHz. 2007-8-20 Modified the 200MHz parameter of DDR controller 2007-8-23 Modified the EEPROM byte 3 to 0x87...
-
Page 5: Table Of Contents
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Contents ..............................5 ONTENTS ............................7 IST OF IGURES ............................8 IST OF ABLES 1 Board Architecture................9 ......................... 11 OARD LOCKING ........................11 TRAPPING PTIONS DDR SDRAM D ........................13 ESIGN PCI BUS ............................ - Page 6 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 6 Displays ..................35 7 Connectors ...................36 ..................... 37 XPANSION NTERFACE ONNECTOR IIC C ..........................38 ONNECTOR SPI C ..........................38 ONNECTOR JTAG D ...................... 39 EBUGGER ONNECTOR RISCT ......................40 RACE ONNECTOR ......................
-
Page 7: List Of Figures
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual List of Figures Figure 1-1. Board architecture……………………………………………………………………………. 9 Figure 1-2. Top view board layout……………………………………………………………………….. 10 Figure 1-3. Clock architecture of the board ……………………………………………………….…… .11 Figure 1-4. SW3 factory fault setting (strapping option F) ………………………………………………13 Figure 1-5. - Page 8 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual List of Tables Table 1-1. Board Strapping Options………………………………………………………………………12 Table 1-2. SW3 Switch Settings……………………………………………………………………………13 Table 1-3. SW1 Switch Settings …………………………………………………………………………..14 Table 1-4. Chip Select Usage ……………………………………………………………………………..16 Table 1-5. CPLD Registers Address Assignment………………………………………………………….16 Table 1-6.
-
Page 9: Board Architecture
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 1 Board Architecture The PPC440GX contains a high-performance RISC processor core, DDR SDRAM controller, PCI-X bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Utilizing this processor, features of the board include 256MB SDRAM, 64MB flash for boot and application, an IIC serial EEPROM stored the strap configuration data, two 64-bit PCIX slots, a expansion interface connector (EBC connector), built-in Ethernet support, a 16X2 character LCD module, a CPLD, two serial ports, and a IIC serial Temperature... -
Page 10: Figure 1-2. Top View Board Layout
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Figure 1-2 shows the top view board layout, the figure shows the headers unpopulated. Figure 1-2. Top view board layout... -
Page 11: Board Clocking
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 1.1 Board Clocking The clock architecture of the board is illustrated in figure 1-3. Note that the clock PLL is reset only at board power-on, not by any other reset source. MUX via 22 ohm PPC440GX 33MHZ OSC... -
Page 12: Table 1-1. Board Strapping Options
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 1-1. Board Strapping Options UART0_D UART0_ GMC1TX Option DSR# Strapping Option A SysClk - 33 MHz VCO - 1000 MHz CPU - 500 MHz PLB - 166 MHz OPB - 83 MHz PerClk - 83 MHz Boot ROM Location - EBC Boot width - 16 bit... -
Page 13: Ddr Sdram Design
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Strapping Option F IIC Bootstrap controller enabled, serial ROM address 0b1010000; The default configuration is 800MHz CPU and 200MHz PLB. Please refer to the table 3-1. Table 1-2. SW3 switch settings Switch Description BOOT_CFG0, the CPU strapping pin UART0_DCD#... -
Page 14: Pci Bus
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 1.4 PCI BUS The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. -
Page 15: Ethernet Design
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Figure 1-5. SW1 Factory Default Setting 1.5 Ethernet Design The board provides two 10/100/1000Base-T Ethernet ports, with auto negotiation to 10/100Base-T when connected to networks not capable of 1000Mbps operation. Ethernet support through the Media Access Control (MAC) layer is provided in the PPC440GX chip. -
Page 16: Character Lcd Module
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 1-4. Chip Select Usage CS[4:0] Usage Comment PerCS0 Flash 64MB PerCS1 CPLD PerCS2 LCD module PerCS4 EBC connector 2 x 50 Header … PerCS7 1.7 16x2 Character LCD module The 16X2 character LCD module (LCM) is provided on the board. -
Page 17: Table 1-7. Cpld Register Switch(0:7) Usage
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 1-7. CPLD Register SWITCH(0:7) Usage D[7:0] usage Default Comment Reserved User switch 1 User switch 2 User switch 3 User switch 4 Table 1-8. CPLD Register CTL(0:7) Usage D[7:0] usage Default Comment... -
Page 18: Gpio Usage
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual GPIO Usage The PPC440GX has one 32-bit GPIO controller. GPIO provides 32 user-programmable external signals, multiplexed with system-related signal groups including trace outputs, external interrupt inputs, UART interface signals, IIC bus interface signals, and Ethernet MAC interface signals. Table 1-10 shows the GPIO usage. -
Page 19: Serial Eeprom
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 1.10 Serial EEPROM The Serial EEPROM (sEEPROM) used on the board is the ATMEL semiconductor AT24C02B. The AT24C02B provides 2048 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. -
Page 20: Spi Port Support
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 1.14 SPI Port Support A 1x5 header connector is provided on GPIOs. See Table 1-10, “GPIO Usage” Table 7-4 SPI Connector Pin Assignment, for more details. 1.15 Serial Port Two serial ports, software compatible with 16750, are included in the PPC440GX chip. UART 0 provides a full set of modem control lines. -
Page 21: Ppc440Gx Processor Power
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 1.17 PPC440GX Processor Power The PPC440GX chip requires four voltages, +1.55V, +3.3V, +2.5V, +1.25V. In this board design, all voltages are derived from the +5V input (+5V input of ATX or +5V power adapter). There are separate DC-DC voltage regulators for each voltage. -
Page 22: Memory Map
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 2 Memory Map Table 2-1 summarizes address space assignment on the board. Table 2-1. PPC440GX Address Space assignment Function Subfunction Start Address End Address Size 0x0 0000 0000 0x0 0FFF FFFF 256MB Local DDR SDRAM... - Page 23 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 2-1. PPC440GX Address Space assignment (continued) Function Subfunction Start Address End Address Size PCI-X Reserved 0x2 0000 0000 0x2 07FF FFFF PCI-X I/O 0x2 0800 0000 0x2 0BFF FFFF 64MB Reserved 0x2 0C00 0000...
-
Page 24: Programming The Ppc440Gx
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 3 Programming the PPC440GX This chapter provides guidance on programming the PPC440GX to work with the board design. 3.1 PLL Configuration On this board, the PCI clock is determined by the CPLD during power-on reset. The input reference clock, SysCLk, derives from 33.33MHz OSC. - Page 25 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 3-2. Bootstrap Configuration (continued) Serial Device Strap Strapping option Description Register bit field (EEPROM) SDR0_SDSTP0[FWDVB] PLL Forward Divisor B 101 PLL Forward Divisor B = 4 SDR0_SDSTP0[PRBDV0] PLL Primary Divisor B 001 PLL Primary Divisor B = 1 Note: Reset value for PLL Primary Divisor A is 1.
-
Page 26: Ddr Sdram Bank 0
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 3-2. Bootstrap Configuration (continued) Serial Device Strap Strapping option Description Register bit field (EEPROM) SDR0_SDSTP1[RMII] RMII Mode 1 RMII 10 Mb SDR0_SDSTP1[TRE] GPIO Trace Enable 1 GPIO 18-31 are disabled SDR0_SDSTP1[Nto1] CPU:PLB N to 1 clock ratio 0 CPU:PLB ratio N to X where X is 1... -
Page 27: Table 3-5. Ddr Sdram Timing Register 1 - Sdram0_Tr1 (Offset 0X81)
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 3-4. DDR SDRAM Timing Register 0 - SDRAM0_TR0 (offset 0x80) 200MHz (continued) Initial Field Value Description 16:17 SDLD Command leadoff (2 CLK). 0xC18A 40BE 18:23 xxxxxx Reserved. (0xC10A 401A 166MHz) TWTR Write-to-read command (1 selects Twtr of... -
Page 28: Table 3-8. Refresh Timer Register - Sdram0_Rtr (Offset 0X30)
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 3-7. DDR SDRAM Bank 0 Configuration Register - SDRAM0_B0CR (offset 0x40) 200MHz (continued) Initial Field Value Description 0x000C 4001 Reserved. 16:18 SDAM Addressing mode (mode 3). 19:30 xxxxxxxxxx Reserved. SDBE Memory bank enable. -
Page 29: Peripheral Bus Timings
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 3.4 Peripheral Bus Timings The following timings all assume that the peripheral bus frequency is 83MHz. At lower bus frequencies, these timings should still work, though with sub-optimum throughput. The EBC0_CFG register is same setting for eight Peripheral banks. Table 3-11 shows register EBC0_CFG setting. -
Page 30: Peripheral Bank 0
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 3.4.1 Peripheral Bank 0 The flash, 64MB, is attached to bank 0. Table 3-12 shows Peripheral bank 0 register EBC0_B0CR settings. Table 3-13 shows Peripheral bank 0 register EBC0_B0AP settings. Table 3-12. -
Page 31: Peripheral Bank 1
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 3.4.2 Peripheral Bank 1 The CPLD is attached to bank 1. Table 3-14 shows Peripheral bank 1 register EBC0_B1CR settings. Table 3-15 shows Peripheral bank 1 register EBC0_B1AP settings. Table 3-14. Peripheral Bank 1 Configuration Register EBC0_B1CR (offset 0x01) Initial Field Value... -
Page 32: Peripheral Bank 2
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 3.4.3 Peripheral Bank 2 The LCM is attached to bank 2. Table 3-16 show Peripheral bank 2 register EBC0_B2CR settings. Table 3-17 show Peripheral bank 2 register EBC0_B2AP settings. Table 3-16. Peripheral Bank 2 Configuration Register EBC0_B2CR (offset 0x02) Initial Field Value... -
Page 33: Reset And Interrupts
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 4 Reset and Interrupts Reset is generated at power-on, by the reset pushbutton, by system-reset from the PPC440GX or by under voltage on either the +5V or +3.3V supplies. There are 11 external interrupt inputs to the PPC440GX. They are multiplexed with GPIOs. More detail about these interrupts is given in Table 1-10, “GPIO Usage”. -
Page 34: Switches
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 5 Switches The board contains a reset switch and a 4-position slide switch for testing. Additionally, the board contains two 4-position slide switches for CPU strapping and PCI clock configuration. Table 5-1 shows the switch list. -
Page 35: Displays
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 6 Displays The LED displays provided on the board are described in Table 6-1. Table 6-1. Displays Name Location Color Description Lights when the PPC440GX SYS_ERROR System error signal is asserted. User LED1 Green User programmable LED1. -
Page 36: Connectors
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 7 Connectors The connector types and pin usage for board connectors are described in the following sections. Table 7-1 shows the connector list. Table 7-1. Connector List Location Description EBC connector Serial port 0 connector CPLD JTAG Port IIC connector... -
Page 37: Expansion Interface Connector
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 7.1 Expansion Interface Connector User logic may be placed on a daughter card attached to the Expansion Interface connector. The pin usage of the connector is described in Table 7-2. Refer to the board schematic for the definitions of each of the signal names in the table. -
Page 38: Iic Connector
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 7-2. Expansion Interface Connector Pin Assignment (continued) Signal name Signal name EBC_D20 PER_BE3# EBC_D19 PER_PAR0 EBC_D18 PER_ PAR1 EBC_D17 PER_ PAR2 EBC_D16 PER_ PAR3 PER_ERR DMAREQ0 HOLDREQ DMAACK0 HOLDACK EOT0 EXTREQ# PER_READY... -
Page 39: Jtag Debugger Connector
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual Table 7-4. SPI Connector Pin Assignment Signal name SPI_SCLK +3.3V SPI_DI SPI_DO 7.4 JTAG Debugger Connector The JTAG debugger connects to the board through a 2x8-pin header. Pin usage is described in Table 7-5. Table 7-5. -
Page 40: Risctrace Connector
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 7.5 RISCTrace Connector The RISCTrace feature connects to the board through a 2x10-pin header. Pin usage is described in Table 7-6. Table 7-6. RISCTrace Connector Pin Assignment Signal name Signal name Capacitor to GND TRCCLK HALT#... -
Page 41: Serial Port Connector
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 7.6 Serial Port Connector Two serial ports are included on the board. Pin usage is described in Table 7-7. Table 7-7. Serial port Connector Pin List Signal name Serial 1 Serial 0 Comment √... -
Page 42: Pcix Connector
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 7.8 PCIX Connector PCIX slot is a standard connector as defined by the +3.3VDC, 64-bit, 184-pin, PCI edge specification. This interface allows PCIX cards to be interfaced to the evaluation board. The pin assignment of the connector is described in Table 7-9. - Page 43 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual C/BE2# +3.3V FRAME# IRDY# +3.3V TRDY# DEVSEL# PCIXCAP STOP LOCK# +3.3V PERR# +3.3V +3.3V +3.3V SERR# +3.3V C/BE1# AD15 AD14 +3.3V AD13 AD12 AD11 AD10 M66EN C/BE0# +3.3V +3.3V +3.3V(I/O) +3.3V(I/O) ACK64# REQ64#...
- Page 44 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual AD53 +3.3V(I/O) AD52 AD51 AD50 AD49 +3.3V(I/O) AD48 AD47 AD46 AD45 AD44 AD43 AD42 AD41 +3.3V(I/O) AD40 AD39 AD38 AD37 +3.3V(I/O) AD36 AD35 AD34 AD33 AD32 Reserved Reserved Reserved Reserved...
-
Page 45: Board Dimension
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 8 Board Dimension Figures 8-1 shows the dimension for the evaluation board. Figure 8-1. The evaluation board dimension... -
Page 46: Cpld Programming
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual 9 CPLD Programming The following section contains CPLD code listing and the related registers refer to section 1.10, “CPLD”. Figure 9-1. CPLD code listing --*****************************************************************************-- CPLD for the Taishan440GX Evaluation Board Ver10 --*****************************************************************************-- --************ CPU R/W PORT, CPU STRAPPING, CONTROL SIGNALS ***************-- --*****************************************************************************--... - Page 47 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual USER_DIP2 : IN STD_LOGIC; USER_DIP3 : IN STD_LOGIC; 16245 BIDIRECTIONAL TRANSCEIVER CONTROL SIGNALS PER_RW : IN STD_LOGIC; EXTREQ : IN STD_LOGIC; PER_CS2 : IN STD_LOGIC; PER_CS3 : IN STD_LOGIC; PER_CS4 : IN STD_LOGIC;...
- Page 48 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual BOOT_CFG2 : IN STD_LOGIC; UART0_DCD : OUT STD_LOGIC; -- TRI-STATE OUTPUT UART0_DSR : OUT STD_LOGIC; -- TRI-STATE OUTPUT GMC1TXCTL_BOOT : OUT STD_LOGIC; -- TRI-STATE OUTPUT -- UART1 SIGNALS MULTIPLEXING UART1_RTS_DTR : IN STD_LOGIC;...
- Page 49 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual SIGNAL UART1Flow_CTL : STD_LOGIC; SIGNAL LCM_E_TMP1,LCM_E_TMP2,LCM_E_TMP3,LCM_E_TMP4 : STD_LOGIC; SIGNAL PER_CS2_TMP1,PER_CS2_TMP2,PER_CS2_TMP3 : STD_LOGIC; SIGNAL EXTREQ_TMP : STD_LOGIC; SIGNAL EBC_EN : STD_LOGIC; COMPONENT EN_GEN PORT : IN STD_LOGIC; : OUT STD_LOGIC; : OUT STD_LOGIC END COMPONENT;...
-
Page 50: Per_Rw
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual -- CLOCKING --TMR_CLK <= CPLD_CLK; 16245 CONTROL PROCESS (BOARD_RESET,PER_CLK) BEGIN IF BOARD_RESET = '0' THEN PER_CS2_TMP1 <= '1'; PER_CS2_TMP2 <= '1'; PER_CS2_TMP3 <= '1'; ELSIF PER_CLK'EVENT AND PER_CLK = '1' THEN PER_CS2_TMP1 <= PER_CS2;... -
Page 51: Pcix Capability Detecting And Clocking Configuration
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual PROCESS (BOARD_RESET,PER_CLK) BEGIN IF BOARD_RESET = '0' THEN LCM_E <= '0'; ELSIF PER_CLK'EVENT AND PER_CLK = '1' THEN LCM_E <= LCM_E_TMP4; END IF; END PROCESS; SYSERR_N, SYSTEM ERROR LED INDICATOR SYSERR_N <= NOT SYSERR;... -
Page 52: Pci_Clk_S1
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual END PROCESS; PROCESS(CPLD_CLK) BEGIN IF CPLD_CLK'EVENT AND CPLD_CLK = '1' THEN IF EN = '1' THEN SEL(0) <= PCIXCAP; END IF; END IF; END PROCESS; PROCESS(CPLD_CLK) BEGIN IF CPLD_CLK'EVENT AND CPLD_CLK = '1' THEN IF ENN = '1' THEN SEL(1) <= PCIXCAP;... -
Page 53: Pci_M66En
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual WHEN "00" => PCI_CLK_S1_TMP <= '0'; PCI_CLK_S0_TMP <= PCI_M66EN; WHEN "01" => PCI_CLK_S1_TMP <= '0'; PCI_CLK_S0_TMP <= '1'; WHEN "10" => PCI_CLK_S1_TMP <= '0'; PCI_CLK_S0_TMP <= '0'; WHEN "11" => PCI_CLK_S1_TMP <= PCI_CLK_S1_CFG_N; PCI_CLK_S0_TMP <= PCI_CLK_S0_CFG_N;... -
Page 54: Cpu Strapping
Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual IF PER_CS1 = '0' AND PER_WE = '0' AND PER_A(29 TO 31) = "010" THEN CTL(4) <= PER_D(4); CTL(5) <= PER_D(5); CTL(6) <= PER_D(6); CTL(7) <= PER_D(7); END IF; END IF; END PROCESS;... - Page 55 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual GMC1TXCTL_BOOT <= BOOT_CFG2; ELSE UART0_DCD <= 'Z'; UART0_DSR <= 'Z'; GMC1TXCTL_BOOT <= 'Z'; END IF; END PROCESS; END RTL; COMPONENT EN_GEN __PCIXCAP DETECT PULSE GENERATE LIBRARY ieee; USE ieee.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all;...
- Page 56 Beijing UD Technology Co., Ltd. Taishan440GX Evaluation Board User’s Manual PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN IF SCLR = '1' THEN COUNT_OUT <= (OTHERS => '0'); ELSE COUNT_OUT <= COUNT_OUT + 1; END IF; END IF; END PROCESS; COUT <= '1' WHEN COUNT_OUT = (0 TO 7 =>...
Need help?
Do you have a question about the UDTech Taishan440GX and is the answer not in the manual?
Questions and answers