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Low Noise Integer-N PLL with Integrated VCO
n
Output Jitter:
n
90fs RMS (12kHz to 20MHz)
n
115fs RMS (ADC SNR Method)
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Noise Floor = –165dBc/Hz at 250MHz
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EZSync™, ParallelSync™ Multichip Synchronization
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SYSREF Generation for JESD204B, Subclass 1
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Output Frequency Range:
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1.95MHz to 2.5GHz (LTC6951)
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2.1MHz to 2.7GHz (LTC6951-1)
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–229dBc/Hz Normalized In-Band Phase Noise Floor
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–277dBc/Hz Normalized In-Band 1/f Noise
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Five Independent, Low Noise Outputs
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Reference Input Frequency up to 425MHz
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LTC6951Wizard™ Software Design Tool Support
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–40°C to 105°C Operating Junction Temperature Range
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applicaTions
High Performance Data Converter Clocking
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Wireless Infrastructure
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Test and Measurement
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Typical applicaTion
1µF
0.01µF
100MHz
1µF
1µF
REF OSC
+
REF
–
REF
50
1µF
LTC6951
CMA
CMB
CMC
TB
BB
1µF
BVCO
470nF
1µF
SYNC
SYNC
CONTROL
STAT
TO/FROM
CS
PROCESSOR
SCLK
SERIAL
PORT
SDI
SDO
3.3V
10
1µF
0.01µF
+
+
V
V
CP
R DIVIDER
PHASE
CHARGE
FREQUENCY
PUMP
DETECTOR
N DIVIDER
P DIVIDER
D0
M0
DELAY
DIV
D1
M1
DELAY
DIV
D2
M2
DELAY
DIV
D3
M3
DELAY
DIV
D4
M4
DELAY
DIV
GND
For more information
Multioutput Clock Synthesizer
with Integrated VCO
DescripTion
The
LTC
6951
is a high performance, low noise, Phase
®
Locked Loop (PLL) with a fully integrated VCO. The low
noise VCO uses no external components and is internally
calibrated to the correct output frequency with no external
system support.
The clock generation section provides five outputs based
on the VCO prescaler signal with individual dividers for
each output. Four outputs feature very low noise, low skew
CML logic. The fifth output is low noise LVDS. All outputs
can be synchronized and set to precise phase alignment
using the programmable delays.
Choose the LTC6951-1 if any desired output frequency
falls in the ranges 2.5GHz to 2.7GHz, 1.66GHz to 1.8GHz,
or 1.25GHz to 1.35GHz. Choose the LTC6951 for all other
frequencies.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
EZSync, LTC6951Wizard and ParallelSync are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 8319551 and 8819472.
5V
0.01µF
1µF
+
V
VCO
63.4
CP
63.4
820pF
1.2nF
68nF
TUNE
0.1µF
+
OUT0
–
OUT0
TO LTC2107
100
+
OUT1
0.1µF
–
OUT1
+
OUT2
TO ADC
–
OUT2
OR DAC
+
OUT3
–
OUT3
+
OUT4
–
TO FPGA
OUT4
6951 TAO1a
www.linear.com/LTC6951
LTC6951
Ultralow Jitter
SNR vs Input Frequency of
LTC6951 Clocking an LTC2107,
f
= 210Msps, A
= –3dBFS
S
IN
82
80
78
76
74
72
70
68
66
NOTE 12
64
LTC2107 APERTURE JITTER
= 45f
RMS
S
LTC6951 JITTER
=115f
RMS
S
62
0
100 200 300 400 500 600 700 800
INPUT FREQUENCY (MHz)
6951 TAO1b
6951fa
1
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Related Manuals for Linear Technology LTC6951
Summary of Contents for Linear Technology LTC6951
- Page 1 L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync, LTC6951Wizard and ParallelSync are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, High Performance Data Converter Clocking including 8319551 and 8819472.
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Page 2: Absolute Maximum Ratings
LTC6951 absoluTe MaxiMuM raTings pin conFiguraTion (Note 1) TOP VIEW Supply Voltages ) to GND ......3.6V to GND ..........5.5V 40 39 38 37 36 35 34 33 Voltage on CP Pin ....GND – 0.3V to V + 0.3V – Voltage on all other Pins ...GND – 0.3V to V + 0.3V... -
Page 3: Electrical Characteristics
REFOK = 0, PDREFPK = 0 10MHz ≤ f ≤ 425MHz, Sine Wave Input Resistance Differential kΩ Input Capacitance Differential Frequency Range LTC6951 (Note 3) LTC6951-1 (Note 3) Tuning Sensitivity (Notes 3, 4) 2.5 to 3.7 %Hz/V Phase/Frequency Detector (PFD) Input Frequency Charge Pump (CP) - Page 4 , OUT1 , OUT1 , OUT2 , OUT2 , OUT3 , OUT3 ), Differential Termination = 100Ω Unless Otherwise Noted LTC6951 Output Frequency 1.95 2500 /2 Subharmonic Generated, 1667 2000 P = 2.5, Mx = 1 (Note 16) /2 Subharmonic Generated,...
- Page 5 MC4[1:0] = 2 –21 MC4[1:0] = 3 –34 SYNC = V or SSYNC = 1 Phase Noise and Spurious LTC6951 VCO Phase Noise 10kHz Offset –87 dBc/Hz = 4.0GHz, f = 2.0GHz, P = 2, M0 = 1, OUT0 100kHz Offset –113...
- Page 6 = 25°C (Note 2). V = 3.3V, V = 5V unless otherwise specified. All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS UNITS LTC6951 VCO Phase Noise 10kHz Offset –83 dBc/Hz = 5.0GHz, f = 2.5GHz, P = 2, M0 = 1, OUT0 100kHz Offset –110...
- Page 7 Note 3: Valid for 1.50V ≤ V(TUNE) ≤ 2.85V with part calibrated after a power cycle or software power-on-reset (POR). Note 15: Measured using differential LTC6951 outputs driving LTC6954. LTC6954 provides differential to single-ended conversion for rejection of Note 4: Based on characterization.
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Page 8: Typical Performance Characteristics
LTC6951 Typical perForMance characTerisTics + = 25°C. V = V = V = V = 3.3V, = V = 5V, Unless otherwise noted. Charge Pump Hi-Z Current vs REF Input Sensitivity vs REF Input Signal Detected vs Frequency Frequency, Temperature Voltage, Temperature –25 –30 –35 –40 –45... - Page 9 LTC6951 Typical perForMance characTerisTics + = 25°C. V = V = V = V = 3.3V, = V = 5V, Unless otherwise noted. LTC6951 CML Differential Output LTC6951-1 CML Differential Output LTC6951 CML Differential Output at 2.5GHz at 2.7GHz at 1.25GHz –0.1 –0.1 –0.1 –0.2 –0.2 –0.2...
- Page 10 6951 G16 6951 G17 6951 G18 Normalized In-Band Phase Noise LTC6951 VCO Phase Noise at LTC6951-1 VCO Phase Noise at Floor vs CP Current CML Outputs, P = 2, Mx = 1 CML Outputs, P = 2, Mx = 1 –224...
- Page 11 Typical perForMance characTerisTics + = 25°C. V = V = V = V = 3.3V, = V = 5V, Unless otherwise noted. LTC6951-1 Phase Noise at CML Spurious Response Spurious Response Outputs, f = 5.4GHz, P = 2, Mx = 1, = 1250MHz, f = 100MHz, = 500MHz, f = 100MHz, 2 and 4 = 100MHz, Loop BW = 340kHz...
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Page 12: Pin Functions
LTC6951 pin FuncTions – (Pins 1, 4, 7, 10, 13, 16): 3.15V to 3.45V OUT4 , OUT4 (Pins 14, 15): LVDS Output Signals. The Positive Supply Pins for Output Dividers, SYNC Function M4 output divider is buffered and presented differentially and Serial Port. - Page 13 LTC6951 pin FuncTions CP (Pin 34): Charge Pump Output. This bidirectional current GND (Pins 25, 29, Exposed Pad Pin 41): Negative Power output is normally connected to the external loop filter. Supply (Ground). These pins should be tied directly to the See the Applications Information section for more details.
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Page 14: Block Diagram
PEAK DETECTOR B DIV CAL, ALC BVC0 N DIV CONTROL ÷2 TO 1023 TUNE P DIV LTC6951: 4GHz TO 5GHz ÷2, 2.5, 3, 3.5, 4 LTC6951-1: 4.3GHz TO 5.4GHz – OUT0 D0 DELAY M0 DIV OUT0 0 TO 255 SYNC... -
Page 15: Timing Diagrams
RLVDS FLVDS 6951 TD03 OUT4 6951 TD01 operaTion The LTC6951 is a high-performance integer-N PLL, com- plete with a low noise VCO. Its multi-output clock generator BIAS incorporates Linear Technology’s proprietary EZSync and LOWPASS 1.9V ParallelSync standards, allowing synchronization across 2.1k... - Page 16 LTC6951 operaTion LVPECL LTC6951 LVPECL OR – 50 SOURCE LTC6951 DIFFERENTIAL LVPECL – SINGLE-ENDED LVPECL OR 50 SOURCE LTC6951 – DIFFERENTIAL CML CMOS LTC6951 CMOS – 3.3V LVDS LTC6951 1.8V – SINGLE-ENDED CMOS 6951 F02 DIFFERENTIAL LVDS Figure 2. Common Reference Input Interface Configurations. All Z Signal Traces Are 50Ω...
- Page 17 LTC6951 operaTion REFERENCE ALIGNED OUTPUT (RAO) The RAO bit (register h03) controls the fundamental con- shows the operation of the SN bit. Table 5 is a brief de- figuration of the PLL. Figure 3 shows the PLL loop diagram scription of the SR and SN functions. See the ParallelSync with bit RAO set to “0”, which is the power-up default.
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Page 18: Lock Indicator
LTC6951 operaTion REFERENCE DIVIDER (R) the CPRST bit which prevents UP and DOWN pulses from being produced. See Figure 6 for a simplified schematic A 6-bit divider is used to reduce the frequency seen at the of the PFD. PFD. Its divide ratio R may be set to any integer from 1 to 63. - Page 19 LTC6951 operaTion The PFD phase difference must be less than t for the CHARGE PUMP (CP) COUNTS number of successive counts before the lock The charge pump, controlled by the PFD, forces sink indicator asserts the LOCK flag. The LKCT[1:0] bits are (DOWN) or source (UP) current pulses onto the CP pin, used to set COUNTS depending upon the application.
- Page 20 7.2 to 9.6 The integrated VCO operates from 4GHz to 5GHz for the 9.6 to 14 LTC6951 and 4.3GHz to 5.4GHz for the LTC6951-1. The 14 to 19 frequency range of the VCO, coupled with the output pres- 19 to 29...
- Page 21 LTC6951 operaTion The relationship between bits BD[3:0], the B value, and It is recommended to set AUTOCAL = 0 in this mode the N value for RAO = 1 is shown in Table 11. and to calibrate the VCO by setting CAL = 1 after all the appropriate registers have been written.
- Page 22 (40% and 57%, respectively) and a large subharmonic spurious Table 17. MC0[1:0] Programming output. In systems where the LTC6951 output drives into MC0[1:0] DESCRIPTION a frequency divider of at least 2 (as in some ADCs), the Do not mute output on VCO CAL.
- Page 23 MC1[1:0], MC2[1:0], and MC3[1:0] to 2. See Figure 9 for OUTPUT SYNCHRONIZATION (SYNC) circuit details and the Applications Information section for The LTC6951 has circuitry to allow the outputs to be syn- common interface configurations. chronized into known phase alignment in several different...
- Page 24 SR or SN = 1, in which case the SSYNC bit is inactive). DLY0[7:0] D0 delay setting for the M0 divider (RAO = 0). Internal to the LTC6951, the SYNC pin’s signal and the DLY1[7:0] D1 delay setting for the M1 divider.
- Page 25 LTC6951 operaTion The internal synchronization signal is controlled by the 1ms • f ⎛ ⎞ REFCYCLES = R • CEILING settings of RAO and SN. If either bit is “0” the internal ⎝ ⎜ ⎠ ⎟ synchronization falling edge is delayed by at least 25µs to meet the requirements of EZSync.
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Page 26: Serial Port
(Hi-Z) when CS is high, or when data is Communication Sequence not being read from the part. If the LTC6951 is not used in a multidrop configuration, or if the serial port master The serial bus is composed of CS, SCLK, SDI, and SDO. - Page 27 LTC6951 operaTion Single Byte Transfers The serial port is arranged as a simple memory map, with Figure 17 shows an example of two write communication status and control available in 20, byte-wide registers. All bursts. The first byte of the first burst sent from the serial data bursts are comprised of at least two bytes.
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Page 28: Multidrop Configuration
6951 F19 Figure 19. Serial Port Auto-Increment Read Multiple Byte Transfers Once the LTC6951 detects a read burst, it takes SDO out of the Hi-Z condition and sends data bytes sequentially, More efficient data transfer of multiple bytes is accom- beginning with data from register ADDRX. The part ignores plished by using the LTC6951’s register address auto-... -
Page 29: Serial Port Registers
LTC6951 operaTion Serial Port Registers The memory map of the LTC6951 may be found below in The read-only register at address h00 is used to determine Table 20, with detailed bit descriptions found in Table 21. different status flags. These flags may be instantly output The register address shown in hexadecimal format under on the STAT pin by configuring register h01. - Page 30 LTC6951 operaTion Table 21. Serial Port Register Bit Field Summary BITS DESCRIPTION DEFAULT ADDR BITS DESCRIPTION DEFAULT ADDR ALCCAL Auto enable ALC during CAL operation MD4[3:0] M4 Divider value ALCEN Always enable ALC (override) MUTE0 Mute OUT0 (only valid if RAO = 0)
- Page 31 Block Power-down Control STAT Output The LTC6951’s power-down control bits are located in The STAT output pin is configured with the x[6:0] bits and register h02, described in Table 21. Different portions of INVSTAT of register h01. These bits are used to bit-wise the device may be powered down independently.
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Page 32: Output Frequency
LTC6951 applicaTions inForMaTion INTRODUCTION OUTPUT FREqUENCY A PLL is a complex feedback system that may conceptually When the loop is locked, the frequency f (in Hz) pro- be considered a frequency multiplier. The system multiplies duced at the output of the VCO when RAO = 0 is determined ±... -
Page 33: Output Delays
The PFD frequency f is given by the following equation: LOOP FILTER DESIGN A stable PLL system requires care in designing the external loop filter. The Linear Technology LTC6951Wizard appli- cation, available from http://www.linear.com/software/, and f with RAO = 0 may be alternatively expressed as: aids in design and simulation of the complete system. - Page 34 = 250MHz in quadrature to f Also, from Table 10 determine B: OUT1 OUT0 = 1GHz B = 384 and BD[3:0] = hB OUT2 = unused The same technique is used for the LTC6951-1, substitut- OUT3 ing f = 4.3GHz to 5.4GHz = 125MHz OUT4 RAO = 0 Selecting Loop Bandwidth...
- Page 35 π • 316k • 58.3 From Table 6 we see that LKWIN = 0 with a t of 5ns. The LTC6951 will consider the loop “locked” as long as the phase coincidence at the PFD is within 180°, as = 1.44nF 12 • π • 316k • 58.3 calculated below.
- Page 36 LTC6951 applicaTions inForMaTion R and N Divider Programming OUT0 will be considered the reference output, so the delay, D0, will be set to 0: Program registers Reg05 to Reg06 with the previously determined R and N divider values. Because the AUTOCAL Reg0A = h00...
- Page 37 LTC6951 applicaTions inForMaTion Synchronization Reg02 = h04 The outputs in this example are now running at the desired After waiting a minimum of 1ms, write Reg02 again: frequency, but have random phase relationships with Reg02 = h00 each other. Synchronization forces the outputs to run...
- Page 38 Simple synchronization of multiple cascaded chips is accomplished by driving each chip’s SYNC pin with a Since the LTC6951 is a clock generator, it is defined as a common CMOS signal. There are no precision timing CONTROLLER for EZSync. Any EZSync part wired to any 3.3V...
- Page 39 = 1GHz OUT2 Additionally the goal is for OUT0, OUT1 and OUT4 of the LTC6951 to be synchronized to OUT0, OUT1 and OUT2 of the LTC6954-1. EZSync defines OUT0, OUT1 and OUT4 of the LTC6951 as follower-synchronous and OUT2 of the LTC6951 as a follower-driver.
- Page 40 Once all the registers defined above have been written and CS is driven back high, the part will initiate a CAL routine The delay settings are what the LTC6951 uses to imple- and the loop will lock. This can be monitored by reading ment each output’s mode.
- Page 41 LTC6951 applicaTions inForMaTion SYNC LTC6951 OUT0 LTC6951 OUT1 LTC6951 OUT2 7 FOLLOWER-DRIVER CLOCK CYCLES LTC6951 OUT4 6954 LTC6954 OUT0 LTC6954 OUT1 LTC6954 OUT2 6951 F25 Figure 25. Outputs after SYNC for the EZSync Design Example Synchronization The outputs in this example are now running at the desired...
- Page 42 CMOS SYNC pulse provides the best possible jitter performance since clock synchronous to the reference input. To do this the LTC6951 path cascading is not necessary to achieve synchronization. needs to be put into Reference Aligned Output mode (bit CHIP 1 3.3V...
- Page 43 P = 2 and, by loop inference, to the R divider. This example will M0 = 8 show how to program an LTC6951 and then use the SYNC pin to create outputs which will be aligned in phase and M1 = 8 time for the system shown in Figure 26.
- Page 44 LTC6951 applicaTions inForMaTion The LTC6951Wizard uses Equations 15 through 18 to for 18 P cycles after an N divider retiming event. OUT0 calculate C and R always has a rising edge at the N divider in this mode, so OUT1 needs to be moved to the same spot with the = 65.3nF...
- Page 45 LTC6951 applicaTions inForMaTion Synchronization To get repeatable REF-to-output latency with R ≥ 2, the The outputs for all LTC6951s in this example are now SYNC pulse must be an exact number of REFCYCLES running at the desired frequency, but have random phase wide as described in Equation 2.
- Page 46 The JESD204B subclass 1 interface clocking can be accom- synchronized by the pulse (or pulse train) SYSREF. Care plished with the LTC6951 as shown in the circuit example must be taken to make sure the SYSREF signal remains of Figure 28, utilizing two dual ADCs, an FPGA, and a 1:3 synchronized to the ADC and FPGA clocks and meets setup SYSREF buffer.
- Page 47 LTC6951 applicaTions inForMaTion For this example assume the following parameters of The same technique is used for the LTC6951-1, substitut- interest: ing f = 4.3GHz to 5.4GHz. = 61.44MHz @ 7dBm into 50Ω Selecting Loop Bandwidth = 9.6MHz OUT0 SYSREF The next step in the algorithm is choosing the open loop bandwidth.
- Page 48 LTC6951 applicaTions inForMaTion From Table 1, FILT = 0 for a 61.44MHz reference frequency. OUT4 runs the FPGA management clock which is made Next, convert 7dBm into V . For a sine wave, use the continuous by turning off synchronization and not muting P–P...
- Page 49 PDBUFFER pulses may be turned off once lane alignment is achieved The delay time in the LTC6951 for Dx = 1 is: to save power and reduce possible beat frequencies in the system. To keep SYSREF synchronized to the ADC and = 406.9ps...
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Page 50: Phase Noise
In-band phase noise at very low offset frequencies may VCO’s tune line, or into other loop filter signals. Example be influenced by the LTC6951’s 1/f noise, depending upon suggestions are the following. . Use the normalized in-band 1/f noise L of –277dBc/... - Page 51 100Ω in series with the refer- provided below. ence output before being applied to the transmission line, and loaded with 50Ω to GND as close to the LTC6951 as http://www.linear.com/docs/14077 possible. See Reference Source Considerations above.
- Page 52 LTC6951 applicaTions inForMaTion SINE WAVE BITS INPUT SIGNAL SAMPLING CLOCK SINE WAVE SINE WAVE SINE WAVE INPUT SIGNAL WITH INPUT SIGNAL WITH INPUT SIGNAL WITH NOISELESS AMP NOISY AMP NOISELESS AMP ∆V = V ∆V = V SAMPLE ERROR ERROR...
- Page 53 LTC6951 applicaTions inForMaTion It is important to note that the frequency of the analog requirement for a given input signal or the expected input signal determines the sample clock’s jitter require- SNR performance for a given sample clock jitter. ment. The actual sample clock frequency does not matter.
- Page 54 (28) J(TOTAL) 2πf the sample clock input having a different common mode input voltage than the LTC6951’s CML outputs. Most ADC Assuming the inherent aperture jitter of the ADC (t ) is applications will require AC coupling to convert between...
- Page 55 Figure 40 shows DC-coupled and AC-coupled output to a spectrum analyzer to correctly measure the spurious configurations for the LVDS output OUT4. energy. An example of this technique using the LTC6951 as the clock generator and an LTC6954 as the limiter is OUT4 LVDS OR ADCs shown in Figure 41.
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Page 56: Typical Applications
LTC6951 Typical applicaTions 6951fa For more information www.linear.com/LTC6951... - Page 57 LTC6951 Typical applicaTions 6951fa For more information www.linear.com/LTC6951...
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Page 58: Package Description
LTC6951 package DescripTion Please refer to http://www.linear.com/product/LTC6951#packaging for the most recent package drawings. UHF Package 40-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1951 Rev Ø) 0.70 ±0.05 5.50 ±0.05 5.60 ±0.05 4.10 ±0.05 3.60 ±0.05 3.50 REF... -
Page 59: Revision History
Charge Pump Function and Current Programming section changed to CP[2:0] 6951fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- For more information www.linear.com/LTC6951... -
Page 60: Typical Application
DELAY PORT OUT4 – TO FPGA OUT4 DELAY 6951 TAO4a LTC6951 OUT0 Phase Noise = 250MHz, P = 2, Mx = 8 OUT0 LTC6951 JESD204B Subclass 1 –100 Clock and SYSREF NOTES 9, 12 JITTER = 79fs (12kHz to 20MHz) –110...
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