Oki MSM9566 User Manual
  1. Manuals
  2. Brands
  3. Oki Manuals
  4. Modulator
  5. MSM9566
  6. User manual
Oki MSM9566 User Manual

Oki MSM9566 User Manual

Ic for fm multiplex data demodulation
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
¡
Preliminary
MSM9566
IC for FM Multiplex
Data Demodulation
(DDJ Supported)
User's Manual
[Hardware]
FIRST EDITION
ISSUE DATE: Dec. 1999
PEUL9566-01

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MSM9566 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Summary of Contents for Oki MSM9566

  • Page 1 ¡ Preliminary MSM9566 IC for FM Multiplex Data Demodulation (DDJ Supported) User's Manual [Hardware] FIRST EDITION ISSUE DATE: Dec. 1999 PEUL9566-01...
  • Page 2 IMPORTANT NOTICE DARC (DAta Radio Channel), an FM multiplex broadcast technology, has been developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). Any manufacturer who intends to manufacture/sell products that utilize DARC technology needs to be licensed by NHK-ES.
  • Page 3 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration...

  • Page 4: Table Of Contents

    TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................... 1-1 2. BLOCK DIAGRAM ..................2-1 3. PIN INFORMATION ..................3-1 3.1 PIN CONFIGURATION (TOP VIEW) ............3-1 3.2 PIN DESCRIPTIONS ................... 3-2 4. ELECTRICAL CHARACTERISTICS ..............4-1 4.1 ABSOLUTE MAXIMUM RATINGS .............. 4-1 4.2 RECOMMENDED OPERATING CONDITIONS ...........
  • Page 5 - ii -...

  • Page 6: General Description

    Chapter 1 GENERAL DESCRIPTION...
  • Page 8 Radio Channel) format to obtain digital data. The MSM9566 operates at 5 V. The MSM9566 contains on one chip a band pass filter using a switched capacitor filter (SCF) and a group of circuits including frame memory, a frame synchronization circuit, and an error correction circuit.
  • Page 9 MSM9566 User’s Manual Chapter 1 GENERAL DESCRIPTION...

  • Page 10: Block Diagram

    Chapter 2 BLOCK DIAGRAM...
  • Page 12 Variable FM multiplex gain Clock Block Frame Clock Timing signal input (SCF) regeneration synchronization synchronization generator control Timer Vref Filter Section Descr- Receive SÆP FRAME Error Layer 4 CRC Data processor ambler memory correction for DDJ IC internal clock Data bus Delay Detection Section Address bus Frequency...
  • Page 13 MSM9566 User’s Manual Chapter 2 BLOCK DIAGRAM...

  • Page 14: Pin Information

    Chapter 3 PIN INFORMATION...

  • Page 16: Pin Configuration (Top View)

    MSM9566 User’s Manual Chapter 3 PIN INFORMATION PIN INFORMATION PIN CONFIGURATION (TOP VIEW) ADETIN XOUT AGND XTAL2 XTAL1 XOUTC DGND MOUT0 MOUT1 MOUT2 MOUT3 44-Pin Plastic QFP Figure 3.1 Pin Layout * Leave the NC pins (17, 39, 41, 42, 43, and 44) open.

  • Page 17: Pin Descriptions

    MSM9566 User’s Manual Chapter 3 PIN INFORMATION PIN DESCRIPTIONS Table 3.1 Pin Description Function Symbol Type Description Microcontroller Write signal to internal register. interface Read signal to internal register. Interrupt signal to microcontroller. When set to "L", an interrupt is generated.

  • Page 18: Electrical Characteristics

    Chapter 4 ELECTRICAL CHARACTERISTICS...

  • Page 20: Absolute Maximum Ratings

    MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power supply voltage –0.3 to +7.0 = DV Ta = 25°C Input voltage –0.3 to AV + 0.3 Output voltage –0.3 to DV + 0.3...

  • Page 21: Dc Characteristics

    MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS = AV = 5 V ± 10%, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Applied Pin WR, RD, 0.8 ¥...

  • Page 22: Ac Characteristics

    MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS = AV = 5 V ± 10%, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter Symbol* Condition Min. Typ. Max. Unit Applied Pin WR, CS, — —...

  • Page 23: Filter Characteristics

    MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS FILTER CHARACTERISTICS = AV = 5 V ± 10%, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Applied Pin 72 to 80 kHz...

  • Page 24: Timing Diagram

    MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS TIMING DIAGRAM Address input SWR1 HWR1 CS input SWR1 HWR1 WR input HWR2 SWR2 Data bus input Figure 4.1 Write Timing Address input CS input RD input DRD2 DRD1 Data bus output Figure 4.2 Read Timing...
  • Page 25 MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS Address input 0x29 0x2A Data bus input Layer 4 data Layer 4 data Layer 4 data CRC result IWRWR2 IWRWR3 IWRRD1 IWRRD2 Figure 4.3 Layer 4 CRC mode and Layer 4 DDJ mode Timing...
  • Page 26 MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS Address input IRDRD Figure 4.6 Intarval between read and read Address signal input 0x00 Data signal input XXXX01XX WR input (INTCLR signal) INT output DINTCLR Figure 4.7 Interrupt CLR Timing CLR signal WCLR...
  • Page 27 MSM9566 User’s Manual Chapter 4 ELECTRICAL CHARACTERISTICS...

  • Page 28: Control Registers

    Chapter 5 CONTROL REGISTERS...

  • Page 30: Operating Mode Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS CONTROL REGISTERS OPERATING MODE REGISTERS 5.1.1 Mode setting of main channel and subchannel Table 5.1.1 Main channel mode and subchannel mode Address — — — MOD_ — — — MOD_ MAIN 0x04 Initial value —...
  • Page 31 _MAIN reproduction (L1BF) Main station Frame memory Tuner switching Clock regeneration Block synchronization Frame synchronization _MAIN/SUB _MAIN _MAIN _MAIN Channel connection/ disconnection _MAIN (R_04) Timer _MAIN Timing interrupt _MAIN (R_00) Tuner MSM9566 Figure 5.1 Main/Subchannel switching receive block diagram...
  • Page 32 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.1.3 Page mode Table 5.1.3 Page mode Address — MAINCH — MOD_ CLRMC0 MOD_ PAGE1 PAGE0 0x3E (Note) _CLRB PARITERC2 _PAGE PAGE Initial value — — Note: The settings MOD_SUB=1 and MOD_MAIN=0 should be made in the register 0x04.
  • Page 33 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.1.4 Main channel clear bit (MAINCH_CLRB) This MAINCH_CLRB bit (DB6 of register 0x3E) has been provided to speed up switching to the main channel. When this bit is set to "1" (MAINCH_CLRB, BIT 6 =1), the main channel synchronization, error correction, DDJ signal processing section, internal frame memory control section, and interrupt will be reset.

  • Page 34: Interrupt Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS INTERRUPT REGISTERS 5.2.1 Interrupt register When an interrupt occurs, a "1" is written in this register and the INT Pin is set to the "0" level. After reading out this register, write a "1" in the corresponding bit of this register to clear the interrupt.
  • Page 35 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB0: REAL This bit is not an interrupt. This bit is cleared simultaneously with the receive interrupt after the first horizontal error correction _MAIN when a "1" is written in DB1. 1: Indicates that the received packet is a REAL packet.

  • Page 36: Receive Data Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS RECEIVE DATA REGISTERS When data is received, that fact is reported by generating an interrupt and setting the INT pin to the "0" level, after which the received data should be read out from the receive data port. The...
  • Page 37 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB0: MAINB/SUB 1: The receive port after the first horizontal error correction is connected to the RAM (LIBF_SUB) for the subchannel. 0: The receive port after the first horizontal error correction is connected to the RAM (LIBF) for the main channel.
  • Page 38 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS BYTE0 DB7: CRC0 1: Indicates that there is an error in the CRC of the packet after the first horizontal error correction. 0: Indicates that the CRC of the packet is normal after the first horizontal error correction.
  • Page 39 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB5: INT0 This bit indicates the receive interrupt after the first horizontal error correction. Even though this bit indication is made in the reception condition after the second horizontal correction, it is possible to confirm that reading has been made when a receive interrupt has occurred after the first horizontal error correction.
  • Page 40 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.3.3 Conditions of receive interrupt after the first horizontal error correction Table 5.3.3.1 Conditions of receive interrupt after the first horizontal error correction Address MOD_ MOD_CH MOD_ MOD_ MOD_ MOD_ MOD_ SISEL 0x34...
  • Page 41 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.3.4 Specification of SI (Service identifier) Table 5.3.4 SI Specification Address (Note 1) 0x35 SI15 SI14 SI13 SI12 SI11 SI10 (Note 2) Initial value Note 1: The setting SISEL=0 should have been made in the register 0x34.
  • Page 42 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Figure 5.3 Access prohibited segments of the frame memory (R_38) The frame memory access inhibited time occurs when the intersection of the packet number and the byte number correspond to the hatched parts in the follwoing figure.
  • Page 43 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Precautions in reading the packet number and byte number Since the microcontroller and data clocks are not mutually synchronized, it is possible that wrong values are read out when reading out is made when the packet number or the byte number is changing.
  • Page 44 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.3.6 Data configuration of the receive frame memory after the second horizontal error correction Table 5.3.6.1 Receive frame memory data configuration after the second horizontal error correction Byte No. Packet No. · ·...
  • Page 45 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB5: RECCRC 1: Indicates that there is an error in the CRC of the received packet before error correction. 0: Indicates that the CRC of the received packet is normal before error correction.
  • Page 46 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB4: CRC2 1: Indicates that there is an error in the CRC of the packet after the second horizontal error correction. 0: Indicates that the CRC of the packet is normal after the second horizontal error correction.
  • Page 47 The readable frame memory address (packet number) is selected from the registers 0x3C and 0x3D. 1: Enables the MSM9566 to read the address (packet number) of the receive data packet that is being written. 0: Enables an external microcontroller to read the address (packet number) of the receive data packet that is being accessed.
  • Page 48 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.3.8 Receive frame memory pointer after the second horizontal error correction Table 5.3.8.1 Frame memory address (1/3) Address — — 0x3B BYTE5 BYTE4 BYTE3 BYTE2 BYTE1 BYTE0 Initial value — — Table 5.3.8.2 Frame memory address (2/3)
  • Page 49 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Read (PCTL1BL2=0) It is possible to know the byte number and the packet number of the data to be read next by reading these registers 0x3B, 0x3C, and 0x3D. However, it is necessary to set PCTL1BL2 of the register 0x39 to "0". Before reading these registers.

  • Page 50: Timing Interrupt Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS TIMING INTERRUPT REGISTERS There are the two timing interrupts of TIMINT_MAIN which operates in synchronization with the main channel and the timing interrupt TIMINT_SUB which operates in synchronization with the subchannel. The block diagram of TIMINT_MAIN is shown in Figure 5.4.1.
  • Page 51 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.4.1 Timing interrupt mode Since some of the interrupt timing registers have been mapped to the same address, this register controls their selection and timing enable conditions. Table 5.4.1 Interrupt timing mode Address —...
  • Page 52 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.4.2 Interrupt byte number specification (main channel) Table 5.4.2.1 Interrupt timing _MAIN (byte number 1/2) Address BCK7 BCK6 BCK5 BCK4 BCK3 BCK2 BCK1 BCK0 INTBCK7 INTBCK6 INTBCK5 INTBCK4 INTBCK3 — — — 0x16...
  • Page 53 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Table 5.4.3.2 Interrupt timing _MAIN (packet number 2/2) Address ACTMC0 ACTMC2 ACTMC1 ACTMC0 — — — FRCK8 _SUB 0x1E — — — — — — (Note 1) ALLFRCKTIM FRCK8 Initial value — —...
  • Page 54 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Table 5.4.4.2 Interrupt timing _SUB (byte number 2/2) Address — — — — — — — PRE_BCK8 (Note 1) _SUB — — — — — — — BCK8 0x07 (Note 2) _SUB —...
  • Page 55 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Read FRCK8_SUB (MSB) to FRCK0_SUB (LSB) indicate the packet number of the packet being received. (FRCK8_SUB is allocated to DB0 of the register 0x09.) Write (FRCK8_SUB to FRCK0_SUB) This is the register for specifying the initial value of the packet number in the subchannel packet counter.
  • Page 56 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Write (INTFNCK0_SUB to INTFNCK3_SUB) This is the register for specifying the subchannel interrupt frame number. The range of setting is 0 to 15. Carry out the settings of TIMINTEN_SUB and SETINTCK of the register 0x05 before setting this register.

  • Page 57: Clock Regeneration Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS CLOCK REGENERATION REGISTERS 5.5.1 Fixed phase Table 5.5.1 Fixed phase adjustment Address — 0x0B Initial value — The phase of the regenerated data clock is adjusted. Use with the initial value left unchanged.
  • Page 58 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.5.4 Phase correction step Table 5.5.4 Phase correction step Address — — 0x0E Initial value — — This register is used for setting the phase correction step width of the digital PLL for data clock regeneration.

  • Page 59: Block Synchronization Registers

    — This is a specification related to the synchronization and clock regeneration processing of the MSM9566, and consists of the specification of the allowable number of error bits in the block identification code (BIC). DB1 to DB0: Allowable number of BIC errors before block synchronization (common to main...
  • Page 60 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.6.2 Number of block synchronization backward protection steps Table 5.6.2 Number of block synchronization backward protection steps Address — — B1_SUB B0_SUB — — 0x11 Initial value — — — — This register is used for setting the number of successive detections of the block identification code (BIC) before considering that a block has been synchronized.
  • Page 61 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.6.3 Number of block synchronization forward protection steps Table 5.6.3 Number of block synchronization forward protection steps Address B3_SUB B2_SUB B1_SUB B0_SUB 0x12 Initial value Write This register is used for setting the number of successive detection failures of the block identification code (BIC) before considering that the block has been synchronized.
  • Page 62 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.6.4 Block synchronization monitor Table 5.6.4 Block synchronization monitor Address — — — BSYNC_SUB — — — BSYNC 0x13 Initial value — — — — — — DB0: Main channel block synchronization state...

  • Page 63: Frame Synchronization Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS FRAME SYNCHRONIZATION REGISTERS 5.7.1 Number of frame synchronization backward protection steps Table 5.7.1 Number of frame synchronization backward protection steps Address — — — — — — 0x18 Initial value — — —...
  • Page 64 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Read When synchronization points cannot be detected successively in a frame synchronization state, the number of detection failures is decremented from the set number of frame synchronization forward protection steps, and when the value of this register changes from 1 to 0, the frame is considered to have been out-of-synchronization.

  • Page 65: Error Correction Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS ERROR CORRECTION REGISTERS The first horizontal error correction, vertical error correction, and the second horizontal error correction have been automated. The results of correction and CRC can be read together with the receive data from the receive port after the first horizontal error correction and the receive port after the second horizontal error correction.
  • Page 66 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.8.4 Number of corrections and error correction results Table 5.8.4 Number of corrections and error correction results Address Result of Result of Second First — — — — second first horizontal horizontal horizontal...

  • Page 67: Ddj And Layer 4 Crc Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DDJ AND LAYER 4 CRC REGISTERS The MSM9566 automatically processes DDJ signals by setting the DDJ mode when horizontal error correction or layer 4 CRC is executed. 5.9.1 Layer 4 CRC/DDJ mode Table 5.9.1 Layer 4 CRC and DDJ mode...
  • Page 68 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Read DB7: L4CRCOUT (Display of layer 4 CRC result) 1: There is an error in the layer 4 CRC result. Ignor the following (2) and (3). 0: The layer 4 CRC result is normal.
  • Page 69 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.9.3 Layer 4 CRC result Table 5.9.3 Layer 4 CRC result Address — — — — — — — L4CRC 0x2A result Initial value — — — — — — — DB0: L4CRC result...
  • Page 70 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.9.5 DDJ prefix Table 5.9.5 Layer 4 DDJ prefixes Address 0x2D Initial value Write Write prefixes to this register when layer 4 CRC/DDJ mode is used. First, execute CLRPFIX for the register at 0x28, and write prefixes of the last packet sequentially (4 bytes).
  • Page 71 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS From layer 4 data group editing CLRPFIX Layer 4 VICS R_28=0xE4 initial setting Write prefixes of Set layer 4 VICS the last packet mode R_2D=Prifix_0 R_28=0xC0 R_2D=Prifix_1 R_2D=Prifix_2 R_2D=Prifix_3 To layer 4 data...
  • Page 72 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS From layer 4 data group editing Clear layer 4 CRC process circuit R_2B=0x00 R_2C=0x00 Write layer 4 data group R_29=L4Data(i) Layer 4 data group complete? CRC result? R_28&0x01==0 Layer 4 data group editing complete Figure 5.9.2 Mode other than layer 4 CRC/VICS mode...

  • Page 73: Analog Test Register

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5.10 ANALOG TEST REGISTER Table 5.10.1 Analog test Address — DET0 SGAIN1 SGAIN0 DETC 0x30 DTST Initial value — DB0: DETC For testing purposes only. Use normally with DETC=0. DB2 to DB1: SGAIN1 to SGAIN0 These set the variable gain amplifier for the analog signal input (composite signal).

  • Page 74: Power Down Register

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB6: DEST0DTST For testing purpose only. Normally use with the setting DB6=0. DET (data identification circuit) input control (DETODTST) (DETC) AIN pin input enable (FM multiplex broadcast reception) ADETIN pin input enable (analog input) ADETIN pin input enable (digital input) 5.11...

  • Page 75: Test Control Registers

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS DB1: Digital section power down 0: The power is down and the internal clock stops at the "H" level. 1: The power is turned on and the clock for operating the digital section starts from the "H"...

  • Page 76: Extension Port Register

    MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS Note 3: BIC Detection BICDET1 BIC1 BIC0 BIC NO. — — Not detected 5.12.2 Test control 1 Table 5.12.2 Test Control 1 Address Delay Delay Clock Serial Differential — Serial output PN Decoding...
  • Page 77 MSM9566 User’s Manual Chapter 5 CONTROL REGISTERS 5-48...

  • Page 78: External Connection Example

    Chapter 6 EXTERNAL CONNECTION EXAMPLE...
  • Page 80 MSM9566 User’s Manual Chapter 6 EXTERNAL CONNECTION EXAMPLE EXTERNAL CONNECTION EXAMPLE MSM9566 interface Tuner section ADETIN 330 pF (±10%) XOUT 32 2.2 mF (Note 1) – XTAL2 30 15 pF 8.192 MHz crystal (Note 3) XTAL1 29 15 pF (Note 2) (Note 2) 2.2 mF (Note 1)
  • Page 81 MSM9566 User’s Manual Chapter 6 EXTERNAL CONNECTION EXAMPLE...

  • Page 82: Application Circuit

    Chapter 7 APPLICATION CIRCUIT...
  • Page 84 MSM9566 User’s Manual Chapter 7 APPLICATION CIRCUIT APPLICATION CIRCUIT Antena tuner 8 bits FM multiplex data demodulation (ROM) MSM9566 Font LCD control SRAM driver LCD display (16 kanji characters ¥ 2 lines)
  • Page 85 MSM9566 User’s Manual Chapter 7 APPLICATION CIRCUIT...
  • Page 86 APPENDIX...
  • Page 88 MSM9552/9553 (reference) MSM9562/9563/9566 Register Initial Recommended Page Initial Recommended Register Category Register name R/W Category Register name address value value value value address 0x00 Interrupt Interrupt cause 0-000000 — Interrupt Interrupt register 0000-000 — 0x00 0x01 Interrupt mask --000000 — Interrupt mask 0000-00- —...
  • Page 89 MSM9552/9553 (reference) MSM9562/9563/9566 Register Initial Recommended Page Initial Recommended Register Category Register name R/W Category Register name address value value value value address 0x20 Error Internal address counter clear xxxxxxxx — Error Internal address counter clear 5-36 ------00 — 0x20 0x21 correction Data transfer port for error correction...
  • Page 90 MSM9566 User's Manual First Edition: December 1999 © © © © © 1999 Oki Electric Industry Co., Ltd. PEUL9566-01...

Table of Contents