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'
L
'
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.
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'
:
~
...
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Table 4-2.
Wo r d I I (con t • )
BIT ASSIGNMENT
DESCRIPTION OF USE
271 281 29
Bandwidth Selection
~
~
~
1~
Hz
~
~
1
4~
Hz
~
1
~
55 Hz
~
1
1
75 Hz
1
~
~
1~5
Hz
1
~
1
145 Hz
1
1
"
2~~
Hz
1
1
1
33~
Hz
3~
I
31
Mode
- -
~
~
Mark Only
~
1
Mark
&
Space
1
~
Space Only
4.3.8
High Level Keyers
The optional
loop printed circuit board contains the loop
supply and the keying circuits for high level keying.
The loop
supply is a
full wave reetifier which produces a by-polar
55 volt output •
The
board
also
contains
the
keying
circuits
for
both
demodulator units.
Incorporated in the keyers is a delay clock
circuit which prevents both keyers from being active at the
same time.
This is a protection feature which will prevent
possible damage caused due to activation of the mark and space
keyers simultaneously.
4-15
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